JP2720695B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise reducer for removing a noise of a video signal by utilizing a correlation of a field used in a video disk player and the like, and a TBC (Time Base Corrector) for removing a time axis fluctuation of the video signal.
The present invention relates to a video signal processing device in which a time-axis fluctuation removing circuit called a “time-axis fluctuation removing circuit” is combined.

[0002]

2. Description of the Related Art In recent years, it has been desired to improve the image quality of devices that handle video signals such as video disk players, and there has been an increasing demand for a TBC for removing fluctuations in the time axis and a noise reducer for removing noise effectively. I have. Hereinafter, a conventional TBC and a noise reducer combined therewith will be described with reference to FIG.

Reference numeral 30 denotes a TBC for removing a time axis error of a video signal. The video signal having time axis fluctuation is A /
The digital signal is converted by the D converter 13 and
Is written to. At this time, the time axis error of the video signal converted by the A / D converter 13 is detected by the time axis error detection circuit 37, and the error controls the write clock generation circuit 14. As a result, the video signal is A / D-converted by the clock following the error and written to the memory 15. If the written video signal is read with a fixed clock, a video signal from which the time axis error has been removed can be obtained, but since the write clock is created by feedback control, it cannot completely follow the time axis error of the video signal, Time axis fluctuation remains. Therefore, the phase of the read clock generator 35 is controlled at the time of reading, and the time axis fluctuation remaining at the time of writing is removed by feedforward control.

In this way, if the video signal read from the memory 15 is D / A-converted, a video signal having no fluctuation in the time axis can be obtained. In this example, in order to improve the S / N of the video signal, Further, a noise reducer 31 is connected in cascade. Since the noise reducer 31 performs digital processing, the D / A converter 36 is connected after this.

In the noise reducer 31, the memory 1
The video signal from 5 is input to the subtractor 2 and then delayed by a delay circuit 7 for one field period. The delayed signal is subtracted from the input by the subtractor 5, and returns to the subtractor 2 through the limiter 21. The output of the subtractor 5 is a noise reducer 31
Is a difference signal between the signal delayed by one field and the input video signal, that is, a correlation signal. Since the limiter 21 passes only when the signal is small, it is not fed back when there is no correlation, so that the afterimage can be suppressed and the S / N can be improved. Finally, the output of the noise reducer 31 is D / A converted by the D / A converter 36 and output.

An example of a noise reducer is “Digital Signal Processing of Images” (by Nikkan Kogyo Shimbun, Nobuhiko Fuukiki), p.
5-P118.

[0007]

However, in the above-described conventional configuration, when the signal processed by the noise reducer 31 is D / A converted, the D / A is converted by a phase-modulated clock.
Since the phase modulation is generated by controlling the read clock 35 in accordance with the time axis variation of the video signal input to the A / D converter 13, the phase modulation of the video signal processed by the noise reducer 31 is performed. Since it does not correspond to time axis fluctuation, there is a disadvantage that the time axis fluctuation is increased by phase modulation.

The present invention solves the above-mentioned conventional problems. A noise reducer is further effectively connected in cascade to a TBC which performs phase modulation of a read clock and performs high-performance time-axis fluctuation removal by feedforward correction. It is an object of the present invention to provide a video signal processing device capable of performing the above.

[0009]

In order to achieve this object, a video signal processing apparatus according to the present invention provides an error signal for adding time-axis error information of a video signal during a horizontal blanking period of a digitally converted video signal. The video signal to which the time axis error information has been added by the data adding circuit and the error data adding circuit is delayed by n (n is a natural number) fields and fed back to the input to smooth the signal. A noise reducer that switches between a period in which the time axis error information is added and a period other than the period, a D / A converter that converts an output of the noise reducer into an analog signal, and a noise reducer that converts the output of the noise reducer into an analog signal. A data separation circuit for separating the processed time axis error information,
A clock generation circuit that modulates the phase of a clock according to the output of the data separation circuit and supplies the clock to the D / A converter.

[0010]

According to the present invention, a noise reducer is directly connected after a TBC, and a clock for D / A conversion is phase-modulated by the above-described configuration to effectively remove time-axis fluctuations and S / N of a video signal. Improvement can be realized.

[0011]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a video signal processing apparatus according to a first embodiment of the present invention. In FIG. 1, the input video signal is subjected to time-base fluctuations by a TBC 12. The operation of the TBC 12 is the same as that of the conventional TBC 30, except that the read clock of the memory 15 is generated by the read clock generation circuit 9;
That is, the error data adding circuit 17 is provided.

The error data adding circuit 17 is a circuit for adding the time axis error data detected by the time axis error detecting circuit 16 as data during the horizontal blanking period of the video signal. FIG. 2 shows an example of a video signal waveform to which time axis error data is added. The time axis error data is added in a form that is replaced by a certain period in the horizontal synchronizing signal period, and the level indicates the time axis error. Next, the video signal to which the time axis error data has been added is processed by the noise reducer 1.

The difference between the noise reducer 1 and the conventional example is 2
Two limiters 3 and 4 are provided, and a switch circuit 11 for switching the outputs of the limiters 3 and 4 is provided. The switch circuit 11 switches the limiters 3 and 4 only during the period of the time axis error data added to the video signal described above by the timing generation means 6. For example, the error data period is defined as limiter 4, and other than that, that is,
The video signal period is switched to the limiter 3. The limiters 3 and 4 have different gains. That is, the noise reducer also processes the time axis error data, and the feedback coefficient at that time is changed to the video signal. The time axis error data thus processed is finally separated by the data separation circuit 8, the clock of the read clock generation circuit 9 is phase-modulated based on the error, and the clock is converted to the D / A converter 10 and the memory 15. To supply. The meaning of phase-modulating the clock for D / A conversion by such a method will be described next with reference to FIG.

FIG. 3A shows a time axis fluctuation of a video signal, and FIG. 3B is a circuit for explaining a time axis fluctuation amount after processing a video signal having a time axis fluctuation. In (b), the input signal A is delayed by 1H (H is a horizontal synchronization period) by the delay circuit 40, added by the adder 41, halved by the coefficient circuit 42, and output. In such a circuit, A of (a)
It is assumed that a video signal having a time-axis variation indicated by is input and processed. Since the time axis fluctuation of the signal B delayed by 1H is also delayed by 1H, the time axis fluctuation as indicated by B in FIG. Accordingly, the time axis fluctuation of the signal obtained by averaging A and B is as shown by the solid line in FIG.

By the way, the time axis fluctuation of the video signal is (a)
As shown in (1), the time axis fluctuation can be detected from the video signal only with the burst signal or the horizontal synchronizing signal. That is, it can be detected only once in 1H. A circle indicates this detection point. As can be seen from this figure, the time axis fluctuation amount at the detection point of the signal passing through the circuit (b) is the average of the time axis fluctuation amount at the detection point of the input signal and the time axis fluctuation amount of the detection point 1H before. is there. However, in the present invention, the time axis error data is superimposed in the horizontal synchronization period of the video signal as described with reference to FIG. 2, so that the time axis data is automatically processed at the same time as the video signal through the circuit of FIG. You.
That is, the time axis error data of the output of the circuit in FIG. 9B corresponds to the time axis fluctuation of the video signal.

Up to this point, the time axis fluctuation has been described with reference to the circuit of FIG. 3B as an example. Next, processing when the signal passes through the noise reducer 1 will be described. Noise reducer 1
In the case of, the circuit can be basically considered in the same manner as the circuit described above. However, in the noise reducer 1, limiter circuits 3 and 4 are provided in the feedback loop as described above,
The feedback coefficient is changed adaptively. For this reason, the way in which the input video signal is averaged changes constantly, so that the time axis error data cannot be processed with the same coefficients as the video signal as in the previous example. However, since the noise reducer 1 is a circuit that qualitatively averages the video signal, the time axis fluctuation of the averaged video signal output is also averaged. Therefore, a coefficient for the time axis error data optimal for the feedback coefficient of the video signal is experimentally determined and set in the limiter 4. Then, the timing generator 6 switches to the limiter 4 only for the feedback of the time axis error data, so that the optimal processing for the time axis error data is performed. By separating this data by the data separation circuit 8 and phase modulating the clock of the read clock generation circuit 9, accurate feedforward correction can be performed.

[0018]

As described above, according to the present invention, the time axis error data added to the horizontal synchronization signal is processed simultaneously with the video signal by the noise reducer, and the feedback coefficient for the time axis error data at that time is converted to the feedback coefficient for the video signal. In other words, there is an effect that the clock at the time of D / A conversion is phase-modulated based on the error data of the output video signal, and high-performance time-axis fluctuation can be removed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video signal processing device according to an embodiment of the present invention.

FIG. 2 is a waveform chart showing time axis error data in the embodiment.

FIG. 3 is a waveform diagram and a block diagram showing an example of arithmetic processing in the embodiment, and a time axis error subjected to arithmetic processing;

FIG. 4 is a block diagram showing a configuration of a conventional video signal processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Noise reducer 3, 4 Limiter 9 Read clock generation circuit 12 TBC 14 Write clock generation circuit 15 Time axis error detection circuit 17 Error data addition circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Inoue 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-1-318374 (JP, A)

Claims (4)

(57) [Claims] 1. An error data adding circuit for adding time axis error information of a video signal to a digitally converted video signal during a horizontal blanking period, and a video to which time axis error information is added by the error data adding circuit. A noise reducer that delays a signal by n (n is a natural number) fields, feeds back the signal to the input, smoothes the signal, and switches a feedback coefficient at the time of feedback between a period in which the time axis error information is added and a period other than the period. A D / A converter that converts an output of the noise reducer into an analog signal; a data separation circuit that separates time axis error information processed by the noise reducer from an output of the noise reducer; A clock generation circuit that modulates the phase of a clock according to the output and supplies the clock to the D / A converter. Image signal processing device. 2. A noise reducer comprising: a first subtraction circuit for subtracting a second signal from an input signal; a delay circuit for delaying an output of the first subtraction circuit by n (n is a natural number) fields; A second subtraction circuit that subtracts an input signal from an output of the circuit; a first and second limiter circuit that passes a signal only when the output of the subtraction circuit is small and has a different gain; and a first and second limiter. The video signal processing device according to claim 1, further comprising: a switch circuit that switches an output of a limiter circuit and supplies the output to the first subtraction circuit as the second signal. 3. An A / D converter for A / D converting an input video signal.
A D converter, a memory in which the output of the A / D converter is written and data can be read with a clock independent of writing, a time axis error of the video signal A / D converted by the A / D converter A time-axis error detector for detecting the time-varying error, and a write controlled to the output of the time-axis error detector and generating a write clock to the memory following the time-axis variation of the input video signal to the A / D converter. A clock generation circuit, an error data addition circuit for adding a time axis error detected by the time axis error detector to a horizontal synchronization period of the video signal read from the memory, and a time axis error in the error data addition circuit. The information-added video signal is delayed by n (n is a natural number) fields and fed back to the input to smooth the signal, and the feedback coefficient at the time of feedback is determined by the time period during which the time-axis error information is added and the feedback coefficient. A noise reducer that switches in a period other than the above, a D / A converter that converts the output of the noise reducer into an analog signal, and a data separation circuit that separates the time axis error information processed by the noise reducer from the output of the noise reducer A video signal processing apparatus comprising: a clock generator that modulates the phase of a clock in accordance with an output of the data separation circuit and that is supplied as a read clock for the memory. 4. A noise reducer comprising: a first subtraction circuit for subtracting a second signal from an input signal; a delay circuit for delaying an output of the first subtraction circuit by n (n is a natural number) fields; A second subtraction circuit for subtracting an input signal from an output of the circuit; a first and second limiter circuit for passing a signal only when the output of the subtraction circuit is small and having different gains; 4. The video signal processing device according to claim 3, further comprising: a switch circuit that switches an output of a limiter circuit and supplies the output to the first subtraction circuit as the second signal.