JP2703554B2 - Time axis correction device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a time axis correction apparatus, and more particularly to an apparatus for correcting a time axis error of a video signal.

2. Description of the Related Art A video signal reproduced by a recording information reproducing apparatus such as a video disc player or a VTR includes a time axis error generated due to rotation unevenness of a mechanical system. Since such fluctuations and color unevenness have an adverse effect, it is necessary to remove this time axis error as much as possible in the video signal processing system.

By the way, there is a video signal reproducing apparatus by the present applicant in which all processing of reproduced video signals is performed digitally (see Japanese Patent Application Laid-Open No. 62-140587), and a conventional time axis correction apparatus in this video signal reproducing apparatus. Will be described below with reference to FIG.

In the figure, an FM video signal read from a recording medium such as a video disk is supplied to an A / D converter 2 via an analog LPF (low-pass filter) 1. LPF1 is for removing aliasing distortion in A / D conversion. The digitized FM video signal output from the A / D converter 2 is supplied to the RF processing circuit 7. This RF processing circuit 7
A digital BPF (band-pass filter) 3 for extracting only components necessary for detecting a video signal from an A / D conversion output including an FM audio signal, a digital FM detection circuit 4 for FM-detecting the components, It comprises a video LPF 5 for extracting only the baseband component of the video signal from the detection output of the circuit 4 and a dropout detection circuit 6 for detecting a dropout of the video signal. The digitized video signal that has passed through the video LPF 5 is supplied to a dropout correction circuit 8 and a PLL (phase locked loop) circuit 9.

The dropout correction circuit 8 performs dropout correction in response to the dropout detection signal supplied from the dropout detection circuit 6. PLF circuit 9 is video LPF5
4N ₁ fs synchronized with digitized video signal supplied from
c (N ₁ is an integer greater than or equal to 2, for example, 4, fsc is a is color subcarrier frequency) for generating a master clock f _M of the frequency. Master clock f _M is used as a clock of the digital signal processing of up-sampling clock and video LPF5 the A / D converter 2. N ₁ frequency divider 10 is the master clock f _M and 1 / N1 frequency division of the frequency of 4fsc clock WCK
, And this clock WCK becomes a clock for downsampling in the video LPF 5 and a sampling clock for the dropout correction circuit 8. The digitized video signal output from the dropout correction circuit 8 is written to the buffer memory 12 by the clock WCK.
Reading of data from the buffer memory 12 is performed by a 4 fsc reference clock RCK generated by the reference signal generation circuit 11. The digitized video signal read from the buffer memory 12 is converted into an analog signal by the D / A converter 13 and becomes a reproduced video signal output.

As described above, by writing the reproduced video signal to the buffer memory 12 with the clock that follows the jitter of the reproduced video signal, and reading out the data from the buffer memory 12 with the stable reference clock that does not follow the jitter of the reproduced video signal, It is possible to absorb the jitter of the reproduced video signal. The phase error of the PLL at this time becomes the residual time axis error. That is, assuming that the open loop gain of the PLL is G, the time axis error is reduced to 1 / (1 + G).

However, in such a feedback loop by the PLL, the loop band is limited by the phase comparison period T = 1 / f _H (f _H is the horizontal scanning frequency and 15.734 KHz).
As the frequency increases, the open-loop gain decreases, and the ability to remove high-frequency components (about 1 KHz or more) of the time axis error decreases. When trying to increase the open loop gain near 1 KHz, the phase margin decreases, and
Peaks will occur at frequencies above 3 KHz. 2-3K
At frequencies above Hz, the true time axis error component is small and the noise and phase comparator error components contained in the video signal are large, so the peak of the closed loop characteristic amplifies these noises and errors, resulting in the time axis error. This will increase the error.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to provide a time axis correction device having good correction characteristics even for a high frequency component of a time axis error.

The time axis correction apparatus according to the present invention is configured to open the feedback loop in a high frequency region of the time axis error component by removing the time axis error component which cannot be completely removed by the feedback loop for performing the time axis correction of the input signal. The signal is input to a filter having an amplitude characteristic similar to the characteristic, and the signal obtained by performing phase control on the input signal by a feedback loop is further subjected to time-forward correction by feedforward using the output of the filter.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a video signal reproducing apparatus having a time axis correcting apparatus according to the present invention, for example, having a configuration for performing signal processing digitally. The device shown in the figure is obtained by adding a variable delay device 14 to the device shown in FIG. 7, and the same blocks as those in FIG. 7 are denoted by the same reference numerals. In the variable delay device 14, a time axis correction is performed on the digitized video signal supplied from the dropout correction circuit 8 using a phase error signal from the PLL circuit 9. In a steady state, the phase error signal of the PLL is detected by a color burst.

In time base correction by PLL, a sampling clock (f _M, WCK) generated in PLL although components could not follow the jitter of the video signal is the residual time base error, the variable delay device 14 without changing the sampling clock In addition, the residual time axis error is canceled by feedforward by changing the delay amount of the video signal according to the phase error of the PLL. The video signal whose residual time axis error with respect to the sampling clock WCK has been canceled by the variable delay device 14 is written into the buffer memory 12 by the sampling clock WCK, and read out by the reference clock RCK in the same manner as the device of FIG. Then, the correction of the time axis error is completed.

FIG. 2 is a block diagram showing an equivalent circuit of the time axis correction system in FIG. In the figure, reference numeral 21 denotes a PLL phase comparator, reference numeral 22 denotes a noise adder equivalently representing the addition of a noise component, and reference numeral 23 denotes a block representing the open loop characteristic of the PLL. Time axis correction is being performed. Reference numeral 24 denotes a filter which receives the output of the noise adder 22 as an input and outputs a feedforward correction signal, 25 denotes a delay circuit having the same delay amount as the filter 24 and a transfer function represented by D, and 26 denotes a correction adder. These correspond to the variable delay device 14 in FIG.
Time axis correction by feed forward is performed.
θi is the jitter of the reproduced video signal, but due to the noise component included in the reproduced video signal and the error component of the phase comparator 21, the noise adder 22 equivalently adds the time noise component θn to the phase error. Is fed back into the PLL loop. From the figure, the time axis correction output θc is expressed by the following equation.

Since θc is delayed from θi by the transfer function D, the residual time axis error θce after time axis correction by feedback and feedforward is expressed by Dθi−θc. By substituting the above equation (1), It looks like an expression.

Since θi and θn have little correlation, both (D−H) θi and (H + DG) θn must be close to 0 to make θce close to 0. Focusing on the frequency components, the value of θi is largely dominant in the low band, and θn is dominant and the value of θi is small in the high band.

If the open loop gain of the PLL is set to a large value up to about 1 KHz, the error response of the closed loop becomes 1/2 due to lack of phase margin in a high frequency region of 2 to 3 KHz or more near G becomes 0 dB.
A peak occurs at (1 + G), and as a result, θn is amplified in a high frequency range. Therefore, in the above equation (2), θ
In the low range where i is sufficiently large, the term of θi can be brought close to 0 by bringing the term of θn close to 0 in the high range where θi is sufficiently small. That is, it is sufficient that H ≒ D in a low band and H 、 -DG in a high band. Further, D is | D | = 1 and the delay characteristic is the same as H, and G ≒ − | G | in the high band. Therefore, to satisfy the above condition, H is | H | ≒ 1 in the low band. ,
It is sufficient if the function is such that | H | ≒ | G | As such a function, for example, the following may be selected.

Here, T = 1 / f _H , and Z ⁻¹ represents a delay of one sample at the clock of f _H. Further, the second product term is a hold function. This H has a linear phase and a constant delay amount Z ^-1 . Therefore, D = Z ^-1 . Further, the amplitude characteristic conforms to the above conditions as shown in FIG.

FIG. 4 shows a specific circuit configuration of the variable delay device 14 in FIG. 1, that is, the filter 24, the delay circuit 25, and the correction adder 26 in FIG. Have. In the figure, 1H delay circuit
Numeral 40 is for delaying the input video signal by one horizontal scanning period, and the delayed video signal becomes one input of the subtractor 41. The subtraction output is supplied to a first register 42. The output of the first register 42 becomes the input of the second register 44 and is supplied to the multiplication circuit 43 of the multiplication coefficient k. The output of the multiplication circuit 43 becomes another input of the subtractor 41 and an adder.
It becomes one input of 45. The output of the second register 44 is an adder 45
And is added to the output of the multiplication circuit 43. This addition output is supplied to an overflow circuit 47 via a third register 46.
After the dynamic range is limited, the video signal is output after being latched by the fourth register 48.

The multiplication circuit 43 has a configuration as shown in FIG.
After the phase error signal in the PLL circuit 9 in FIG. 1 is averaged by the averaging circuit 50, the amplitude is limited by the limit circuit 51 and becomes the address of the RAM 52. The output 1 of the first register 42 in FIG. The RAM 52 outputs a multiplication result k · l of the coefficient k determined by the output of the limit circuit 51 and the output 1 of the first register 42. The multiplication data is stored in the ROM 53 in advance, and is loaded into the RAM 52 when the power is turned on. The output of the RAM 52 becomes another input of the subtractor 41 and the adder 45.

Next, the operation of the variable delay device 14 having such a configuration will be described.

The 1H delay circuit 40 corresponds to the delay circuit 25 in FIG. The averaging circuit 50 averages the phase error of the PLL input for each horizontal scanning line between two horizontal scanning lines, and holds the result for one horizontal scanning period. That is, the averaging circuit 50 has the transfer function of the above equation (3) and operates as the filter 24 in FIG. 2 which receives the phase error component of the PLL as an input. The limit circuit 51 determines a variable range of k, which will be described later, and limits the amplitude of the output of the averaging circuit 50. The output of the limit circuit 51 corresponds to the aforementioned feedforward correction signal.

The subtractor 41, the first register 42, the multiplying circuit 43, the second register 44, and the adder 45 form a first-order all-pass filter (hereinafter abbreviated as APF) having the following transfer function H _A (z). Make up.

Here, k is a multiplication coefficient, and Z ⁻¹ represents one sample delay due to the sampling clock WCK.

In the APF of this circuit, the multiplication coefficient k is variable, and the multiplication coefficient k is
FIG. 6 shows the phase characteristics of the APF when. If the phase delay is θ and the angular frequency is ω, the delay time at each frequency is θ / ω, so it is proportional to the slope of the straight line connecting each point in the figure and the origin, and the phase characteristic, ie, the delay, is determined by the multiplication coefficient k. It can be seen that the characteristics change. The amplitude characteristic is 1 regardless of the value of the multiplication coefficient k. The APF changes the multiplication coefficient k according to the output of the limit circuit 51, and the 1H delay circuit 40
It operates as the correction adder 26 shown in FIG. 2 which changes the delay time of the video signal output from the FB and performs time axis correction by feedforward.

The multiplication result k · l of the first register output 1 and the variable multiplication coefficient k in the multiplication circuit 43 is obtained by a table look-up method. That is, the multiplication result k · l of the multiplication coefficient k according to the output of the limit circuit 51 and the register output l
Is loaded from the ROM 53 to the RAM 52 in advance, and k · l is read from the RAM 52 using the register output 1 and the output of the limit circuit 51 as the address input of the RAM 52. In addition, the multiplication by the above-mentioned variable coefficient is performed by combining a plurality of shifters each shifting by a different number of bits and a plurality of adders simply adding up all the shifter outputs in order to reduce the circuit scale when the circuit is formed into an LSI. The coefficient may be changed by turning ON / OFF the addition of each shift output. Or,
If the limitation of the circuit scale is relatively moderate and the operation speed is sufficient, the multiplier may be used as it is after converting the output of the limit circuit 51 into the value of the corresponding multiplication coefficient k.

The output of the adder 45, which is the APF output, is latched by a third register 46, and the overflow circuit 47 calculates an n-bit portion for a portion where the dynamic range exceeds the range of n (for example, n = 8) bits by an operation in the APF. It is limited to the dynamic range, latched by the fourth register 48, and output. Note that all the registers in FIG. 4 operate with the sampling clock WCK.

In the above embodiment, the first-order APF is used for the time axis correction by the feed forward.
Other circuits such as APF of the above integer) may be used.

Further, in the above-described embodiments, the case where the present invention is applied to a video signal reproducing apparatus based on digital processing is described. However, the present invention is also applicable to a video signal reproducing apparatus based on analog processing.

Further, the input signal is not limited to the video signal, and the present invention is applicable to any signal having a time axis error mainly composed of low frequency components, and has the same effect as the above embodiment. Play.

Effects of the Invention As described above, according to the time axis correction device of the present invention, the time axis error component that cannot be completely removed by the time axis correction by the feedback loop is fed back to the feedback
Input to a filter with high-frequency amplitude characteristics similar to the open-loop characteristics of the loop, and using this filter output to further correct the time-axis error by feedforward, expand the bandwidth of the feedback loop. The noise component can also be suppressed, and good time axis correction can be performed up to a high frequency range.

In addition, by setting the amplitude characteristic of the filter in the low frequency range of the feedforward correction system to be approximately 1, excellent correction of the time axis error can be performed even in the low frequency range.

Further, when the filter shown in the embodiment is used, the switching point of the multiplication coefficient k enters the horizontal blanking period, so that the switching point is not conspicuous on the screen.

It should be noted that the present invention can be applied to a device that performs all signal processing digitally, and for detecting a time axis error, for example, a phase comparator proposed by the present applicant in Japanese Patent Application No. 62-122183 can be used. Thus, the detection and correction of the time axis error can be performed with high accuracy, and the LSI can be easily formed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a video signal reproducing apparatus having a time axis correction device according to the present invention, FIG. 2 is a diagram showing an equivalent circuit of a time axis error correction system in FIG. 1, and FIG. The figure which shows an example of the amplitude characteristic of the filter in a figure, 4th
4 is a block diagram showing a specific circuit configuration of the variable delay device in FIG. 1, FIG. 5 is a block diagram showing a specific circuit configuration of the multiplication circuit in FIG. 4, and FIG. 6 is a circuit in FIG. FIG. 7 is a block diagram showing the configuration of a video signal reproducing apparatus having a conventional time axis correction device. Explanation of Signs of Main Parts 7 RF Processing Circuit 8 Dropout Correction Circuit 9 PLL Circuit 12 Buffer Memory 14 Variable Delay Device 21 Phase Comparator 24 Filter 25 Delay circuit 42,44,46,48 Register 43 Multiply circuit 50 Averaging circuit 51 Limit circuit

Claims (3)

(57) [Claims] 1. A feedback loop for detecting a time axis error of an input signal and performing time axis correction, and an amplitude characteristic approximate to an open loop characteristic of the feedback loop in a high frequency region of the time axis error component. And a filter having the time-axis error component as an input, and a signal obtained by subjecting the input signal to phase control by the feedback loop, and further performing time-forwarding by feedforward using an output of the filter. An inter-axis axis correcting device for performing axis correction. 2. The time axis correction device according to claim 1, wherein the filter has an amplitude characteristic of approximately 1 in a low frequency region of the time axis error component. 3. The filter has a transfer function of (1 + Z ⁻¹ ) / 2.
3. The time axis correction device according to claim 2, wherein the time axis correction device is represented by a product of a time and a hold function.