JP2908482B2 - Video signal processing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit, and more particularly to a separate (S) Y / C signal for a luminance signal (hereinafter, referred to as Y signal) and a chrominance signal (hereinafter, referred to as C signal). The present invention relates to a video signal processing circuit in a video device provided with a so-called S terminal that independently outputs the signals.

2. Description of the Related Art In video equipment such as a video disk player, a frequency characteristic adjusting circuit is arranged on a signal line of a Y signal, and a high frequency gain of the Y signal is reduced according to a frequency characteristic set by a user's selection, thereby reducing the user's preference. In general, the image quality is adjusted according to the image quality. As the frequency characteristic adjustment circuit, an analog circuit configuration that includes a plurality of stages of low-pass filters and lowers the high-frequency gain or changes the capacitance of the variable capacitance diode as necessary is simple. This adjustment of the frequency characteristics must be performed on the time-axis corrected video signal having no jitter, and the frequency characteristic adjustment circuit is inevitably disposed on the output side of the time axis correction circuit.

By the way, a so-called composite video signal including a synchronization signal such as a horizontal synchronization signal and a vertical synchronization signal obtained by reading and demodulating from a recording medium such as a video disk is corrected by using an image memory to compensate for the time axis fluctuation. However, in this case, the frequency characteristic adjustment circuit cannot be configured by an analog circuit. In addition, in recent years, video equipment having an S terminal for independently outputting a Y signal and a C signal, in addition to a V terminal for outputting a composite video signal, is becoming mainstream. For this reason, video equipment naturally requires a Y / C separation circuit, but since the output of the time axis correction circuit is a digital signal,
It is more advantageous to perform the separation digitally. Thus, the frequency characteristic adjustment circuit having the analog circuit configuration is provided for the analog Y signal after the D / A conversion.

However, when the frequency characteristic adjusting circuit is provided for the analog Y signal, a phase change occurs due to a time constant of the adjusting circuit, and thus a problem occurs that the phases of the Y signal and the C signal do not match. become.

SUMMARY OF THE INVENTION [Object of the Invention] Accordingly, the present invention provides a video signal processing circuit that prevents a phase change between a Y signal and a C signal by inserting a frequency characteristic adjusting circuit for the Y signal. The purpose is to provide.

[Constitution of the Invention] A video signal processing circuit according to the present invention comprises: a time axis correction circuit for digitally correcting a time axis fluctuation of a composite video signal obtained by reading and demodulating from a recording medium;
A Y / C separation circuit for separating the digital composite video signal passed through the time axis correction circuit into a Y signal and a C signal;
What is claimed is: 1. A video signal processing circuit which converts a separated Y signal and a C signal into analog signals and independently derives them as circuit outputs, wherein a frequency characteristic adjustment is performed to adjust a high-frequency characteristic of the analogized Y signals. The circuit includes a circuit and a phase compensation circuit that compensates for the phase of the C signal that has been analogized by the phase change of the Y signal by the frequency characteristic adjustment circuit.

[Operation of the Invention] In the video signal processing circuit according to the present invention, the correction of the time axis fluctuation of the composite video signal and the Y / C separation are digitally performed, and the Y signal and the C signal are each converted into an analog signal and independently output as a circuit output. And analog Y
The image quality is adjusted by adjusting the frequency characteristics of the high frequency range of the signal, and the phase of the analog C signal is compensated for the phase change of the Y signal accompanying the adjustment of the frequency characteristics.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, a read RF signal read from a recording medium (not shown) such as a video disk is supplied to an FM demodulation circuit 2 after passing through an RF amplifier 1 and is subjected to FM demodulation. A composite video signal (hereinafter, simply referred to as a video signal), which is a demodulated output of the FM demodulation circuit 2, is supplied to an A / D converter 3 and a synchronization separation circuit 4. In the sync separation circuit 4, for example, a horizontal sync signal in the video signal is separated and extracted. This horizontal synchronization signal is supplied to the PLL circuit 5. The PLL circuit 5 generates a clock phase-synchronized with the video signal based on the horizontal synchronization signal.

The clock generated by the PLL circuit 5 is applied to the write control circuit 6
At the same time as the conversion clock of the A / D converter 3 and at the same time as the write clock to the line memory 7 at the next stage.
The digital video signal written in the line memory 7 is read out by a read control signal from a read control circuit 9 based on a master clock of a clock oscillator 8, and subsequently read into an image memory 10 by a write control signal from a write control circuit 11. It is written to a predetermined address. The read control signal RCS1 of the line memory 7, the write control signal WCS2 of the image memory 10, and the read control signal RCS2 are all generated based on the master clock by the clock oscillator 8 whose time axis is stable. As described above, the video signal is written to the line memory 7 based on the clock phase-synchronized with the video signal, and is read out based on the master clock whose time axis is stable, so that the video whose time-axis fluctuation (jitter) is corrected. A signal is obtained (time axis correction processing).

The image memory 10 has a storage capacity capable of storing a video signal for one field. Each time a video signal is read from the line memory 7, it is sequentially written to a predetermined address of the image memory 9, and is sequentially read independently of the writing. Control is performed by the write control signal WCS2 from the write control circuit 11 and the read control signal RCS2 from the read control circuit 12. In this case, since the read control signal RCS2 is a signal phase-synchronized with the reference synchronization signal of the reference synchronization signal generator 13, a video signal whose synchronization signal is discontinuous is written to the image memory 10 by a track jump operation by special reproduction. Also, by reading with the read control signal RCS2 which is phase-synchronized with the reference synchronization signal, the video signal can be converted into a video signal synchronized with the horizontal and vertical synchronization signals (synchronization conversion processing).

The digital video signal read from the image memory 10 is supplied to a digital Y / C separation circuit 14,
At 4 the signal is separated into a Y signal and a C signal. Digital Y
As the / C separation circuit 14, a circuit having a well-known circuit configuration can be used, an example of which is shown in FIG. In FIG. 2, the current digital video signal a is multiplied by a coefficient 1/4, and 1H
(H: horizontal scanning period) The digital video signal b 1H before passing through the delay element 15 is multiplied by a factor of 1/2, and the digital video signal c 2H before passing through the 1H delay element 16 is further multiplied by a factor of 1/4.
The signal obtained by multiplying the current digital video signal multiplied by the coefficient 1/4 by the inverter 18 and the coefficient 1/2 by the coefficient 1/2 are obtained. The C signal is introduced by adding in the adder 20 the multiplied digital video signal b 1H before and the digital video signal c 2H before multiplied by the coefficient 1/4 and inverted by the inverter 19. You can do it.

The Y / C separated digital Y signal is converted into an analog Y signal by a D / A converter 21 and then supplied to a noise reduction circuit 22 to be subjected to noise removal processing. As the noise reduction circuit 22, for example, only the noise component is extracted from the original signal (Y signal), the phase is inverted and added to the original signal, thereby canceling the noise component. The one disclosed in Japanese Patent No. 153061 can be used. On the other hand, the Y / C separated digital C signal is subjected to noise removal processing at the digital stage in a noise reduction circuit 23, and then subjected to an analog C / A conversion by a D / A converter 24.
Converted to a signal. As the noise reduction circuit 23, for example, one having the configuration shown in FIG. 3 can be used.

In FIG. 3, the digital C signal a becomes the subtracted input of the subtractor 25 and the added input of the adder 26. The subtracter 25 receives the digital C signal b delayed by one field period in the field memory 27 as a subtraction input, and supplies the subtraction output to the nonlinear circuit 28. The nonlinear circuit 28 is a subtractor 25
Is configured to output data having a predetermined relationship with respect to the subtraction output. Output data of the nonlinear circuit 28 is added to the digital C signal a in the adder 26. The added output of the adder 26 is inverted in phase by the inverter 29 and supplied to the field memory 27.

In the noise reduction circuit 23 having such a configuration,
Digital C signal a output from Y / C separation circuit 14 and digital C signal b read from field memory 27
And a signal obtained by mixing the above with a mixing ratio according to the difference (movement) between the instantaneous values of both signals. That is, when the motion is large, the digital C signal a output from the Y / C separation circuit 14 is dominant, and when the motion is small, the digital C signal one field period earlier read from the field memory 27 is replaced with the digital C signal. The noise is less noticeable by mixing with the signal a.

As described above, the noise is removed at the analog stage for the Y signal and the noise is removed at the digital stage for the C signal for the following reason. That is, the Y signal has a wide range of frequency components, and if digital detection and correction of the noise is required, a large-capacity memory system and complicated control are required. This is because, since the frequency is low and the frequency is single, an effective noise reduction process can be performed with a relatively simple controller and a small-capacity memory.

The Y signal that has passed through the noise reduction circuit 22 is supplied to the frequency characteristic adjustment circuit 30. This frequency characteristic adjustment circuit 30
Is for adjusting the image quality by lowering the gain of the high frequency component of the Y signal in accordance with the set frequency characteristic, and is constituted by, for example, a two-stage low-pass filter as shown in the figure. The frequency characteristics are variable in three stages when both low-pass filters are not operated, when only one is operated, and when both are operated simultaneously. The switching control of this frequency characteristic
This is performed by the controller 32 in response to a user's selection command from the operation unit 31.

By arranging the frequency characteristic adjusting circuit 30 for the Y signal, a phase change occurs due to the time constant of the adjusting circuit 30, and the phase of the Y signal and the C signal is not matched. The phase of the C signal is compensated by arranging a frequency characteristic adjusting circuit 33 having the same characteristic in synchronization with the frequency characteristic adjusting circuit 30. By disposing the frequency characteristic adjusting circuit 33 for the C signal,
Although the gain of the high frequency component of the signal is reduced, there is little practical problem since the ACC circuit provided on the television receiver operates to adjust the gain of the C signal.

The Y signal passed through the frequency characteristic adjustment circuit 30 is a buffer amplifier
It is supplied to a character insertion circuit 35 via. The character insertion circuit 35 is for selectively inserting character information such as characters into the Y signal. The character control signal issued from the controller 32 causes a portion constituting the character in each line of the Y signal to output the Y signal. Is replaced with a predetermined level (white level) + Vcc to insert character information into the Y signal. On the other hand, the C signal that has passed through the frequency characteristic adjusting circuit 33 is supplied to the color extracting circuit 37 via the buffer amplifier 36. The color removal circuit 37 replaces the C signal with the ground level over the insertion period in synchronization with the character insertion operation of the character insertion circuit 35. This color removal circuit
By the operation of 37, the character is prevented from being colored when the character is inserted.

The Y signal into which the character information is inserted by the character insertion circuit 35 is output from the output terminal Yout1 as a Y signal with a character, and the C signal from which the color component is removed by the color extraction circuit 37 is output from the output terminal Cout1 as a color extraction C signal. , For example, the input from the S terminal of the revision receiver. On the other hand, Y, C on each input side of the character insertion circuit 35 and the color removal circuit 37
The signal is output from the output terminals Yout2 and Cout2 as a separate Y / C signal without a character, and is used, for example, for dubbing. A composite video signal obtained by adding the character-added Y signal and the color-removed C signal by the adder 38 is output as a composite video signal with a character from an output terminal Vout1 and becomes, for example, a V terminal input of a television receiver.
Y, on each input side of the character insertion circuit 35 and the color removal circuit 37
The composite video signal obtained by adding the C signals to each other by the adder 39 is output from the output terminal Vout2 as a composite video signal without a character, and is used for, for example, dubbing.

In the above embodiment, the frequency characteristic adjusting circuit 30
As an example, a low-pass filter having a plurality of stages (two stages in this example) is used. However, the present invention is not limited to this. For example, a configuration in which the capacitance is changed using a variable capacitance diode is used. It may be.

As means for compensating the phase of the C signal, a frequency characteristic adjusting circuit having the same characteristics as the frequency characteristic adjusting circuit 30 is used.
Although 33 is used, the present invention is not limited to this, and an equalizer may be arranged in the C signal line to compensate for the phase shift from the Y signal. At this time, as an equalizer, a so-called all-pass network in which the amplitude is constant irrespective of the frequency and only the phase is changed (Japanese Patent Laid-Open No. 58-29104)
Reference), and the amount of phase compensation is as follows:
The variable impedance means in the all-pass network may be adjusted by utilizing the fact that there is a correlation between the amount of attenuation and the phase shift when adjusting the frequency characteristics of the Y signal.

As described above, in the video signal processing circuit according to the present invention, the correction of the time axis fluctuation of the composite video signal and the Y / C separation are performed digitally, and the Y signal and the C signal are each converted into an analog signal. Independently derived as a circuit output, the image quality is adjusted by adjusting the high-frequency characteristics of the analog Y signal, and the phase of the analog C signal is changed by the phase change of the Y signal accompanying the adjustment of the frequency characteristics. Since the compensation is performed, it is possible to derive the Y signal whose frequency characteristic has been adjusted for image quality adjustment without causing a phase shift between the Y signal and the C signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a circuit configuration of a digital Y / C separation circuit in FIG. 1, and FIG. 3 is a digital noise elimination circuit in FIG. FIG. 3 is a block diagram illustrating an example of a circuit configuration of a circuit. Description of Signs of Main Part 2 FM demodulation circuit 5 PLL circuit 7 Line memory 10 Image memory 14 Digital Y / C separation circuit 22 Analog noise removal circuit 23 Digital noise Elimination circuit 30,33 …… Frequency characteristic adjustment circuit 35 …… Character insertion circuit 37 …… Color removal circuit

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masaaki Tanaka 4-2610 Hanazono, Tokorozawa-shi, Saitama Prefecture Pioneer Corporation Tokorozawa Plant (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 9/79 -9/898

Claims (2)

(57) [Claims] 1. A time axis correction circuit for digitally correcting a time axis fluctuation of a composite video signal obtained by reading and demodulating a composite video signal from a recording medium, and a luminance signal for the digital composite video signal passed through the time axis correction circuit. And a Y / C separation circuit for separating the luminance signal and the chrominance signal into a color signal.The video signal processing is performed such that the luminance signal and the chrominance signal separated by the Y / C separation circuit are each converted into an analog signal and independently derived as a circuit output. A frequency characteristic adjustment circuit that adjusts a high-frequency characteristic of the analogized luminance signal, and compensates a phase of the analogized color signal by an amount corresponding to a phase change of the luminance signal by the frequency characteristic adjustment circuit. A video signal processing circuit comprising: a phase compensation circuit. 2. The video signal processing circuit according to claim 1, wherein said phase compensation circuit comprises a frequency characteristic adjustment circuit having the same characteristics as said frequency characteristic adjustment circuit.