JPH07115620A - Time base corrector - Google Patents

Abstract

PURPOSE:To eliminate the necessity of some kind of countermeasure when the timing of correction is deviated by the non-execution of D/A conversion just after reading from a memory at the time base corrector (TBC) for correcting a time base by changing the phase of a clock not only on a memory write side but also on a read side. CONSTITUTION:Based on a residul phase error not to be completely corrected by a write side PLL circuit 702 of a first-in first-out (FiFo) memory 705, the velocity component of that error is calculated by an interpolation circuit 707. When the phase is corrected by an IIR (infinite impulse response) type APF (all-pass filter) 101 just after the FiFo memory 705, a FiFo memory read clock can be fixed. On the other hand, the circuit scale of the APF 101 can be considerably reduced in comparison with that of an FIR (finite impulse response) type interpolation filter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device for correcting the time axis of a video signal in an optical disk player, a video tape recorder or the like.

[0002]

2. Description of the Related Art A conventional time axis correction device (hereinafter,
(Also referred to as TBC).

FIG. 7 shows a block diagram of a conventional TBC. The TBC is a device that corrects jitter (for example, fluctuation of the time axis of the reproduced video signal caused by uneven rotation of the optical disk in the optical disk player) in the reproduction processing of the video signal. Jitter is detected from a horizontal synchronizing signal or a color burst signal (hereinafter referred to as a burst) in the input video signal, and is obtained as an error on the time axis with respect to a standard television signal such as the NTSC system or the PAL system. The input video signal is a baseband composite signal (for example,
In case of NTSC system, color difference signal is about 3.58 as luminance signal.
A color television signal in which carrier color signals quadrature-phase modulated at MHz are multiplexed. First, AD the input video signal
A C (analog / digital converter) 701 converts the digital signal. The PLL circuit 702 generates a write clock that is phase-synchronized with the input video signal. The reference clock generation circuit 703 oscillates a rectangular wave of about 14.3 MHz, which is four times the frequency of the color sub-carrier frequency f _sc , as a reference clock by a crystal oscillator, for example. The delay circuit 704 delays by one horizontal synchronization period (hereinafter referred to as one line). The output of the delay circuit 704 is FiFo (read ahead first)
The data is input to the memory 705 and written with the write clock output from the PLL circuit 702. Since using the read clock that reads the signal from the FiFo memory 705 as the reference clock is not sufficient as the jitter suppression characteristic of the TBC, the read clock is phase-modulated by the jitter (residual jitter) that cannot be completely absorbed by the write side alone. And a desired jitter suppression characteristic is obtained. Although this correction method is generally known, it is called feed-forward type velocity error (speed error) correction capable of high-speed response. The phase error can be detected only discretely for each line from the horizontal synchronizing signal or the burst, but the phase error changes every moment. Therefore, for example, if the phase error for each line is simply linearly interpolated, it can be approximated to the actual phase error. The phase error after this interpolation process is a velocity error, and the velocity axis correction is based on this velocity error correction. An interpolation circuit 707 interpolates a signal for each line based on the residual jitter output from the PLL circuit 702 to obtain a velocity error. At least one line time is required for the interpolation, and a one-line delay circuit must be inserted in the video signal in order to match the timing of the velocity error with the timing of the video signal. The circuit for delaying the one line is the delay circuit 704. Based on the velocity error output from the interpolation circuit 707, the clock phase modulation circuit 708 phase-modulates the reference clock so as to cancel the velocity error, and the FiFo memory 705
Read clock. An output of the FiFo memory 705 is converted by a DAC (digital / analog converter) 706 into an analog signal by a read clock.

[0004]

However, the above conventional structure has the following two problems. 1
The second issue is as follows. In order to obtain a desired jitter suppression characteristic, not only the write clock of the FiFo memory but also the read clock are phase-modulated.
Unless it is converted to an analog signal by the DAC immediately after reading the Fo memory, the timing of the time axis correction is deviated and the ideal jitter suppression characteristic is not obtained. In particular, after reading the FiFo memory, if a large-scale digital signal processing circuit such as a Y / C separation circuit for separating a luminance signal and a carrier color signal or a noise removing device for removing a noise component is connected, at least the time axis correction timing It is necessary to take some measures to adjust the values, and ideal time axis correction may not be possible. Thus, if the read clock of the FiFo memory is also phase-modulated, it is difficult to perform ideal time-axis correction in some cases.

The second problem is as follows.
In order to solve the first problem, for example, an FIR (finite impulse response) type interpolation filter is connected after reading the FiFo memory, the read clock is fixed, and the input video signal phase is changed by the interpolation filter to change the time axis error. However, since the interpolation filter includes a large number of multipliers, the circuit scale is very large.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a time axis correction device which makes it possible to perform ideal time axis correction with a fixed FiFo memory read clock and a sufficiently small circuit scale. To do.

[0007]

In order to achieve this object, the time axis correction apparatus of the present invention for the first object is to use an input video signal as a PLL (Phase Locked Lo).
Op) circuit to convert into a digital signal according to the write clock output from the analog-digital converter (AD)
C), a delay circuit that delays the output of the ADC for one horizontal synchronization period by the write clock output from the PLL circuit, and AD
A PLL circuit that outputs a write clock that is phase-synchronized with the input video signal by the output of C and the reference clock that the reference clock generation circuit outputs, a reference clock generation circuit that generates a reference clock of a predetermined frequency, and a PLL circuit output. The output of the delay circuit and the interpolation circuit that interpolates the phase error signal for each one horizontal synchronization period into a continuous phase error signal is P
A FiFo (first in, first out) memory having a predetermined storage capacity that is read by a reference clock output by a write reference clock generation circuit by a write clock output by an LL circuit,
An all-pass filter (AP) that shifts the output of the FiFo memory by a predetermined phase based on the phase error signal output from the interpolation circuit by the reference clock output from the reference clock generation circuit.
F) and a DAC (digital-analog converter) that converts the output of the APF into an analog signal with the reference clock output from the reference clock generation circuit.

In order to achieve this object, the all-pass filter (APF) of the present invention for the second problem is to provide a first decoder for decoding the phase error signal output from the interpolation circuit and the phase error signal for the phase error signal. A second decoder for decoding, a first subtractor for subtracting the input video signal and the output of the first D-type flip-flop (DFF), the output of the first subtractor and the output of the first coefficient switching circuit. A second subtractor for subtracting, the second DFF for latching the output of the second subtractor with the input clock, and the output of the second DFF multiplied by a predetermined coefficient to switch the output of the first decoder. A first coefficient switching circuit, a second coefficient switching circuit that multiplies the output of the second DFF by a predetermined coefficient and switches with the output of the second decoder, and the output of the first coefficient switching circuit is latched with an input clock. Third DF to do A first adder for adding the output of the second coefficient switching circuit and the output of the third DFF; a first DFF for latching the output of the second coefficient switching circuit with an input clock; A fourth DFF that latches the output of the DFF with the input clock, a fifth DFF that latches the output of the fourth DFF with the input clock, and the output of the first adder and the output of the fifth DFF And a second adder.

[0009]

The present invention has the following actions for the first problem due to the above configuration. Since the APF can change the phase of the input signal by adaptively changing its transfer function, the phase of the input signal can be corrected by changing the transfer function by the phase error signal. That is, A
An ideal time axis correction can be performed by connecting the PF after reading the FiFo memory, fixing the read clock and changing the input video signal phase by the APF to correct the time axis error. That is, the FiFo memory read clock can be fixed, and the time axis correction is completed by the APF, so that no problem arises no matter what digital signal processing circuit is connected thereafter.

The present invention having the above-mentioned configuration has the following actions for the second problem. APF is II
FIR with R (infinite impulse response) type filter
The circuit scale is sufficiently smaller than that of the interpolation filter. However, since it is the IIR type, there always exists a path in which the multiplication for adaptively changing the transfer function must be completed within one clock period. Therefore, the maximum operating clock frequency of the APF becomes low, but since the multiplication is embodied by the coefficient switching circuit instead of the multiplier, the maximum operating clock frequency can be raised to a frequency at which the video signal can be processed. In this way, the circuit scale of APF is sufficiently small,
Hardware for processing video signals can be realized.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the time axis correction device according to the present invention will be described below with reference to the drawings. However,
The same components as those of the conventional time axis correction device shown in FIG. 7 are designated by the same reference numerals, and the description of the operation thereof is omitted.

FIG. 1 is a block diagram showing the arrangement of a time axis correction apparatus according to the first embodiment of the present invention. An APF (all-pass filter) 101 is connected to the output of the FiFo memory 705, and the residual phase error signal which is the velocity error output from the interpolation circuit 707 is input. The velocity error adaptively changes the transfer function of the APF 101 to change the phase of the input video signal. For example, if the velocity error is 10 ° (one cycle of the carrier color signal is 360 °), the APF 101 shifts the phase by -10 °. APF1
01 is a special filter whose amplitude characteristic is constant with respect to all angular frequencies and whose phase characteristic changes depending on the pole and zero. AP
The transfer function H ₁ (z) of F is, for example, in the case of quadratic (Equation 1)
Given in.

[0013]

[Equation 1]

The phase characteristics are changed by adaptively changing the coefficients k _a , k _b , and k _{c according} to the velocity error, and the input video signal of a predetermined frequency is phase-shifted.

FIG. 2 is a block diagram showing the structure of the APF in the time base correction apparatus according to the first embodiment of the present invention.

In order to embody the transfer function H ₁ (z) of (Equation 1) described above, first, a ROM (read-only memory) for converting velocity errors into coefficients k _a , k _b , k _c , A total of 6 multipliers are required to multiply the signals by the coefficients k _a , k _b , k _c . However, in that case, the circuit scale becomes very large, and as is apparent from the function of the denominator which is the feedback part of H ₁ (z), at least two multiplications must be executed within one clock period. Here, considering that the input video signal is, for example, a standard television signal of the NTSC system, the signal band is about 5 MHz, and when trying to process a digital signal, the clock frequency is about 15 MHz according to the sampling theorem, and the digital video signal is 8 bits. is necessary. In other words, one clock cycle is about 67 nsec, and it is virtually impossible to execute two multiplications of 8 bits within this time. Here, the transfer function H ₁ of (Equation 1)
(Z) is transformed into H ₂ (z) in (Equation 2). However, even though this still requires one multiplication to be performed within one clock cycle, it is difficult to consider that addition is also performed.

[0017]

[Equation 2]

Therefore, in the present invention, as shown in FIG. 2, high-speed calculation is possible by switching the coefficient units by the coefficient switching circuits 205 and 206, instead of executing the multiplication by the multiplier. Further, the coefficients are not generated in the ROM, but are decoded by the decoders 212 and 213 into switching signals for switching the coefficient units in the coefficient switching circuits 205 and 206. The block diagram of FIG. 2 embodies the above-mentioned transfer function H ₂ (z), in which the signal and coefficient k
_The coefficient switching circuit 205 _performs multiplication with _bc by the signal and coefficient k.
_The coefficient switching circuit 206 embodies multiplication with _ac . Further, the velocity error is decoded by the decoder 212 into the switching signal of the coefficient switching circuit 205, and is decoded by the decoder 213 into the switching signal of the coefficient switching circuit 206. The important part is the coefficient switching circuit 205.
And 206 and the decoders 212 and 213, the subtracters 201 and 202 and the adder 20 are implemented.
3 and 204, D-type flip-flop (DFF) 207
Operations such as where to arrange 211 to 211 on the block diagram, what to do with the sign of the subtractor, or change the delay time by changing the number of DFFs are not related to the present invention. In other words, since there are many possible APF circuit configurations due to the transformation of the transfer function, they will not be mentioned here. Also,
Although the embodiment has been described here as a second-order IIR type APF, the present invention can be applied to higher-order APFs.

FIG. 3 is a block diagram showing the configuration of the coefficient switching circuit in the APF in the time base correction apparatus according to the first embodiment of the present invention. That is, the internal configuration of the coefficient switching circuits 205 and 206 in the block diagram of FIG. 2 is shown.
Bit shift the input signal (sequentially move bits to the upper bit direction and insert 0 in the vacant lower bits, or move the bits sequentially to the lower bit direction and discard the protruding bits. When the signal is an 8-bit binary signal, if the least significant bit is set to 0, and carry is carried out sequentially to make a 9-bit signal, the input signal is doubled. If the least significant bit is discarded, the input signal is set to 7 bits. It is input to M coefficient units 301 (M is a natural number) that is multiplied by 2 ^N (N is an integer). The switching circuit 302 switches the output from the M outputs of the M coefficient units to L outputs (L is a natural number of L <M) in response to an input switching signal. Then, the switching circuit 30
The two L outputs are added or subtracted by the adder / subtractor 303. For example, if the input signal is 8 bits, the minimum N is-
M is 14th because it is considered to be 7 at the maximum. Of course, not all cases are required to embody the coefficients, so there are coefficients that can be omitted, so M is smaller than 14. With this coefficient switching circuit, for example (11 /
4 + 1/32) to realize the coefficient
01 ² 2, 2 ^{- 1,} 2 ^-2, 2 ^-5 and selected by a circuit 302 switches the those coefficients multiplied respectively, may be added to the total signal in the adder-subtracter 303.

FIG. 4 is a block diagram showing the configuration of the coefficient switching circuit in the APF in the time base correction apparatus according to the first embodiment of the present invention. That is, this is an embodiment of the internal configuration of the coefficient switching circuits 205 and 206 different from that of FIG.

However, the same components as those of the time axis correction device according to the embodiment shown in FIG. 3 are designated by the same reference numerals, and the description of the operation thereof will be omitted.

For example, if the velocity error is VE,
And the coefficient k _ac in the APF is k _ac = _11/4 + 1
If it is represented by a linear equation of / 32 · VE, then 11 /
Since the coefficient part of 4 is fixed, it is embodied by the coefficient unit 401 and the adder / subtractor 402. 2 ² , 2 in the coefficient switching circuit
Multiply the coefficients by ^-1 , 2 ^-2 and add them all by the adder / subtractor 402. When VE = 1, the coefficient unit 301 multiplies the coefficient by 2 ⁻⁵ , the switching circuit 302 selects this coefficient, and the adder / subtractor 303 does not need to perform addition, and the adder / subtractor 403 outputs the output of the adder / subtractor 402 and the coefficient unit 301. Just add the outputs. When VE = 2, the coefficient unit 301 multiplies a coefficient of 2 ⁻⁴ and the same calculation as when VE = 1 is performed. As described above, the embodiment of FIG. 4 is very effective when the coefficient is represented by the addition or subtraction of the fixed coefficient and the variable coefficient.

FIG. 5 is a block diagram showing the structure of the APF in the time base correction apparatus according to the first embodiment of the present invention.

However, the same components as those of the time axis correction apparatus according to the embodiment shown in FIG. 2 are designated by the same reference numerals, and the description of the operation thereof will be omitted.

This is an embodiment in the case where there is a part where the calculation can be shared when the coefficients k _ac and k _bc are embodied. The coefficient switching circuit 501 uses the coefficient switching circuits 205 and 2 of FIG.
The operation of 06 is performed by the decoder 502 in the decoder 212 of FIG.
By embodying the operations of 1 and 213, the circuit scale can be further reduced as compared with the embodiment of FIG.

FIG. 6 is a block diagram showing the configuration of the coefficient switching circuit in the APF in the time base correction apparatus according to the first embodiment of the present invention. That is, the internal configuration of the coefficient switching circuit 501 in the block diagram of FIG. 5 is shown.

However, the same components as those of the time axis correction device according to the embodiment shown in FIGS. 3 and 4 are designated by the same reference numerals, and the description of the operation thereof is omitted.

The relationship between the coefficients k _ac and k _bc is, for example, k _ac = k
_When represented by _bc / 2, the output of the adder / subtractor 303 is input to the subtractor 202, multiplied by 2 ⁻¹ by the coefficient unit 601, and added by the adder 20.
Enter in 3. As described above, there are many methods for embodying the coefficients k _ac and k _bc , and although not described in detail here, they are embodied by a combination of a coefficient unit, a switching circuit, and an adder / subtractor.

In all the embodiments, the operation has been described with the input signal as the video signal, but it goes without saying that the present invention can be applied to the case of an audio signal. Further, the internal configuration of the APF can be applied not only as a part of the time axis correction device but also to a device requiring phase correction, for example, an APC (automatic phase control) circuit, and the industrial value is very large.

[0030]

As described above, according to the present invention, the FiFo (first in, first out) memory is read by the reference clock output from the reference clock generating circuit, and the all-pass filter (APF) is F.
The output of the iFo memory is phase-shifted by a predetermined phase based on the phase error signal output from the interpolation circuit by the reference clock output from the reference clock generation circuit.
o The memory read clock can be fixed, and the circuit scale of the APF is sufficiently small, and hardware for processing a video signal can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a time axis correction device according to a first embodiment of the present invention.

FIG. 2 shows a first all-pass filter (APF) in FIG.
Block diagram showing the configuration of

FIG. 3 is a block diagram showing a first configuration of first and second coefficient switching circuits in FIG.

FIG. 4 is a block diagram showing a second configuration of the first and second coefficient switching circuits in FIG.

FIG. 5 is a second all-pass filter (APF) in FIG.
Block diagram showing the configuration of

6 is a block diagram showing a first configuration of a coefficient switching circuit in FIG.

FIG. 7 is a block diagram showing the configuration of a conventional time axis correction device.

[Explanation of symbols]

 101 APF 205,206,501 Coefficient switching circuit 212,213,502 Decoder 301,401,601 Coefficient device 302 Switching circuit 303,402,403 Adder / subtractor

Claims (6)

[Claims] 1. An input video signal is transferred to a PLL (Phase L).
an analog-digital converter that converts a digital signal by a write clock output from an locked loop circuit; and a delay circuit that delays the output of the analog-digital converter by the write clock output from the PLL circuit for one horizontal synchronization period, A PLL circuit that outputs a write clock that is phase-synchronized with the input video signal based on the output of the analog-digital converter and the reference clock output by the reference clock generation circuit; and a reference clock generation circuit that generates a reference clock of a predetermined frequency. An interpolation circuit that interpolates a phase error signal for each horizontal synchronization period output from the PLL circuit into a continuous phase error signal, and writes the output of the delay circuit with a write clock output from the PLL circuit. Read with reference clock output from generator Fi, and having a predetermined storage capacity
An Fo (first in, first out) memory, and an all-pass filter for shifting the output of the FiFo memory by a predetermined phase based on a phase error signal output from the interpolation circuit by a reference clock output from the reference clock generation circuit. And a digital-analog converter that converts the output of the all-pass filter into an analog signal with a reference clock output from the reference clock generation circuit. 2. The all-pass filter comprises: a first decoder for decoding the phase error signal output from the interpolation circuit; a second decoder for decoding the phase error signal; an input video signal and a first D signal. First subtractor for subtracting the output of the flip-flop, a second subtractor for subtracting the output of the first subtractor and the output of the first coefficient switching circuit, and the output of the second subtractor A second D-type flip-flop for latching with an input clock, a first coefficient switching circuit for multiplying the output of the second D-type flip-flop by a predetermined coefficient and switching the output with the output of the first decoder, A second coefficient switching circuit that multiplies the output of the second D-type flip-flop by a predetermined coefficient and switches the output of the second decoder; and a second coefficient switching circuit that latches the output of the first coefficient switching circuit with an input clock. D flip-flop, a first adder that adds the output of the second coefficient switching circuit and the output of the third D flip-flop, and the output of the second coefficient switching circuit is latched with an input clock. The first D-type flip-flop, the fourth D-type flip-flop that latches the output of the second D-type flip-flop with the input clock, and the output of the fourth D-type flip-flop with the input clock. The time axis according to claim 1, further comprising: a fifth D-type flip-flop for latching, and a second adder for adding an output of the first adder and an output of the fifth D-type flip-flop. Correction device. 3. An all-pass filter, a decoder for decoding a phase error signal output from an interpolation circuit, a first subtractor for subtracting an input video signal and an output of a first D-type flip-flop, A second subtractor for subtracting the output of the first subtractor and the output of the coefficient switching circuit; a second D-type flip-flop for latching the output of the second subtractor with an input clock; and the second The output of the D flip-flop is multiplied by a predetermined coefficient and switched by the output of the decoder to output two signals, and a third D for latching the first output of the coefficient switching circuit with an input clock. -Type flip-flop, a first adder for adding the second output of the coefficient switching circuit and the output of the third D-type flip-flop, and a second output of the coefficient switching circuit for the input clock A first D-type flip-flop for latching, a fourth D-type flip-flop for latching the output of the second D-type flip-flop with an input clock, and an output of the fourth D-type flip-flop for the input clock 2. The time according to claim 1, further comprising: a fifth D-type flip-flop latched by the second adder, and a second adder that adds the output of the first adder and the output of the fifth D-type flip-flop. Axis correction device. 4. The first (or second) coefficient switching circuit includes M (M is a natural number) coefficient units for multiplying an input signal by 2 ^N times (N is an integer) by bit shifting, and the M coefficients. A switching circuit for switching L outputs (L is a natural number of L <M) from the M outputs of the switching device and an adder / subtractor for adding or subtracting the L outputs of the switching circuit, The input signal is the output of the second D-type flip-flop, the input switching signal is the output of the first (or second) decoder, and the output of the adder / subtractor is the first (or second) coefficient switching circuit. The time axis correction device according to claim 2. 5. The first (or second) coefficient switching circuit includes Q (Q is a natural number) first coefficient multipliers that multiply an input signal by 2 ^P (P is an integer) by bit shifting, and A first adder / subtractor for adding or subtracting Q outputs of a coefficient unit of 1 and 2 ^N times (N is an integer) the input signal by bit shifting
M (M is a natural number) second coefficient multipliers and M outputs of the M second coefficient multipliers are switched between L outputs (L is a natural number satisfying L <M) by an input switching signal. A switching circuit, a second adder / subtractor for adding or subtracting the L outputs of the switching circuit, and a third adder / subtractor for adding or subtracting the output of the first adder / subtractor and the output of the second adder / subtractor And the input signal is the output of the second D-type flip-flop, the input switching signal is the output of the first (or second) decoder, and the output of the third adder / subtractor is the first (or Or (2) The time axis correction device according to claim 2, which is an output of the coefficient switching circuit. 6. The coefficient switching circuit comprises M (M is a natural number) first coefficient multipliers for multiplying an input signal by 2 ^N times (N is an integer) by bit shifting, and the M first coefficient multipliers. A switching circuit that switches L outputs (L is a natural number of L <M) from M outputs by an input switching signal, an adder / subtractor that adds or subtracts the L outputs of the switching circuit, and an output of the adder / subtractor Is a second coefficient multiplier for multiplying by a predetermined coefficient, the input signal is the output of the second D-type flip-flop, the input switching signal is the output of the decoder, and the output of the adder / subtractor is the output of the coefficient switching circuit. A first output or a second output, and when the output of the adder / subtractor is the first output of the coefficient switching circuit, the output of the second coefficient device is the second output of the coefficient switching circuit, Addition and subtraction Time base corrector when the output of the second output of the coefficient switching circuit according to claim 3 wherein the output of the second coefficient unit and the first output of the coefficient switching circuit.