JP2000040963A - Digital signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the digital signal processing circuit which can obtain optimum frequency characteristics without adjusting the phase of a sampling clock. SOLUTION: An amplifier 6 multiplies an output signal (c) of an A/D converter 2 by -1/2. One-clock delay units 7 and 8 delay the clock (c) by one clock each. An amplifier 9 multiplies the output of the one-clock delay unit 8 by -1/2. An adder 10 adds the output signal (d) of the amplifier 6, the output signal (e) of the one-clock delay unit 7, and the output signal (f) of the amplifier 9 together. An amplifier 11 multiplies the output signal (g) of the adder 10 by α (0<α). A limiter circuit 12 limits the amplitude of the output of the amplifier 11. An adder 13 adds the signal (e) and an output signal (h) of the limiter circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital signal processing circuit provided with an A / D converter for converting an analog signal into a digital signal, and more particularly to a digital signal processing circuit capable of obtaining an optimum frequency characteristic. .

[0002]

2. Description of the Related Art Normally, when an analog signal is sampled by an A / D converter and converted into a digital signal, sampling is performed at a clock frequency twice or more the frequency band of the input analog signal. However, when sampling is performed at twice the clock frequency, in the highest frequency component of the input analog signal, the sampling position of the signal changes depending on the clock phase, and the signal may be deteriorated. Therefore, it is common to provide a phase adjustment circuit for adjusting the phase of the sampling clock supplied to the A / D converter, and to prevent the signal from deteriorating by adjusting the phase of the sampling clock.

FIG. 4 is a block diagram showing an example of a conventional digital signal processing circuit. In FIG. 4, an analog signal input to an input terminal 1 is sampled by an A / D converter 2 and converted into a digital signal.
Output. The phase of the sampling clock generated by the clock generation circuit 4 is optimally adjusted by the phase adjustment circuit 5 and is input to the A / D converter 2.

In FIG. 5, (A) shows an analog signal input to the input terminal 1, (B) shows a clock whose phase has been optimally adjusted by the phase adjusting circuit 5, and (C) shows a clock before the phase adjustment. . The signal shown in FIG.
When sampling with the clock shown in the following, the sampling point is b
Will be. This is not the optimal sampling phase. Then, FIG. 5 (C) shows that the sample point is a.
The phase adjustment circuit 5 adjusts the phase of the clock shown in
A clock as shown in FIG.

[0005] Thus, even at the highest frequency component of the input analog signal, the signal is not degraded, and an optimum frequency characteristic can be obtained.

[0006]

However, since the phase adjustment circuit 5 must have a clock adjustment range of several nS to several tens nS, the conventional digital signal processing circuit shown in FIG. Is difficult, even if L
Even if it is made into SI, there is a problem that variation is large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a digital signal processing circuit capable of obtaining an optimum frequency characteristic without adjusting the phase of a sampling clock. .

[0008]

In order to solve the above-mentioned problems of the prior art, the present invention comprises an A / D converter (2) for sampling an analog signal by a sampling clock and converting it into a digital signal. In a digital signal processing circuit, a first amplifier (6) for multiplying the output of the A / D converter by -1/2 and an output of the A / D converter by 1
A first one-clock delay unit (7) for delaying a clock, a second one-clock delay unit (8) for delaying the output of the first one-clock delay unit by one clock, and the second one-clock delay unit Amplifier (9) for multiplying the output of -1/2 times
And a first adder (1) for adding the outputs of the first amplifier, the first one-clock delay unit, and the second amplifier.
0); a third amplifier (11) for multiplying the output of the first adder by α (0 <α); a limiter circuit (12) for limiting the amplitude of the output of the third amplifier; A digital signal processing circuit comprising: a second adder (13) for adding the output of one one-clock delay unit and the output of the limiter circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital signal processing circuit according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of the digital signal processing circuit of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the digital signal processing circuit of the present invention, and FIG. FIG. 4 is a characteristic diagram for explaining. In FIG. 1, the same parts as those in FIG. 4 are denoted by the same reference numerals.

In FIG. 1, an analog signal input to an input terminal 1 is sampled by an A / D converter 2 and converted into a digital signal. The sampling clock shown in FIG. 2A generated by the clock generation circuit 4 is input to the A / D converter 2. An example of the output signal c of the A / D converter 2 is shown in FIG.

The output signal c of the A / D converter 2 is -1/2.
It is input to a double amplifier 6 and a one-clock delay circuit 7.
The amplifier 6 multiplies the output signal c of the A / D converter 2 by -1/2 to obtain a signal d shown in FIG. The one-clock delay circuit 7 delays the signal c by one clock, and converts the signal e shown in FIG.
The signals are input to the adders 10 and 13.

The one-clock delay circuit 8 delays the output signal e of the one-clock delay circuit 7 by one clock and inputs the output signal e to the -９ amplifier 9. The amplifier 9 multiplies the output of the one-clock delay circuit 8 by -1/2 to obtain a signal f shown in FIG. The one-clock delay circuits 7 and 8 include:
The sampling clock shown in FIG. 2A generated by the clock generation circuit 4 is input.

The adder 10 receives the input signals d, e, f
, And the signal g shown in FIG. The amplifier 11 amplifies the signal g by α (0 <α) times,
It is input to the limiter circuit 12. The limiter circuit 12 limits the output of the amplifier 11 so that the amplitude of the output signal i of the adder 13 does not exceed a predetermined value, and inputs the signal h shown in FIG. The adder 13 adds the signal e output from the one-clock delay circuit 7 and the signal h output from the limiter circuit 12, and outputs a signal i shown in FIG.

As can be seen from FIG.
The output signal i has a larger amplitude than the signal c shown in FIG.

The filter circuit composed of the one-clock delay circuits 7 and 8, the amplifiers 6 and 9 and the adder 10 is shown in FIG.
The characteristics are as shown in FIG. In FIG. 3, the horizontal axis is frequency and the vertical axis is amplitude. The frequency on the horizontal axis is normalized by frequency / sampling frequency. For example, 0.5 means that the frequency is 1/2 of the sampling frequency. The amplitude on the vertical axis is normalized to have a maximum value of 1.0.

In the digital signal processing circuit of the present invention, since the frequency characteristic of the filter circuit is as shown in FIG. 3, the low frequency component of the input analog signal is not changed as shown in FIG. As shown in the figure, the amplification of the amplitude does not work very much, and for the high frequency component of the input analog signal,
The amplification of the amplitude as shown in FIG.

Therefore, according to the digital signal processing circuit of the present invention, the amplitude can be increased with respect to the highest frequency component of the input analog signal. As a result, the signal is not deteriorated and the optimum frequency characteristic is obtained. be able to. As described above, without adjusting the phase of the sampling clock, it is possible to obtain a frequency characteristic equivalent to that obtained by optimally adjusting the phase of the sampling clock as shown in FIG.

[0018]

As described in detail above, the digital signal processing circuit of the present invention outputs the output of the A / D converter to -1/2.
A first amplifier for multiplying the output, a first one-clock delay for delaying the output of the A / D converter by one clock, and a second one-clock delay for delaying the output of the first one-clock delay by one clock A second amplifier for multiplying the output of the second one-clock delay unit by -1/2, and a first addition for adding the outputs of the first amplifier, the first one-clock delay unit, and the second amplifier Amplifier, a third amplifier for multiplying the output of the first adder by α (0 <α), a limiter circuit for limiting the amplitude of the output of the third amplifier, an output and a limiter of the first one-clock delay unit And a second adder for adding the output of the circuit, so that the phase of the sampling clock is not adjusted,
An optimum frequency characteristic can be obtained. Therefore, the digital signal processing circuit of the present invention can be easily formed into an LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the present invention.

FIG. 3 is a characteristic diagram for explaining the present invention.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a waveform chart for explaining the operation of the conventional example.

[Explanation of symbols]

 2 A / D converter 4 Clock generation circuit 6, 9, 11 Amplifier 7, 8 1 Clock delay circuit 10, 13 Adder 12 Limiter circuit

Claims (1)

[Claims] 1. A digital signal processing circuit comprising an A / D converter for sampling an analog signal by a sampling clock and converting the analog signal into a digital signal, wherein a first signal for multiplying an output of the A / D converter by -1/2. And a first 1 that delays the output of the A / D converter by one clock.
A clock delay unit, a second one-clock delay unit that delays the output of the first one-clock delay unit by one clock, and a second amplifier that subtracts -1/2 times the output of the second one-clock delay unit A first adder for adding the outputs of the first amplifier, the first one-clock delay unit, and the second amplifier; and multiplying the output of the first adder by α (0 <α) A third amplifier that limits the amplitude of the output of the third amplifier; and a second adder that adds the output of the first one-clock delay unit and the output of the limiter circuit. A digital signal processing circuit characterized by comprising: