JPH0879634A - Correlation duplex sampling device - Google Patents

Abstract

PURPOSE: To optimize the phase of a sample pulse supplied to a correlation duplex sampling circuit (CDS circuit) through the use of a memory and a microcomputer and to obtain the image pickup signal of a high S/N. CONSTITUTION: CCD 1 outputs a signal obtained by photoelectrically converting light into an electric signal and a CDS circuit 2 processes the output signal of a CCD 1. An ADC circuit 3 AD-converts the output signal of the CDS circuit 2, and the memory 4 stores the output signal of the ADC circuit and outputs stored data to the microcomputer. The microcomputer 5 supplies a phase control signal for controlling the phase of the sample pulse supplied to the CDS circuit 2 to a sample pulse generation circuit 7 based on the output signal of the memory. A sample pulse generation circuit 6 outputs the sample pulse supplied to the CDS circuit 2 based on the phase control signal supplied from the microcomputer 5. A clamping pulse generation circuit 7 generates a clamping pulse clamping the DC level of field through except for the reset pulse of the output signal from CCD 1, which is supplied to the CDS circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correlated double sampling device necessary for improving S / N of an image pickup signal of a CCD which is a photoelectric conversion element in an image pickup device or the like.

[0002]

2. Description of the Related Art In recent years, a correlated double sampling device has become more and more important in an image pickup device or the like in order to remove a reset noise contained in a CCD image pickup signal to obtain a high S / N image pickup signal.

A conventional correlated double sampling device will be described below. FIG. 4 is a block diagram showing the configuration of a conventional correlated double sampling device. FIG.
In, 9 is a CCD, 10 is a CDS circuit, 11 is a clamp pulse generation circuit, 12 is a sample pulse generation circuit,
Reference numeral 13 is an output terminal.

The operation of the correlated double sampling device configured as described above will be described below with reference to FIG.

FIG. 5 is a signal waveform diagram showing an operating state of the conventional correlated double sampling device shown in FIG.

First, when light having no level fluctuation with time as shown in FIG. 5A enters the CCD 9 from a lens or the like, the CCD 9 which is a photoelectric conversion element outputs a signal as shown in FIG. 5B. In addition to C, the output signal containing a constant DC level and a field through component mixed with a reset pulse is C
Output to DS10.

Next, the CDS 10 is supplied with a clamp pulse for clamping a constant DC level other than the reset pulse shown in FIG. 5B from the clamp pulse generation circuit 11 as shown in FIG. A sample pulse for sampling and holding the signal portion of FIG. 5B as shown in FIG. 5D is supplied from the sample pulse generation circuit 12. At this time, the output terminal 13 directly connected to the CDS 10 is shown in FIG.
(E), the signal waveform of FIG. 5 (b) is clamped at the DC level except the reset pulse except for the reset pulse, and the signal portion is sampled and held and output.

[0008]

However, in the above-mentioned conventional configuration, when the phase of the output signal of the CCD output to the CDS circuit changes due to temperature change or the like, the CD
Since the phase of the sample pulse supplied to the S circuit is fixed, the signal portion of the CCD output signal cannot always be optimally sampled and held.

The present invention solves the above-mentioned conventional problems. Correlation 2 that can obtain a high S / N image pickup signal by optimizing the phase of the sample pulse supplied to the CDS circuit using a memory and a microcomputer. An object is to provide a heavy sampling device.

[0010]

To achieve this object, a correlated double sampling device of the present invention is a photoelectric conversion device CCD, and a correlated double sampling circuit CDS for processing an output signal of the CCD. Circuit, an ADC circuit that AD-converts and outputs the output signal of the CDS circuit, a memory that stores the output signal of the ADC circuit and outputs the stored data to the microcomputer, and supplies the CDS circuit based on the output signal of the memory A microcomputer that outputs a phase control signal for controlling the phase of the sample pulse, a sample pulse generation circuit that outputs a sample pulse that is supplied to the CDS circuit based on the phase control signal that is output from the microcomputer, and a clamp that supplies the CDS circuit. It consists of a clamp pulse generation circuit that outputs a pulse and an output terminal that is directly connected to the CDS circuit that extracts the imaging signal. That.

[0011]

According to the present invention having the above-described structure, the CCD outputs the photoelectrically converted output signal to the CDS circuit, and the clamp pulse generating circuit causes the CDS circuit to output the DC level of the field through except the reset pulse of the CCD output signal. The clamp pulse for clamping is supplied, and the sample pulse generation circuit supplies the CDS circuit with a sample pulse for sample-holding the phase of the beginning of the signal period of the output signal of the CCD. The CDS circuit outputs the processed CCD output signal to the ADC circuit, the ADC circuit performs AD conversion, and the memory stores the output signal of the ADC circuit at address 1. Next, the microcomputer applies CC to the sample pulse generation circuit.
A phase control signal that advances the phase of the sample pulse by an arbitrary phase angle θ from the starting phase of the output signal of D is output,
The sample pulse generation circuit supplies the CDS circuit with a sample pulse advanced by an arbitrary phase angle θ from the starting phase of the CCD output signal. The CDS circuit is a processed CCD
Output signal to the ADC circuit, and the ADC circuit outputs AD
The memory converts the output signal of the ADC circuit to address 2
The data stored in address 1 and address 2 are output to the microcomputer. The microcomputer takes the difference between the data at address 1 and address 2, and if the difference is larger than the value set in the microcomputer, the phase control signal that advances the phase of the sample pulse to the sample pulse generation circuit by an arbitrary phase angle θ from the present time. Then, the sample pulse generating circuit supplies the sample pulse obtained by advancing the phase of the sample pulse by an arbitrary phase angle θ from the present time to the CDS circuit. Again, the CDS circuit outputs the processed output signal to the ADC circuit, and the ADC circuit performs AD conversion. The memory erases the data of the address 1 stored at the present time, writes the data of the address 2 to the address 1, and advances the phase of the sample pulse by an arbitrary phase angle θ from the present time. Address 2 for the output signal of the circuit
Stored as data. The microcomputer outputs the phase control signal to the sample pulse generation circuit until the difference between the data of address 1 and address 2 output from the memory converges to the value set in the microcomputer, and the sample pulse generation circuit outputs C
The phase of the sample pulse supplied to the DS circuit is advanced by an arbitrary phase angle θ, the CDS circuit outputs the processed CCD output signal to the ADC circuit, the ADC circuit performs AD conversion, and the memory addresses 1 The data of address 2 is updated and the data is output to the microcomputer. The microcomputer stops the phase control signal to the sample pulse generation circuit when the difference between address 1 and address 2 converges to the value set in the microcomputer, and the sample The pulse generation circuit continuously outputs the sample pulse to the CDS circuit that was generated when the phase control signal output from the microcomputer was stopped, and the image pickup signal C
Take out from the output terminal directly connected to the DS circuit.

[0012]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a correlated double sampling apparatus according to the first embodiment of the present invention.
In FIG. 1, 1 is a CCD that outputs a signal obtained by photoelectrically converting light into an electric signal using a lens, 2 is a CDS circuit that is a correlated double sampling circuit that processes the output signal of the CCD, and 3 is an output of the CDS circuit. An ADC circuit for AD converting the signal, 4 is a memory for storing the output signal of the ADC circuit and outputting the stored data to the microcomputer, and 5 is for controlling the phase of the sample pulse supplied to the CDS circuit based on the output signal of the memory. For supplying a phase control signal to the sample pulse generation circuit, 6 is a sample pulse generation circuit for outputting a sample pulse to be supplied to the CDS circuit based on the phase control signal supplied from the microcomputer, and 7 is a supply to the CDS circuit To generate a clamp pulse that clamps the DC level of the field through except the reset pulse of the CCD output signal. Npuparusu generation circuit, 8 denotes an output terminal directly connected to the CDS circuit for taking out an image pickup signal.

Correlation 2 of the present embodiment configured as described above
The operation of the heavy sampling device is shown in FIGS. 2 and 3 below.
Will be described with reference to. 2 and 3 are signal waveform diagrams showing the operation state of the present embodiment.

First, when light having no level fluctuation with time as shown in FIG. 2A enters the CCD 1 from a lens or the like, the CCD 1 outputs a constant signal in addition to the signal shown in FIG. 2B. The output signal including the field-through component mixed with the DC level and the reset pulse is output to the CDS2. The CDS2 is supplied with a clamp pulse for clamping the DC level of the field through except the reset pulse of the CCD output signal as shown in FIG. 2C from the clamp pulse generation circuit 7, and the sample pulse generation circuit of FIG. A sample pulse for sampling and holding the phase at the beginning of the signal period of the CCD output signal as shown in (d) is supplied. The output signal of CDS2 is output to ADC3,
A / D conversion is performed by DC3, and an output signal having an amplitude value A as shown in (g) of FIG. 3 is output to the memory 4 and stored as address 1 data of the memory 4. Next, from the microcomputer 5 to FIG.
2 (h) outputs a phase control signal, which is a DC signal having an amplitude value B, to the sample pulse generation circuit 6, and the sample pulse generation circuit 6 outputs the phase control signal shown in FIG. C in FIG. 2D as shown in FIG.
The sample pulse advanced by θ0 from the phase of the sample pulse supplied to DS2 is again supplied to CDS2, and CDS2
The ADC output signal is AD-converted by the ADC 3, and the output signal having the amplitude value C as shown in (i) of FIG. 3 is output to the memory 4 and stored as the data of address 2 of the memory 4. Then, the data of address 1 and address 2 of the memory 4 is output to the microcomputer 5, and the microcomputer 5 outputs an amplitude value D which is a difference signal between the data of address 1 and address 2 as shown in (j) of FIG.
Signal of the amplitude value D, which is the detected difference, is larger than the value set in the microcomputer, the phase control signal, which is the DC signal of the amplitude value E as shown in FIG. Output to the generation circuit 6, and the sample pulse generation circuit 6 is based on the phase control signal output from the microcomputer 5,
As shown in (f) of FIG. 2, a sample pulse advanced by θ1 from the phase of the sample pulse supplied to CDS2 of (e) of FIG. 2 is again supplied to CDS2, and the output signal of CDS2 is AD-converted by ADC3. , The memory 4 erases the data previously stored in the address 1 and stores the data of the address 2 as the data of the address 1, (l) in FIG.
The output signal of the amplitude value F output from the ADC 3 as shown in FIG. The data of address 1 and address 2 of the memory 4 is output to the microcomputer 5, and the microcomputer 5 detects the signal of the amplitude value G which is the difference signal of the data of address 1 and address 2 as shown in (m) of FIG. , The phase difference control signal to the sample pulse generating circuit was stopped because the detected signal of the amplitude value G converged to the value set in the microcomputer, and the sample pulse generating circuit stopped the phase control signal output from the microcomputer. The sample pulse to the CDS circuit generated at that time is continuously output, and the image pickup signal is taken out from the output terminal 8 directly connected to the CDS circuit.

As described above, according to this embodiment, the CDS2
, The output signal of the CCD 1 processed by the CDS 2 obtained before and after the phase change of the sample pulse is stored in the memory 4, and the difference value of the data stored in the memory 4 is stored in the microcomputer 5 Detected by the microcomputer 5, the phase of the sample pulse supplied to the CDS 2 is changed until the difference value of the data detected by the microcomputer 5 converges to the value set in the microcomputer 5, and the difference value of the data detected by the microcomputer 5 is set in the microcomputer. When the value converges to the value, the phase control to the sample pulse generation circuit is stopped, and the sample pulse generation circuit continues the sample pulse to the CDS circuit generated when the phase control signal output from the microcomputer is stopped. A high S / N image pickup signal can be obtained by supplying the image pickup signal from the output terminal 8 directly connected to the CDS 2.

[0017]

As described above, according to the present invention, even when the phase of the output signal of the image sensor input to the CDS circuit changes due to a temperature change or the like, the phase of the sample pulse supplied to the CDS circuit can be changed by the CDS circuit. By optimizing based on the output signal, a high S / N image pickup signal can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a correlated double sampling device according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining an operating state of the correlated double sampling device in the same embodiment.

FIG. 3 is a signal waveform diagram for explaining an operating state of the correlated double sampling apparatus in the same embodiment.

FIG. 4 is a block diagram showing the configuration of a conventional correlated double sampling device.

FIG. 5 is a signal waveform diagram for explaining an operating state of a conventional correlated double sampling device.

[Explanation of symbols]

 1,9 CCD 2,10 CDS circuit 3 ADC circuit 4 Memory 5 Microcomputer 6,12 Sample pulse generation circuit 7,11 Clamp pulse generation circuit 8,13 Output terminal

Claims (1)

[Claims] 1. A CCD that outputs a signal obtained by photoelectrically converting light into an electric signal using a lens or the like, a CDS circuit that is a correlated double sampling circuit that processes an output signal of the CCD, and the CDS circuit. Of the output signal of the ADC circuit, a memory for storing the output signal of the ADC circuit and outputting the stored data to the microcomputer, and a phase of the sample pulse supplied to the CDS circuit based on the output signal of the memory. A microcomputer that supplies a phase control signal for controlling the sample pulse generating circuit, and the CDS based on the phase control signal supplied from the microcomputer.
A sample pulse generating circuit for outputting a sample pulse to be supplied to the circuit; a clamp pulse generating circuit for generating a clamp pulse for clamping the DC level of the field through except the reset pulse of the CCD output signal supplied to the CDS circuit; A correlated double sampling device having an output terminal directly connected to a CDS circuit for extracting a signal.