JP2005303934A - Image scanner and method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image scanner and method, in which a high-accuracy CDS output can be obtained even when a plurality of CCD chips on a CIS operate at high speed, and to provide a program. <P>SOLUTION: An image scanner comprises a CCD chip stream 11 which outputs an analog image signal ϕOS, a sample/hold circuit 14 which includes a correlative double sampling operation mode and samples the analog image signal ϕOS, and a sampling pulse generating circuit 13 for outputting sampling pulses ϕCL, ϕSH to the sample/hold circuit 14. The sampling pulse generating circuit 13 specifies a CCD chip that is outputting the analog image signal ϕOS at present, by counting the number of CCD driving clocks ϕM from a horizontal synchronizing signal ϕHsync and if the number of fundamental clocks ϕCLK becomes the number of clocks set for the CCD chip for each specified CCD chip, sampling pulses ϕCL, ϕSH are outputted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image reading apparatus and method, and a program, and more particularly, to an image reading apparatus and method for sampling an analog image signal output from a CCD, and a program.

  When the image reading apparatus has a multi-chip type CMOS image sensor (CIS), the analog image signal output from the CCD chip includes reset noise generated when the signal is detected and 1 / f noise due to the output buffer. Has been conventionally removed by a correlated double sampling (CDS) method (see, for example, Patent Document 1).

  FIG. 5 is a diagram showing a schematic configuration of a conventional CDS circuit, and FIG. 6 is a timing chart used to explain the operation of the CDS circuit of FIG.

  In FIG. 5, a conventional image reading apparatus is connected to a CCD type photoelectric conversion element (hereinafter referred to as “CCD”) 501, a drive circuit 502 that drives the CCD 501, and a CCD 501, and is generated by a clamp pulse generation circuit 506 described later. A clamp circuit 503 that clamps the analog image signal a output from the CCD 501 based on the clamp pulse b, and a sampling pulse that is connected to the clamp circuit 503 and is generated by a sampling pulse generation circuit 505 that will be described later. a sample hold circuit 504 that samples the analog signal c output from the clamp circuit 503 based on d and φSH and outputs an output signal e; and a clamp pulse generation circuit 506 that outputs a clamp pulse b to the clamp circuit 503 , Sample hall The circuit 504 and a sampling pulse generating circuit 505 that outputs a sampling pulse d, the .phi.SH.

  The clamp circuit 503 is connected to the DC blocking capacitor 507 connected to the CCD 501, the output buffer 510 connected to the capacitor 507, and a switch 508 between the capacitor 507 and the output buffer 510 to give a clamp potential. The switch 508 opens and closes based on the clamp pulse b from the clamp pulse generation circuit 506.

  The sample hold circuit 504 includes an output buffer 513 connected to the output buffer 510 of the clamp circuit 503 via the switch 511, and a hold capacitor 512 connected between the switch 511 and the output buffer 513. Is opened and closed based on the sampling pulses d and φSH from the sampling pulse generation circuit 10.

  As shown in FIG. 6A, the waveform (negative polarity) of the analog image signal output from the CCD 501 includes a reset period tR, a field-through period tF, and a signal period tS. Reset noise and 1 / f noise (ΔV) are included in both the field through period tF and the signal period tS.

  In order to remove the noise ΔV, the clamp circuit 503 clamps the output signal in the field through period tF to the constant potential Vr by the clamp pulse b shown in FIG. 6B, and obtains a waveform after clamping ( FIG. 6 (c)).

  The sample hold circuit 504 samples and holds the waveform of the signal period by the sampling pulse φSH shown in FIG. 6 (d), thereby taking out only the signal component Vs from which the noise ΔV is removed as shown in FIG. 6 (e). be able to.

  Generally, in this type of image reading apparatus, in order to extract a good image signal, it is necessary to apply sampling pulses d and φSH to the analog image signal from the CCD 501 at an appropriate timing (phase).

Conventionally, the phase of the sampling pulses d and φSH is expected to be the optimum phase at the initial development stage, or an LSI is created, or the LSI has a built-in setting means that can change the phase of the sampling pulse, and A / D conversion is performed. There is a method of analyzing the later image data and determining the phase of the sampling pulse (see, for example, Patent Document 1).
JP 2000-125120 A

  However, in the case of a multi-chip type CMOS image sensor (CIS), the analog image signal output from the CCD 501 causes a phase difference depending on the temperature characteristics for each CCD chip, and this phase difference is the current image clock (about 1 MHz). The level confirmation time is not a problem because there is a sufficient timing margin with respect to the sampling time, but the phase difference will be shortened by shortening the pulse period due to demand for higher resolution and higher speed in the future. It is expected that the accuracy of the output signal after the CDS operation will be reduced.

  An object of the present invention is to provide an image reading apparatus and method capable of obtaining highly accurate correlated double sampling (CDS) output even when a plurality of CCD chips on a multi-chip type CMOS image sensor perform high-speed operation. And providing a program.

  2. The image reading apparatus according to claim 1, wherein a line-shaped CCD chip array, sample hold means for sample-holding an analog image signal output from the CCD chip array based on a predetermined sampling pulse, and the sampling pulse being predetermined. In an image reading apparatus comprising sampling pulse generation means for generating a phase of the sampling pulse and phase setting means for setting a predetermined phase of the sampling pulse, waveform detection for detecting an analog image signal waveform for each CCD chip in the CCD chip array The phase setting means sets a predetermined phase of the sampling pulse based on the analog image signal waveform detected for each CCD chip for each CCD chip, and the sampling pulse generation means The CCD chip based on the predetermined phase And wherein said switching the phase of generating the sampling pulses.

  2. The image reading apparatus according to claim 1, wherein the phase setting means sets the phase for generating the sampling pulse based on a register value for each CCD chip. To do.

  In order to achieve the above object, an image reading method according to claim 3, wherein the analog image signal output from the line-shaped CCD chip array is sampled and held based on a predetermined sampling pulse, and the sampling pulse. In an image reading method comprising a sampling pulse generation step for generating a predetermined phase of the sampling pulse and a phase setting step for setting a predetermined phase of the sampling pulse, an analog image signal waveform for each CCD chip in the CCD chip row is detected. A waveform detection step, wherein the phase setting step sets a predetermined phase of the sampling pulse based on an analog image signal waveform detected for each CCD chip for each CCD chip, and the sampling pulse generation step includes: The set predetermined position And it switches the phase of generating the sampling pulse for each of the CCD chip based on.

  The image reading method according to claim 4, wherein the phase setting step sets a phase for generating the sampling pulse based on a register value for each CCD chip. To do.

  In order to achieve the above object, a program according to claim 5 includes: a sample hold module that samples and holds an analog image signal output from a line-shaped CCD chip array based on a predetermined sampling pulse; A waveform for detecting an analog image signal waveform for each CCD chip in the CCD chip array in a program that causes a computer to execute a sampling pulse generation module that generates a phase of the sampling pulse and a phase setting module that sets a predetermined phase of the sampling pulse A detection module is executed by a computer, and the phase setting module sets a predetermined phase of the sampling pulse based on an analog image signal waveform detected for each CCD chip for each CCD chip, and Generating module, and also changes a phase of generating the sampling pulse for each of the CCD chip, based on the set predetermined phase.

  According to the image reading apparatus according to claim 1, the image reading method according to claim 3, and the program according to claim 5, the sampling pulse is generated based on the analog image signal waveform detected for each CCD chip for each CCD chip. When a predetermined phase is set and the phase for generating a sampling pulse is switched for each CCD chip based on the set predetermined phase, when a plurality of CCD chips on a multi-chip type CMOS image sensor perform high-speed operation In addition, a highly accurate correlated double sampling (CDS) output can be obtained.

  According to the image reading apparatus according to claim 2 and the image reading method according to claim 4, since the phase for generating the sampling pulse is set based on the register value for each CCD chip, the effect of claim 1 can be obtained reliably. be able to.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram of an image reading apparatus according to an embodiment of the present invention.

  1, the image reading apparatus according to the embodiment of the present invention generates an analog image signal φOS based on a horizontal synchronization signal φHsync, a CCD drive clock φM, and a pixel reset signal φRS output from a CCD drive circuit 12 described later. A plurality of line-shaped, for example, 3-chip CCD chip arrays 11 constituting a multi-chip type CMOS image sensor (CIS), and a correlated double sampling (CDS) operation mode connected to the CDS array 11; An analog image signal φOS output from the CCD chip array 11 based on sampling pulses φCL and φSH for determining a sampling period generated by a pulse generation circuit 13 to be described later has a DC direct connection mode in which the reference voltage Vref is constant. Sample hold circuit 14 to sample and sample N-bit, for example 8-bit data, which is connected to the yield circuit 14 and converts the analog image signal output from the sample-and-hold circuit 14 into a digital signal based on the conversion speed setting pulse φAD generated by the pulse generation circuit 13 described later. A / D conversion circuit 15, a CCD drive circuit 12 for outputting a CCD pixel clock φM, a pixel reset pulse φRS, and a horizontal synchronization signal φHsync to the CCD chip row 11 to drive the CCD chip row 11, and a sample hold circuit 14 Sampling pulses φCL and φSH at the same time, a sampling pulse generation circuit 13 for outputting a conversion speed determination pulse φAD to the A / D conversion circuit 15, and a digital signal output from the A / D conversion circuit 15; Control for controlling the CCD drive circuit 12 and the pulse generation circuit 13. And a circuit 16.

  The control circuit 16 includes a CPU 17 that controls and sets the CCD drive circuit 12 and the pulse generation circuit 13, and a memory 18 that stores a control program and necessary data. The timing at which the sampling pulse generation circuit 13 generates the conversion speed determination pulse φAD is variable by an external register. The CCD drive circuit 12 and the sampling pulse generation circuit 13 operate in synchronization with the basic clock φCLK, and these may be a GA (gate array).

  The operation of the image reading apparatus shown in FIG. 1 will be described below with reference to FIG.

  FIG. 2 is a timing chart for explaining the operation of the image reading apparatus of FIG.

  The CPU 17 outputs a basic clock φCLK in hexadecimal notation (FIG. 2 (a)). The CCD drive circuit 12 receives the horizontal synchronization signal φHsync (FIG. 2B), the CCD drive clock φM (FIG. 2C), and the pixel reset signal φRS (FIG. 2D) based on the basic clock φCLK. Output. The CCD drive clock φM has a period of 16 clocks of the basic clock φCLK. The basic clock φCLK is set to 0 when the CCD drive clock φM rises. The image reset signal φRS is a positive pulse for two basic clocks φCLK.

  The CCD chip array 11 outputs an analog image signal φOS (FIG. 2E) based on the horizontal synchronization signal φHsync, the CCD drive clock φM, and the pixel reset signal φRS output from the CCD drive circuit 12.

  The sampling pulse generation circuit 13 outputs the sampling pulses φCL (FIG. 2 (f)) and φSH (FIG. 2 (g)) at a predetermined phase. Sampling pulses φCL and φSH have a resolution of one clock of basic clock φCLK. Specifically, the sampling pulse generation circuit 13 can identify the CCD chip that is currently outputting the analog image signal φOS by counting the number of CCD drive clocks φM from the horizontal synchronization signal φHsync. Sampling pulses φCL and φSH are output when the basic clock φCLK reaches the set number of clocks for each CCD chip. Thus, the phase of the sampling pulses φCL and φSH can be switched every time the CCD chip that outputs the analog image signal φOS changes.

  The number of clocks set for each CCD chip is set in the test mode of FIG. In the case of a multi-chip type CMOS image sensor (CIS), this setting is necessary to eliminate variations in the potential difference dV between the high level and the low level for each CCD chip.

  The image reading apparatus in FIG. 1 first executes the test mode process in FIG. 3 to calculate the optimum sampling pulse phase for each CCD chip during the CDS operation.

  FIG. 3 is a flowchart of the test mode process executed by the image reading apparatus of FIG.

  In this test mode, the optimum sampling pulse phase for each CCD chip during the CDS operation is calculated.

  In FIG. 3, first, the light amount of the CIS light source is adjusted, and the shading plate is irradiated with the light amount after the adjustment, so that the analog image signal φOS shown in FIG. 2E is output (step S1). Next, the sample hold circuit 14 is set to the DC direct connection mode (step S2). The DC direct connection mode is set by setting the sample hold circuit 14 to an off state and setting the potential difference with respect to a certain reference voltage in the sample hold circuit 14 to a mode for calculating 8-bit digital data.

  The sample hold circuit 14 outputs a high level and a low level potential difference dV to perform correlation sampling in the on state, whereas in the off state, the sample hold circuit 14 performs a reference voltage at each sampling of the analog image signal φOS. The potential (absolute value) for is output.

  Further, the analog image signal φOS is sampled for a predetermined number of pixels for each CCD chip in the CCD chip array 11 (step S3). Specifically, the phase of the sampling pulse φSH is shifted by one clock from “0” to “F” (one cycle of one pixel) of the basic clock φCLK as shown in FIG. By storing the value in the memory 18, the waveform of the analog image signal φOS for each CCD chip in the CCD chip array 11 is stored in the memory 18.

  Finally, based on the stored waveform of the analog image signal φOS, register values for each CCD chip (register names: reg1, reg2, reg3) indicating the phases of the sampling pulses φCL, φSH are calculated. Is sent to the sampling pulse generation circuit 13 (step S4). The CPU 17 can specify the region where the high level value is stably output from the calculated register value as the number of clocks of the basic pulse φCLK.

  The register value is calculated in a state where the potential difference dV between the high level and the low level of the analog image signal φOS is maximized (a state in which the light amount adjustment is completed immediately below the shading plate), and the sampling pulse φCL is applied to the analog image signal φOS. When the phase is shifted by one clock from the numerical value “0” to “F” of the basic clock φCLK, the phase when the potential level of the analog image signal φOS is stable, that is, the midpoint of the range in which the same potential level continues The phase value at.

  Next, the image reading apparatus in FIG. 1 executes the reading operation mode process in FIG. 4 to perform control during the actual reading operation.

  FIG. 4 is a flowchart of the reading operation mode process executed by the image reading apparatus of FIG.

  4, first, as an initial setting, the sample hold circuit 14 is set to the CDS mode (step S5), and the register values of the sampling pulses φCL and φSH calculated in the test mode (FIG. 3) are set for each CCD chip. Then, the image reading operation is performed, and then the application-specific circuit (ASIC) counts the basic clock φCLK based on the horizontal synchronization signal φHsync, and currently outputs the analog image signal φOS. And a clamp pulse clock φCL-CK (clock that holds a high level potential) and a sample hold pulse clock φSH-CK based on the phase of the sampling pulses φCL and φSH based on the register values calculated in the processing of FIG. (Clock that holds the low-level potential) Performs CDS operations (step S7).

  In the CDS mode, for each CCD chip in the figure, a high level (potential high portion) is sampled by the sampling pulse φCL, and a low level (low potential portion) is sampled by the sampling pulse φSH, and a signal having an amplitude of the potential difference dV. Is output (FIG. 2E). The potential difference dV is a potential difference proportional to the amount of light incident on the CCD chip array 11.

  3 and 4, the phase of the sampling pulses φCL and φSH is switched every time the CCD chip that outputs the analog image signal φOS changes, so that a plurality of CCD chips on a multi-chip type CMOS image sensor are used. Even in the case of high-speed operation, it is possible to obtain a highly accurate correlated double sampling (CDS) output, and thus data deterioration and image after A / D conversion caused by the phase of sampling pulses φCL and φSH for each CCD chip. Can be prevented.

  Another object of the present invention is to supply a storage medium (or recording medium) in which a program code of software that realizes the functions of the above-described embodiments is recorded to a system or apparatus, and the computer (or CPU or MPU) of the system or apparatus. Needless to say, this is also achieved by reading and executing the program code stored in the storage medium.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.

  Further, after the program code read from the storage medium is written in a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the CPU or the like provided in the card or the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

  The above-described program only needs to be able to realize the functions of the above-described embodiments by a computer, and the form includes forms such as object code, a program executed by an interpreter, and script data supplied to the OS. But you can.

  As a recording medium for supplying the program, for example, RAM, NV-RAM, floppy (registered trademark) disk, optical disk, magneto-optical disk, CD-ROM, MO, CD-R, CD-RW, DVD (DVD-ROM, DVD-RAM, DVD-RW, DVD + RW), magnetic tape, non-volatile memory card, other ROM, etc. may be used as long as they can store the above programs. Alternatively, the program is supplied by downloading from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like.

1 is a block diagram of an image reading apparatus according to an embodiment of the present invention. 2 is a timing chart for explaining the operation of the image reading apparatus in FIG. 1. 2 is a flowchart of a test mode process executed by the image reading apparatus in FIG. 1. 2 is a flowchart of a reading operation mode process executed by the image reading apparatus in FIG. 1. It is a figure which shows schematic structure of the conventional CDS circuit. 6 is a timing chart for explaining the operation of the CDS circuit of FIG. 5.

Explanation of symbols

11 CCD row 12 CCD drive circuit 13 sampling pulse generation circuit 14 sampling hold circuit 15 A / D conversion circuit 16 control circuit 17 CPU
18 memory

Claims (5)

A line-shaped CCD chip array; sample hold means for sample-holding an analog image signal output from the CCD chip array based on a predetermined sampling pulse; and sampling pulse generating means for generating the sampling pulse at a predetermined phase In an image reading apparatus comprising phase setting means for setting a predetermined phase of the sampling pulse,
Waveform detection means for detecting an analog image signal waveform for each CCD chip in the CCD chip array is provided, and the phase setting means performs sampling based on the analog image signal waveform detected for each CCD chip for each CCD chip. An image reading apparatus, wherein a predetermined phase of a pulse is set, and the sampling pulse generating means switches a phase for generating the sampling pulse for each CCD chip based on the set predetermined phase.   2. The image reading apparatus according to claim 1, wherein the phase setting means sets a phase for generating the sampling pulse based on a register value for each CCD chip. A sample hold step for sample-holding an analog image signal output from a line-shaped CCD chip array based on a predetermined sampling pulse, a sampling pulse generation step for generating the sampling pulse at a predetermined phase, and a predetermined sampling pulse An image reading method comprising: a phase setting step for setting the phase of
A waveform detecting step for detecting an analog image signal waveform for each CCD chip in the CCD chip array, wherein the phase setting step is performed based on the analog image signal waveform detected for each CCD chip for each CCD chip; An image reading method, wherein a predetermined phase of a pulse is set, and the sampling pulse generating step switches a phase for generating the sampling pulse for each CCD chip based on the set predetermined phase.   4. The image reading method according to claim 3, wherein the phase setting step sets a phase for generating the sampling pulse based on a register value for each CCD chip. A sample hold module that samples and holds an analog image signal output from a line-shaped CCD chip array based on a predetermined sampling pulse, a sampling pulse generation module that generates the sampling pulse at a predetermined phase, and a predetermined sampling pulse In a program, an image reading method for causing a computer to execute a phase setting step for setting the phase of
A computer executes a waveform detection module for detecting an analog image signal waveform for each CCD chip in the CCD chip array, and the phase setting module is based on the analog image signal waveform detected for each CCD chip for each CCD chip. And setting a predetermined phase of the sampling pulse, and the sampling pulse generating module switches a phase for generating the sampling pulse for each of the CCD chips based on the set predetermined phase.

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