CN114125338A - Time sequence synchronization method based on 3D integrated chip - Google Patents
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Abstract
The invention relates to a time sequence synchronization method based on a 3D integrated chip, which introduces a time sequence synchronization control device and a 3D integrated chip, wherein the 3D integrated chip internally comprises a CCD chip and a CMOS chip and comprises the following steps: generating timing trigger pulses for the CCD chip and the CMOS chip by using a timing synchronization control device; starting working time sequences of the CCD chip and the CMOS chip according to the time sequence trigger pulse; measuring the time sequence synchronization condition of the CCD chip and the CMOS chip by using a time sequence test port, and recording a time sequence synchronization error; according to the time sequence synchronization error, a time sequence synchronization control device is adopted to finely adjust the relative positions of the time sequence trigger pulse of the CCD chip and the time sequence trigger pulse of the CMOS chip, so that the complete time sequence synchronization of the CCD chip and the CMOS chip is realized; the method has the advantages of flexible implementation mode, insensitivity to uncertain factors in the process, adjustable time sequence synchronization precision and strong adaptability, and solves the problems of delay uncertainty and time sequence synchronization risk caused by heterogeneous integration between a CCD process and a CMOS process.
Description
Technical Field
The invention relates to a time sequence synchronization method based on a 3D integrated chip, in particular to a 3D integrated image sensor time sequence synchronization technology with a CCD pixel structure and a CMOS circuit fused.
Background
The image sensor is mainly of two types, namely, a CCD (Charge coupled Device) and a CMOS (Complementary Metal Oxide Semiconductor), as the most important components of the camera. The CCD image sensor has the characteristics of large full-well capacity, high dynamic range and wide spectrum and high quantum efficiency, is often applied to hyperspectral imaging and military target detection and analysis, but has the defects of complex camera system, high power consumption, large volume, high cost and the like. The CMOS image sensor has the advantages of low cost, low power consumption, high integration and faster readout speed, and is often applied to scenes with large data volume, such as high-definition monitoring, but the performance of the CMOS image sensor is inferior to that of the CCD image sensor. Therefore, in order to combine the advantages of the CCD and the CMOS, a 3D integrated image sensor based on the combination of the CCD structure and the CMOS circuit has been increasingly researched.
The 3D integrated image sensor relates to multi-chip integration, and needs to consider differences of chips in process procedures, working voltages, signal delays and the like besides integration process influence, and in view of the above factors, the 3D integrated image sensor may have the problems that the internal inter-chip interface timing is asynchronous and cannot work according to expected timing requirements. In view of the above problem, it is important to actively explore a timing synchronization method capable of eliminating uncertainty factors of timing delay and further realizing cooperative work among sub-chips in a 3D integrated image sensor.
Disclosure of Invention
In order to solve the above problems, the present invention provides a timing synchronization method based on a 3D integrated chip, wherein a timing synchronization control device and the 3D integrated chip are introduced, the 3D integrated chip internally includes a CCD chip and a CMOS chip, and the method includes:
respectively generating a time sequence trigger pulse for a CCD chip and a time sequence trigger pulse for a CMOS chip by using a time sequence synchronous control device;
respectively starting the working time sequences of the CCD chip and the CMOS chip according to the time sequence trigger pulse for the CCD chip and the time sequence trigger pulse for the CMOS chip;
after the working time sequence is started, measuring the time sequence synchronization condition of the CCD chip and the CMOS chip, and recording the time sequence synchronization error;
according to the time sequence synchronization error, a time sequence synchronization control device is adopted to finely adjust the relative positions of the time sequence trigger pulse of the CCD chip and the time sequence trigger pulse of the CMOS chip, so that the complete time sequence synchronization of the CCD chip and the CMOS chip is realized.
Further, the process of reading out the frame data of the 3D integrated chip includes:
when the CCD chip receives the CCD time sequence trigger pulse, a CCD driving time sequence signal is sent out, and the current frame signal is integrated through a fixed time sequence delay td 1;
after the integration is finished, generating a CCD charge packet signal, transferring the CCD charge packet signal from the first row to the last row of the CCD chip array, and after the transfer is finished, generating an image current signal or a CCD reset voltage signal and a CCD image voltage signal by the CCD chip;
after the generated CCD image current signal or CCD reset voltage signal and CCD image voltage signal are sent to the CMOS chip, the CCD chip starts to integrate the next frame signal;
when the CCD time sequence trigger pulse passes through the adjustable time sequence delay td2, the time sequence synchronous control device generates a CMOS time sequence trigger pulse;
after the CMOS chip receives the CMOS time sequence trigger pulse, the CMOS chip generates a CMOS sampling reset time sequence to synchronously sample the received CCD reset voltage signal through a fixed time sequence delay td3, and then generates a CMOS sampling signal time sequence to synchronously sample the received CCD image current signal or the CCD image voltage signal;
after the current CMOS sampling signal is subjected to time sequence synchronous sampling, PGA processing is carried out on the sampled signal to obtain a PGA processed signal;
performing ADC on the PGA processed signal, and realizing digital output after ADC
Further, the relative position of the timing trigger pulse of each chip is finely adjusted by adopting the timing synchronization control device to move left, and the method comprises the following steps:
the synchronous control device determines a time sequence synchronous error value delta t and converts the time sequence synchronous error value into a clock cycle number N;
the synchronous control device finely adjusts the adjustable time sequence delay td2 according to the clock period number N, so that the CMOS time sequence trigger pulse moves leftwards for time delay delta t;
after the CMOS time sequence trigger pulse moves leftwards by delta t time delay, the CMOS sampling reset time sequence and the CMOS sampling signal time sequence synchronously move leftwards by delta t time delay correspondingly;
and after the CMOS sampling reset time sequence and the CMOS sampling signal time sequence move leftwards for a time delay of delta t, the CCD reset voltage signal and the CMOS sampling reset time sequence as well as the CCD image signal and the CMOS sampling signal time sequence are completely synchronous.
Further, the CCD chip and the CMOS chip are interconnected by utilizing a 3D integration mode to finally form a 3D integrated chip, and each chip inside the 3D integrated chip is provided with a time sequence trigger port and a time sequence test port, wherein:
the time sequence trigger port is used for receiving the time sequence trigger pulse generated by the time sequence synchronous control device;
and the time sequence test port is used for measuring the internal time sequence state of the CCD chip and the internal time sequence state of the CMOS chip.
Further, the CCD chip device structure comprises TDI and EM frameworks;
furthermore, a 3D integration mode adopts a process integration or packaging mode, and the process integration comprises TSV, MCM, SIP, WLP and RDP;
furthermore, the implementation mode of the time sequence synchronous control device adopts an off-chip control chip form independent of the 3D integrated chip, or adopts a form of integrating the 3D integrated chip as a functional module;
the off-chip control chip independent of the 3D integrated chip is adopted, for example, the FPGA-based programmable control chip is adopted, the function of the time sequence synchronous control device can be conveniently modified and adjusted in real time, and the 3D integrated sensor is integrated in the 3D integrated chip and serves as a functional module, so that the integration degree of the 3D integrated sensor is higher, and the design complexity of a peripheral circuit of the 3D integrated sensor can be further simplified.
Furthermore, the time sequence synchronous control device can generate a time sequence trigger pulse for the CCD chip and a time sequence trigger pulse device for the CMOS chip and start the internal working time sequence of each chip; when the time sequence trigger pulse is respectively input to the CCD chip and the CMOS chip, the corresponding pulse signal can be detected in the CCD chip and the CMOS chip, and then the pulse signal is utilized to start the internal working time sequence of each corresponding sub-chip.
Furthermore, the timing synchronization control device adjusts the relative positions of the timing trigger pulse of the CCD chip and the timing trigger pulse of the CMOS chip in a mode of adjusting an internal control register;
by setting corresponding control registers and the like, the time sequence positions of the CCD chip time sequence trigger pulse and the CMOS chip time sequence trigger pulse are changed along with the adjustment of the register value, and the relative positions of the generated CCD chip time sequence trigger pulse and the CMOS chip time sequence trigger pulse are adjusted.
The relative position of the time sequence trigger pulse is adjusted by taking the clock period as a precision unit, and the value of the clock period is adjustable. In addition, for the measurement and adjustment of the timing synchronization situation, the method can adopt the modes including but not limited to manual calculation implementation or program automatic implementation.
Compared with the prior art, the invention has the beneficial technical effects that: based on the time sequence synchronization method based on the 3D integrated chip provided by the invention, the complete time sequence synchronization of the CCD chip and the CMOS chip in the 3D integrated sensor can be well realized by using the time sequence synchronization control device. The method has the advantages of flexible implementation mode, insensitivity to uncertain factors in the process, adjustable time sequence synchronization precision and strong adaptability, and solves the problems of delay uncertainty and time sequence synchronization risk caused by heterogeneous integration between a CCD process and a CMOS process.
Drawings
FIG. 1 is a block diagram of a synchronous control apparatus according to the present invention;
FIG. 2 is an overall timing diagram of the 3D integrated sensor of the present invention;
FIG. 3 is a schematic diagram of the timing shift left fine tuning of the present invention;
FIG. 4 is a schematic diagram of the timing shift fine adjustment of the present invention;
FIG. 5 is a flow chart of the timing synchronization of the present invention;
101-upper side CMOS reading chip, 102-CCD array chip, 103-lower side CMOS reading chip, 104-upper side interconnection wire, 105-lower side interconnection wire, 106-3D integrated sensor chip, 107-time sequence synchronous control device, 108-time sequence trigger pulse of CCD array chip, 109-time sequence trigger pulse of CMOS reading chip, 110-synchronous test signal output of CMOS reading chip, and 111-synchronous test signal output of CCD array chip;
204-a CCD first frame timing trigger pulse, 205-a CCD second frame timing trigger pulse, 206-a CCD first frame charge transfer, 207-a CCD second frame charge transfer, 208-a current signal, 210-a CCD first frame reset voltage signal, 211-a CCD first frame image signal, 214-a CMOS first frame timing trigger pulse, 216-a CMOS first frame sampling reset timing, 218-a CMOS first frame sampling signal timing;
302-CMOS timing trigger pulse, 303-CCD reset signal, 304-CCD image signal, 305-CMOS sample reset timing, 306-CMOS sample signal timing,
402-CMOS timing trigger pulse, 403-CCD reset signal, 404-CCD image signal, 405-CMOS sampling reset timing and 406-CMOS sampling signal timing.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A3D integrated chip-based time sequence synchronization method is provided, the 3D integrated sensor internally comprises a CCD chip and a CMOS chip, and the time sequence synchronization comprises the following steps:
generating a timing trigger pulse for a CCD chip and a timing trigger pulse for a CMOS chip by using a timing synchronous control device;
starting the working time sequence of the CCD chip and the CMOS chip according to the time sequence trigger pulse for the CCD chip and the time sequence trigger pulse for the CMOS chip;
after the working time sequence is started, measuring the time sequence synchronization condition of the CCD chip and the CMOS chip by using a time sequence test port, and recording a time sequence synchronization error;
according to the time sequence synchronization error, a time sequence synchronization control device is adopted, and the relative positions of the time sequence trigger pulse of the CCD chip and the time sequence trigger pulse of the CMOS chip are finely adjusted by taking a clock period as a unit, so that the complete time sequence synchronization of the CCD chip and the CMOS chip is realized.
In one embodiment, the timing synchronization process based on the 3D integrated chip is shown in fig. 5, and includes:
s1, after the 3D integrated sensor is powered on, starting a time sequence synchronization control module;
s2, the timing synchronization control module generates a CCD timing trigger pulse and a CMOS timing trigger pulse, and respectively starts the working timing of the CCD chip and the CMOS chip;
s3, after the working time sequence is started, the time sequence testing port is used for measuring the time sequence synchronization condition of the CCD chip and the CMOS chip, the time sequence synchronization error is recorded, whether the synchronization error meets the synchronization requirement is judged, if yes, the time sequence synchronization control process is ended, otherwise, the step S4 is entered;
s4, converting the synchronous error value into a clock cycle number, determining the time sequence moving direction and adjusting the time sequence synchronous control module;
s5, the timing synchronization control module finely adjusts the relative position of the timing trigger pulse according to the clock period number and the timing moving direction, and returns to the step S3 until the timing synchronization is completed.
In one example, as shown in fig. 1, a block diagram of a timing synchronization control apparatus is shown, and takes a four-phase transfer structure and a CCD array chip 102 adopting a bilateral readout mode as an example, according to a 3D integrated interconnection mode, an upper CMOS readout chip 101 is connected to the CCD array chip 102 through an upper interconnection wire 104, and a lower CMOS readout chip 103 is connected to the CCD array chip 102 through a lower interconnection wire 105;
the timing synchronization control device 107 is used for generating timing trigger pulses of the CCD array chip and timing trigger pulses of the CMOS chip, and is also used for adjusting the relative timing position relation of the trigger pulses by using a register and the like;
when the 3D integrated sensor chip 106 is powered on, the timing synchronization control device 107 is started, and generates a timing trigger pulse 108 of the CCD array chip and a timing trigger pulse 109 of the CMOS readout chip, and starts internal operation timings of the CCD array chip 102, the upper side CMOS readout chip 101, and the lower side CMOS readout chip 103 according to the corresponding timing trigger pulses, and image signals of the CCD array chip are respectively output to the corresponding upper side CMOS readout chip 101 and lower side CMOS readout chip 103 through the upper side interconnection wire 104 and the lower side interconnection wire 105 under the driving of the corresponding operation timings; when the image signal of the CCD array chip reaches the output port of the CCD array chip, the sampling time sequence of the CMOS reading chip synchronously samples the CCD image signal, however, the CCD array chip and the CMOS chip work relatively independently, and the difference of the CCD array chip and the CMOS chip in the aspects of process, working voltage, signal delay and the like is considered, so that the sampling time sequence and the image signal cannot be completely synchronous.
In order to ensure the cooperative work of the CCD array chip and the CMOS chip, the synchronization between the image signal of the CCD array chip and the sampling time sequence of the upper side CMOS reading chip 101 and the synchronization between the image signal of the CCD array chip and the sampling time sequence of the lower side CMOS reading chip 103 are respectively measured.
In the measuring process, as the 3D integrated sensor chip is integrally packaged, the time sequence state between the internal chips can not be directly acquired, the synchronous test signal output of the CMOS chip and the synchronous test signal output 111 of the CCD array chip are measured to determine the internal timing operation state, and recording synchronization errors according to the synchronization condition of the time sequence state, finely adjusting the time sequence position relation between the time sequence trigger pulse of the CCD array chip and the time sequence trigger pulse of the CMOS chip by using a built-in control register of the time sequence synchronization control device 107 until the sampling time sequence of the CMOS chip is just completely synchronized with the output time sequence of the CCD image signal, so that the sampling reading of the image signal of the CCD array chip 102 by the upper CMOS chip reading chip 101 and the lower CMOS reading chip 103 is realized, and the time sequence synchronization among the chips in the 3D integrated sensor chip 106 is completed.
In another example, a 3D integrated sensor overall timing diagram is shown in fig. 2:
when the 3D integrated sensor is powered on, the timing synchronization control device starts and generates a CCD first frame timing trigger pulse 204, after a fixed timing delay td1, a CCD first frame charge transfer timing sequence 206 appears to complete transfer of CCD integrated charge packets, and an image current signal 208 or a CCD first frame reset voltage signal 210 and a CCD first frame image signal 211 are transmitted from a CCD output port to an input port of a CMOS chip through 3D interconnection;
if the image current signal 208 is transmitted from the CCD output port to the input port of the CMOS chip through 3D interconnection, sampling is carried out under the time sequence control through a ctia circuit;
after the CCD first frame timing trigger pulse 204 passes through the adjustable timing delay td2, the timing synchronization control device generates a CMOS first frame timing trigger pulse 214, and after passing through the fixed timing delay td3, generates a CMOS first frame sampling reset timing 216 and a CMOS first frame sampling signal timing 218; at this time, the CMOS first frame sampling reset timing sequence 216 should synchronously sample the CCD first frame reset voltage signal 210, the CMOS first frame sampling signal timing sequence 218 should synchronously sample the CCD first frame image voltage signal 211 or the CCD image current signal 208, so as to achieve timing synchronization and signal sampling of the CCD chip and the CMOS chip, the CCD chip receives the second frame CCD trigger pulse signal 205, and so on, and then the sampled CCD signal is subjected to PGA processing, ADC analog-to-digital conversion, and interface format processing, so as to achieve digital output, and finally achieve a 3D integrated sensor function.
In an embodiment, the specific operation of the register in the timing synchronization control device for adjusting the relative position of the timing trigger pulse is to modify an internal predefined register value by using a chip communication mode, so as to adjust the count value of the timing counter, and finally, adjust the high and low level positions of the timing pulse, thereby implementing the left and right fine adjustment of the timing pulse.
Preferably, the timing synchronization control device performs left shift fine adjustment or right shift fine adjustment on the relative position of the CCD chip timing trigger pulse and the CMOS chip timing trigger pulse by adjusting the internal control register, wherein the left shift fine adjustment of the relative position of the timing trigger pulse by the timing synchronization control device includes:
the synchronization control device determines a time value delta t of the timing synchronization error and converts the time value of the timing synchronization error into a clock period number N;
the synchronous control device finely adjusts the value of the adjustable time sequence delay td2 according to the number N of the clock cycles, so that the CMOS time sequence trigger pulse moves leftwards for a time delay of delta t;
after the CMOS time sequence trigger pulse moves leftwards by delta t time delay, the CMOS sampling reset time sequence and the CMOS sampling signal time sequence synchronously move leftwards by delta t time delay correspondingly;
after the CMOS sampling reset time sequence and the CMOS sampling signal time sequence move leftwards for a time delay of delta t, the CCD reset voltage signal and the CMOS sampling reset time sequence are completely synchronous, and the CCD image signal and the CMOS sampling signal time sequence are also completely synchronous.
Timing shift left fine tuning schematic diagram, as shown in fig. 3:
when the CCD reset signal 303 is not completely synchronized with the CMOS sample reset timing 305, and the CCD image signal 304 is not completely synchronized with the CMOS sample signal timing 306, there is an inter-chip timing alignment error, by adjusting the timing synchronization control to fine tune the timing delay td2, the CMOS timing trigger pulse 302 is shifted to the left by an deltat time delay, since the timing delay td3 remains fixed, the CMOS sample reset timing 305 and CMOS sample signal timing 306 are correspondingly synchronously shifted to the left by the deltat time delay, since the timing synchronization error value of the CCD reset signal 303 and the CMOS sampling reset timing 305, and the CCD image signal 304 and the CMOS sampling signal timing 306 is exactly at time delay, therefore, after the timing synchronization control device adjusts the timing to the left, the CCD reset signal 303 and the CMOS sampling reset timing 305, and CCD image signal 304 is fully synchronized with CMOS sampling signal timing 306.
The timing shift right fine tuning principle is shown in fig. 4, and is the same as the timing shift left fine tuning principle:
when the CCD reset signal 403 and the CMOS sampling reset timing 405, and the CCD image signal 404 and the CMOS sampling signal timing 406 are not completely synchronized, there is an inter-chip timing alignment error, by adjusting the timing synchronization control to fine tune the timing delay td2, the CMOS timing trigger pulse 402 is shifted to the right by an deltat time delay, since the timing delay td3 remains fixed, the CMOS sample reset timing 405 and CMOS sample signal timing 406 are correspondingly synchronized to the right by the deltat time delay, since the timing synchronization error values of the CCD reset signal 403 and the CMOS sampling reset timing 405, and the CCD image signal 404 and the CMOS sampling signal timing 406 are exactly at time delay, therefore, after the timing synchronization control device adjusts the timing to the right, the CCD reset signal 403 and the CMOS sampling reset timing 405, and the CCD image signal 404 is fully synchronized with the CMOS sampling signal timing 406.
Preferably, a 3D integrated sensor with a pixel array size of 2048 × 256 is taken as an example. The 3D integrated sensor comprises a 2048 multiplied by 256 array CCD array chip and two 2048 column processed CMOS circuit structure chips, integrated packaging is completed in a 3D integrated interconnection mode, and 3D integrated interconnection and electrical conduction are realized through 2048 column output ports on two sides of the CCD array chip and input ports of the other two 2048 column read-out circuit CMOS chips through 3D integration.
Based on the 3D integrated sensor, in order to accurately sample, process and output the column photoelectric signals output by the CCD array chip in the sensor by the CMOS readout circuits on both sides, the timing synchronization control device and the timing synchronization method need to be used. Firstly, after a 3D integrated sensor chip is powered on, a synchronous time sequence t1 of a CCD array chip time sequence test port and synchronous output time sequences t2 and t3 of other two CMOS reading circuit chip time sequence test ports are respectively measured by using an oscilloscope, synchronous error measurement is carried out on t1, t2 and t3 according to the synchronous time sequence requirement required by the work of the 3D sensor, if the time sequence synchronous error meets the design requirement, time sequence synchronous adjustment is not needed, if the synchronous error is greater than the time sequence synchronous requirement, the time sequence error value is converted into clock number with a clock period as a unit, and then a time sequence synchronous control module is used for carrying out left-right shift fine adjustment operation on a time sequence trigger pulse of the CCD chip or the CMOS chip until the time sequence error between the CCD chip and the CMOS chip meets the work time sequence requirement.
Based on the time sequence synchronous control device and method, the CCD array chip and the CMOS reading circuit chip in the 3D integrated sensor can work cooperatively according to the required working time sequence, and further the problems of delay uncertainty and time sequence synchronous risk caused by heterogeneous integration between the CCD process and the CMOS process are solved.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. A time sequence synchronization method based on a 3D integrated chip is characterized in that a time sequence synchronization control device and the 3D integrated chip are introduced, the 3D integrated chip internally comprises a CCD chip and a CMOS chip, and the time sequence synchronization comprises the following steps:
respectively generating a time sequence trigger pulse for a CCD chip and a time sequence trigger pulse for a CMOS chip by using a time sequence synchronous control device;
respectively starting the working time sequences of the CCD chip and the CMOS chip according to the time sequence trigger pulse for the CCD chip and the time sequence trigger pulse for the CMOS chip;
after the working time sequence is started, measuring the time sequence synchronization condition of the CCD chip and the CMOS chip, and recording the time sequence synchronization error;
according to the time sequence synchronization error, a time sequence synchronization control device is adopted to finely adjust the relative positions of the time sequence trigger pulse of the CCD chip and the time sequence trigger pulse of the CMOS chip, so that the complete time sequence synchronization of the CCD chip and the CMOS chip is realized.
2. The method of claim 1, wherein the reading of a frame of data by the 3D ic comprises:
when the CCD chip receives the CCD time sequence trigger pulse, a CCD driving time sequence signal is sent out, and the current frame signal is integrated through a fixed time sequence delay td 1;
after the integration is finished, generating a CCD charge packet signal, transferring the CCD charge packet signal from the first row to the last row of the CCD chip array, and generating a CCD image current signal or a CCD image voltage signal by the CCD chip after the transfer is finished;
after the generated CCD image current signal or CCD reset voltage signal and CCD image voltage signal are sent to the CMOS chip, the CCD chip starts to integrate the next frame signal;
when the CCD time sequence trigger pulse passes through the adjustable time sequence delay td2, the time sequence synchronous control device generates a CMOS time sequence trigger pulse;
after the CMOS chip receives the CMOS time sequence trigger pulse, the CMOS chip generates a CMOS sampling reset time sequence to synchronously sample the received CCD reset voltage signal through a fixed time sequence delay td3, and then generates a CMOS sampling signal time sequence to synchronously sample the received CCD image current signal or the CCD image voltage signal;
after the current CMOS sampling signal is subjected to time sequence synchronous sampling, PGA processing is carried out on the sampled signal to obtain a PGA processed signal;
and performing ADC (analog to digital converter) conversion on the signal processed by the PGA, and realizing digital output after ADC conversion.
3. The timing synchronization method according to claim 1, wherein the timing synchronization control device performs left-shift fine adjustment or right-shift fine adjustment on the relative positions of the timing trigger pulse of the CCD chip and the timing trigger pulse of the CMOS chip by adjusting an internal control register, and the left-shift fine adjustment of the relative positions of the timing trigger pulses by using the timing synchronization control device comprises:
the synchronization control device determines a time value delta t of the timing synchronization error and converts the time value of the timing synchronization error into a clock period number N;
the synchronous control device finely adjusts the value of the adjustable time sequence delay td2 according to the number N of the clock cycles, so that the CMOS time sequence trigger pulse moves leftwards for a time delay of delta t;
after the CMOS time sequence trigger pulse moves leftwards by delta t time delay, the CMOS sampling reset time sequence and the CMOS sampling signal time sequence synchronously move leftwards by delta t time delay correspondingly;
after the CMOS sampling reset time sequence and the CMOS sampling signal time sequence move leftwards for a time delay of delta t, the CCD reset voltage signal and the CMOS sampling reset time sequence are completely synchronous, and the CCD image signal and the CMOS sampling signal time sequence are also completely synchronous.
4. The method for timing synchronization based on 3D integrated chip as claimed in claim 1 or 3, wherein the relative position of the timing trigger pulse is adjusted by taking the clock period as a precision unit, and the clock period is adjustable.
5. The timing synchronization method based on the 3D integrated chip as claimed in claim 1, wherein the CCD chip device structure comprises TDI and EM architecture.
6. The timing synchronization method based on the 3D integrated chip according to claim 1, wherein the CCD chip and the CMOS chip are interconnected by a 3D integration method to finally form the 3D integrated chip, and each chip inside the 3D integrated chip is provided with a timing trigger port and a timing test port, wherein:
the time sequence trigger port is used for receiving the time sequence trigger pulse generated by the time sequence synchronous control device;
and the time sequence test port is used for measuring the internal time sequence state of the CCD chip and the internal time sequence state of the CMOS chip.
7. The timing synchronization method based on the 3D integrated chip as claimed in claim 6, wherein the 3D integration mode is a process integration or packaging mode, and the process integration includes TSV, MCM, SIP, WLP, and RDP.
8. The method for timing synchronization based on 3D integrated chip as claimed in claim 1, wherein the timing synchronization control device is implemented in an off-chip control chip independent from the 3D integrated chip or integrated inside the 3D integrated chip as a functional module.
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| CN117074925A (en) * | 2023-10-16 | 2023-11-17 | 中诚华隆计算机技术有限公司 | 3D chip test analysis method and system |
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