JPH0965216A - Output signal processing circuit for ccd element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain stable signal processing without dispersion by eliminating unstable factors of a pulse relating to a noise suppression operation in an output signal processing circuit of a CCD element. SOLUTION: An analog signal from a CCD element 1 is converted into a digital signal for a period of a basic clock signal from the CCD element 1. The digital signal is delayed by one period of the basic clock signal by a delay circuit 3 and the delayed signal is subtracted from the original digital signal before the delay. Only the signal for the signal component period of the CCD element 1 among the subtraction signals is converted into an analog signal and held to obtain a desired output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output signal processing circuit for a CCD element, and more particularly to a technology for eliminating the instability factor of the processing circuit and stably and accurately suppressing the noise of the signal from the CCD image pickup element. Regarding

[0002]

2. Description of the Related Art FIG. 3 shows an example of a signal processing circuit for processing an output of a CCD element to obtain a desired video signal output. The circuit shown in FIG. 1 includes a CCD device 10 such as a CCD image pickup device used in, for example, a video camera, a clamp circuit 11, and a sample hold circuit 12.

The clamp circuit 11 clamps the output signal A from the CCD element 10 to a predetermined DC potential by a clamp pulse B. Further, the sample hold circuit 12 receives the signal clamped to a predetermined potential by the clamp circuit 11, extracts a predetermined portion of the signal by sampling, holds this value until the next sampling, and outputs the video signal output D. It is provided.

Specifically, as shown in FIG. 4, the output signal A of the CCD element 10 has a cycle of three times the cycle t of the basic clock signal (not shown) supplied to the CCD element 10. The first period t1 is a switching period related to charge transfer of the CCD element, the next period t2 is a feedthrough period, and the last period t3 is a signal component period having a level corresponding to the video signal level.

In order to obtain the video signal output, the signal level in the signal component period t3 may be extracted, but normally the output signal of the CCD element has level fluctuation, that is, fluctuation, as shown by the dotted line F. . The level of the signal component period t3, that is, the video signal level is the feedthrough period t2.
With reference to, a minimum level (for example, a black level) N1 and a maximum level (for example, a white level) N2 are changed.

Therefore, in consideration of such fluctuation of the output signal A of the CCD element 10 and the fact that the video signal level is relative to the level of the feedthrough period t2, predetermined signal processing is performed on the signal A. By applying it, it is possible to suppress noise due to fluctuations and obtain a video signal of an appropriate level with respect to the feedthrough level.

That is, in the clamp circuit 11, CC
The signal A is clamped to a predetermined DC potential in each feedthrough period t2 by using the clamp pulse B which becomes high level during the feedthrough period of the output signal A of the D element 10. The sample and hold circuit 12 samples and holds the signal clamped in this way in the signal component period t3 by the sampling pulse C which becomes high level in the signal component period t3. By this, the video signal output D
As a result, the signal level of the feedthrough period t2, that is, the signal level of the signal component period with respect to the feedthrough level is obtained. Such a video output signal D is not affected by such a fluctuation even if the feedthrough level fluctuates due to fluctuations in the output signal A of the CCD element.

As another conventional example, as shown in, for example, US Pat. No. 4,845,382, the feedthrough level of the output signal of the CCD element is sample-held and output, and the video signal level in the signal component period. Is also sampled and held by another sample and hold circuit, and a so-called correlated double sampling circuit is also used to remove the influence of fluctuations by taking the difference between these two sampled and held signals.

[0009]

In these conventional signal processing circuits, it is necessary to clamp and sample the output signal of the CCD element at an appropriate phase by a clamp pulse and a sampling pulse having a predetermined phase. However, in these conventional signal processing circuits, since the output signal of the CCD element is processed as an analog signal as it is, the phase of the clamp pulse that clamps the output signal of the CCD element first in the feed-through period and then the signal component period. Since the phase relationship of the sampling pulse for performing sample-holding is extremely delicate, a phase change or the like occurs due to the wiring process of the electric circuit, and extremely delicate adjustment is necessary to perform stable signal processing. Further, there is a disadvantage that the phase relationship of these pulses becomes unstable due to various factors such as a change in ambient temperature and a change in power supply voltage, and as a result, the output signal of the CCD element cannot be stably processed. It was

In order to simplify or eliminate the adjustment of the clamp pulse and the sampling pulse, the generation of these pulses is performed by the clock generation circuit of the CCD element as described in, for example, Japanese Patent Laid-Open No. 5-83645. Instead of doing so, an output signal processing circuit is disclosed which creates these pulses from the output signal itself of the CCD element.

However, even in such an output signal processing circuit, the clamp pulse and the sampling pulse are generated from the analog signal output of the CCD element, and the circuit for generating the pulse pulse is also generated by analog processing. However, it is still difficult to stabilize the timing of each pulse, and there is the inconvenience that stable signal processing cannot be performed, such as fluctuations in the pulse timing due to variations in CCD elements.

Therefore, in view of the problems in the circuits of these conventional examples, an object of the present invention is to provide an output signal processing circuit of a CCD device, in which circuit device variations, temperature changes and other parameter changes, and electrical circuit wiring processing. Without being affected by fluctuations in circuit parameters due to
It is to enable extremely stable and uniform signal processing so that a non-adjustable and high-performance signal processing circuit can be realized.

[0013]

In order to achieve the above object, an output signal processing circuit of a CCD device according to the present invention comprises:
A / D converter (2) for converting an analog output signal from the CCD element (1) into a digital signal at the cycle of the basic clock signal of the CCD element (1), and the digital signal obtained by A / D conversion A delay circuit (3) for delaying the basic clock by one cycle time, and a digital subtractor (4) for performing a subtraction between the output of the delay circuit (3) and the original digital signal before delay, It is characterized in that the processed signal output is obtained from the output of the digital subtractor (4) during the signal component period of the CCD element (1).

According to this structure, the analog output signal from the CCD element (1) is converted into a digital signal by the A / D converter (2) at the cycle of the basic clock signal of the CCD element, and the digital signal processing is performed. The subsequent signal processing is performed. Therefore, the timing of each signal processing is appropriately regulated at the timing of the basic clock signal of the CCD element, and the signal processing of the delay circuit (3) and the subtractor (4) is also performed digitally.
As in the conventional example, the instability factor of the circuit processing due to the instability of the phase of each pulse is eliminated, and stable and uniform noise suppression processing can be performed.

Further, in the above configuration, it is convenient that the digital subtractor is configured to perform digital subtraction and output subtraction data for each period corresponding to the signal component period of the CCD element. In this case, the subtraction data output from the digital subtractor is only during the signal component period of the CCD element, and the extra data in other periods is not output. Therefore, the subsequent signal processing is simplified and unnecessary noise components are generated. Will no longer be output.

Further, the D / A converter (5) for converting the output of the digital subtractor into an analog signal and outputting the analog signal, and the output of the D / A converter (5) by the following D / A converter. It is convenient to further provide a hold circuit for holding until output. A signal from which high frequency noise such as a pulse signal component has been removed by the D / A converter and the hold circuit is obtained as a substantially continuous signal.

Further, the D / A converter (5) may be configured to sample and hold an input signal and perform D / A conversion in each period corresponding to the signal component period of the CCD element (1). . In this case, it is not necessary to control the digital subtractor (4) so as to perform digital subtraction every period corresponding to the signal component period of the CCD element (1), and the CCD element in the D / A converter (5) is not necessarily controlled. It is possible to extract, hold, and output only the signal in the desired signal component period of.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A signal processing circuit as one mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of an output signal processing circuit of a CCD element according to an embodiment of the present invention. The circuit in the figure is
For example, a CCD device 1 such as a CCD image sensor used in a video camera, an A / D converter 2, a delay circuit 3,
It is composed of a subtractor 4, a D / A converter 5, a hold circuit 6, a clock generator 7, and the like.

The clock generator 7 includes a CCD element 1, an A / D converter 2, a delay circuit 3, a subtractor 4, and a D / A.
It supplies a necessary clock signal to the converter 5 and the like. The clock signal includes a basic clock signal supplied to the CCD element 1, and the basic clock signal includes the A / D converter 2, the delay circuit 3, the subtracter 4 and the D / D converter.
It is also supplied to the A converter 5.

The A / D converter 2 receives the analog output signal from the CCD element 1 and converts it into a digital signal at the cycle of the basic clock signal. The delay circuit 3 digitally delays the output signal of the A / D converter 2 by one cycle of the basic clock using, for example, a shift register, and supplies it to one input of the subtractor 4. The subtractor 4 is a digital subtractor, receives the signal supplied from the delay circuit 3 and the signal before delay output from the A / D converter 2, and subtracts the both. The D / A converter 5 converts the output of the subtractor 4 into an analog signal. This analog signal is held in the hold circuit 6 until the next output of the D / A converter 5 is supplied. The held analog signal is supplied to the outside as a video signal output.

The operation of the circuit of FIG. 1 will be described in more detail with reference to FIG. FIG. 2 shows signal waveforms of the respective parts a to g of the circuit of FIG.

The clock generator 7 internally generates a basic clock signal for driving the CCD element 1, and supplies this basic clock signal a to each part of the digital signal processing circuit surrounded by a dotted line in FIG. The clock generator 7 also generates each drive pulse necessary for driving the CCD element 1 based on this basic clock signal and supplies it to the CCD element 1.
The drive pulse has a cycle three times as long as the basic clock pulse a, and also includes a control pulse having timings corresponding to the switching period, the feedthrough period, and the signal component period of the CCD element 1.

The analog output signal output from the CCD element 1 is a signal as schematically shown in FIG. 2B, has a period three times as long as the basic clock signal a of the CCD element 1, and is switched. Period t1, feedthrough period t
2. The signal has a signal component period t3, and its schematic waveform is shown in FIG. The output signal b of such a CCD element 1 is analog-digital converted in the A / D converter 2 at the cycle of the basic clock signal a to obtain a digital signal c. Since the A / D converter 2 performs A / D conversion in the cycle of the basic clock a, the output signal b of the CCD element 1 is in the switching level period t1, the signal in the feedthrough period t2, and the video signal in the signal component period t3. The level signals are sequentially output for each cycle of the basic clock signal a.

Such a digital signal c is delayed by the delay circuit 3 for one cycle of the basic clock signal a, and the signal d is obtained.
And is supplied to one input of the subtractor 4. The delay circuit 3 is a circuit that digitally delays a signal by using, for example, a shift register, a flip-flop, or the like. The signal c is directly input from the A / D converter 2 to the other input of the subtractor 4. The subtracter 4 subtracts the signal d from the signal c with respect to these input signals to generate an output signal e.

As described above, according to the configuration of FIG. 1, the output of the subtractor 4 is the signal obtained by subtracting the signal level of the preceding feedthrough period from the signal of the signal component period of the output signal of the CCD element 1. This is the desired video signal level.

It should be noted that this subtraction operation of the digital subtractor 4 is expediently configured such that the subtraction operation is performed only during a period corresponding to the signal component period of the signal c. In order to perform the subtraction operation only in such a specific period, for example, a gate circuit is provided for the input signal to the subtractor 4, and the gate circuit is controlled to open for a period corresponding to the signal component period of the CCD element 1. Can be done. As the control pulse for controlling these gate circuits, for example, a clock signal that becomes high level only during the signal component period generated in the clock generator 7 can be used.

Alternatively, since the subtractor 4 is caused to perform the subtraction operation only during the signal component period, the power supply to the subtractor may be turned on only during the signal component period, or a gate circuit is provided at the output of the subtractor 4. The gate circuit may be configured to open only during the signal component period and output the signal of the subtraction result.

The output signal e of the subtractor 4 is input to the D / A converter 5 and converted into an analog signal f. This analog signal f is input to the hold circuit 6 and held until the next analog signal f is input, and a video signal output g is obtained.

In the above description, the subtractor 4 is the CCD element 1
The signal indicating the subtraction result is output only during the period corresponding to the signal component period of the above. However, the subtractor 4 is configured to always perform the subtraction operation, and the D / A converter 5 outputs the C signal.
The input signal may be sampled and converted into an analog signal for each period corresponding to the signal component period of the CD element. Further, the D / A converter 5 may have the function of the hold circuit 6 as well.

[0030]

As described above, according to the present invention, the CCD
The analog output signal from the element is immediately A / D converted at the cycle of the basic clock signal for the CCD element to be converted into a digital signal, and the noise component suppressing operation of the CCD element is performed by digital processing. Therefore, after the A / D conversion of the output signal from the CCD element, the signal processing can be performed digitally uniformly at the basic clock cycle. For this reason,
It is possible to eliminate instability factors including a timing pulse and a level pulse such as a clamp pulse and a sampling pulse of a processing circuit that performs a noise suppressing operation such as conventional correlated double sampling. This completely eliminates the influence of manufacturing instability factors such as variations in elements, fluctuations in parameters due to changes in temperature and other environmental conditions, and changes in capacitance due to wiring processing of electric circuits. An extremely stable and uniform signal processing circuit can be realized. Further, the adjustment of the signal processing circuit can be easily performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an output signal processing circuit of a CCD element as an embodiment of the present invention.

FIG. 2 is an explanatory timing chart showing a signal flow of each part of the circuit of FIG.

FIG. 3 is a block diagram showing a schematic configuration of an output signal processing circuit of a conventional CCD device.

FIG. 4 is a schematic waveform diagram for explaining the operation of the circuit of FIG.

[Explanation of Codes] 1 CCD element 2 A / D converter 3 Digital delay circuit 4 Digital subtractor 5 D / A converter 6 Hold circuit 7 Clock generator 10 CCD element 11 Clamp circuit 12 Sample hold circuit

Claims (4)

[Claims] 1. An A / D converter for converting an analog output signal from a CCD element into a digital signal at a cycle of a basic clock signal of the CCD element, and the digital signal obtained by A / D conversion as the basic clock. And a digital subtractor for performing a subtraction between the output of the delay circuit and the original digital signal before the delay, the digital subtractor in the signal component period of the CCD element. An output signal processing circuit for a CCD device, characterized in that a processed signal output is obtained from the output of. 2. The digital subtractor performs digital subtraction and outputs subtraction data for each period corresponding to the signal component period of the CCD element.
An output signal processing circuit of the CCD device described in 1. 3. A D / A converter that converts the output of the digital subtractor into an analog signal and outputs the analog signal, and a hold circuit that holds the output of the D / A converter until the output of the next D / A converter. The output signal processing circuit for a CCD device according to claim 1, further comprising: 4. The CCD according to claim 1, wherein the D / A converter performs D / A conversion by sampling and holding an input signal in each period corresponding to a signal component period of a CCD element. Output signal processing circuit of the device.