JP3175377B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to a method for canceling a DC offset of an image signal input from an image sensor.

[0002]

2. Description of the Related Art Conventionally, in an electronic copying machine, an image scanner, or the like, an image signal input from an image sensor such as a CCD includes a DC offset that differs depending on each image sensor. It also fluctuates over time. There are the following methods for canceling the DC offset.

Japanese Patent Application Laid-Open No. 57-80869 or Japanese Patent Application Laid-Open No. 60-76876 discloses a system in which a DC component is cut using a capacitor and the DC level is fixed to a reference value by a clamp circuit. I have. Japanese Patent Laid-Open No. 60-
Japanese Patent No. 28183 discloses a method of canceling a DC offset by sampling and holding an offset level and subtracting the signal from an input signal.

[0004]

In the above-described conventional offset canceling system, the former clamping system has an error in the value to be clamped due to the noise included in the image signal. Since it is necessary to use an element having a high speed and good switching characteristics, there is a problem in component selection and cost.

In the latter sample-hold method,
There has been a problem that it is difficult to match the sample and hold timing to perform accurate level detection.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to provide an image processing apparatus capable of stably and accurately canceling a DC offset.

[0007]

According to the present invention, there is provided an image processing apparatus for processing an image signal output from an image sensor, comprising: a differential amplifier for inputting the image signal to one input terminal;
A / D conversion means for A / D converting the output signal of the differential amplifier, and D / D conversion based on output data of the A / D conversion means.
Correction value setting means for setting a correction value for canceling the C offset; and D / A conversion means for D / A converting the correction value and inputting the D / A value to the other input terminal of the differential amplifier. Features.

[0008]

With such means, control is performed using digital data, so that stable and accurate DC offset cancellation is possible.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing one example of an offset cancel circuit of an image processing apparatus to which the present invention is applied. In the differential amplifier 1, an image signal output from an image sensor such as a CCD is input to a minus input terminal.
The output of the D / A converter 5 is connected to the plus input terminal, and the difference voltage between the two inputs is output.

The A / D converter 2 samples and holds the output voltage of the differential amplifier 1 and performs A / D conversion to, for example, 8 bits. This output data is taken into a memory or the like, subjected to signal processing, or output via a correction circuit (not shown) at a later stage according to the application. The data holding circuit 3 fetches and holds the output data of the A / D converter 2 in the non-signal section of the image signal.

The correction value calculation circuit 4 calculates a correction value for canceling the DC offset based on the data from the data holding circuit 3 by calculation. The D / A converter 5 D / A converts the output data (for example, 8 bits) of the correction value calculation circuit 4 and outputs the data to the plus terminal of the differential amplifier 1. 6 is D
This is a resistor for generating the reference voltage Vref of the / A converter 5.

Next, the operation will be described. FIG. 2 (a)
2 shows a signal waveform at a point a in FIG. Normal CCD
The image sensor reads one line of a document on a platen such as an electronic copier in the horizontal direction and outputs it as a serial signal. FIG. 2A illustrates signal waveforms for one line before (left) and after (right) cancellation.
In the figure, on both sides of the read image signal section, there is a non-signal section which is a section of a signal output from the sensor in a portion where light is not detected. The level V1 of this portion corresponds to the DC offset.

First, before canceling, the correction value Da set in the D / A converter 5 is all 1 (25 in case of 8 bits).
5), that is, the maximum output voltage (VaH) of the D / A converter is set. This is because even if the input image signal takes the expected maximum voltage value, the output of the differential amplifier 1 is negative (A / D
This is to prevent the input voltage from falling below the allowable input voltage range of the converter. Therefore, the maximum output voltage of the D / A converter 5 needs to be higher than the expected input maximum voltage.

FIG. 2B shows the signal waveform at point b in FIG. The voltage V2 at point b is V2 = (Va-V1). Here, Va is the output voltage of the D / A converter 5.
Also, since the image signal input is connected to the minus terminal,
The waveform is inverted upside down. The signal at point b is A / D
The data is always sampled by the converter 2 and A / D converted.

The data holding circuit 3 latches the output D2 of the A / D converter in synchronization with the center of the non-signal section of the input signal. This timing signal is supplied from an image sensor control circuit (not shown). In the correction value calculation circuit 3, data corresponding to a voltage to be output by the D / A converter 5 in order to obtain a waveform as shown in the right side of FIG. 2B is obtained by the following calculation.

First, in order to make V2 in FIG. 2B zero, Va = V1. Therefore, in the correction value calculation circuit 3, the data Da corresponding to the voltage V1 should be obtained from the output D2 of the data holding circuit 3 so as to satisfy the above equation. Va is as follows.

Va = V1 = VaH-V2.

In the above equation, Va is Va = VaH
× Da / 255, V2, V2 = ViM × D2 / 255
It can be expressed as. Here, ViM is an input voltage at which the A / D converter outputs all 1 (255). Therefore, the above equation is as follows.

VaH × Da / 255 = VaH−ViM × D2 / 255
.

∴Da = 255− (ViM / VaH) D2 (Equation 1).

Therefore, for example, if VaH is twice ViM, then Da can be obtained by subtracting one half (1 bit shift) of D2 from 255. In general, the operation as in the above equation 1 can be executed by using a multiplier and an adder (subtractor). The circuit as described above enables stable and accurate DC offset cancellation.

Next, a second embodiment will be described. FIG. 3 is a block diagram showing a second embodiment of the offset cancel circuit. 3, the same parts as those in FIG. 1 are given the same numbers as in FIG. The level conversion circuit 7 multiplies the input voltage by (ViM / VaH). This (ViM
When the value of (/ VaH) is larger than 1, an amplifier is required. However, if the value is set to a value smaller than 1, the level conversion circuit 7 may be an attenuator using a simple resistor.

The switch SW is controlled by a control circuit (not shown). When a DC offset is obtained, the output of the level conversion circuit 7 is selected, and thereafter, the output of the differential amplifier 1 is selected. The data holding circuit 8 latches the output D2 of the A / D converter in synchronization with the center of the non-signal section of the input signal. This timing signal is supplied from an image sensor control circuit (not shown). The latched data is simply inverted and output to the D / A converter 5.

Next, the operation will be described. FIG. 4 is a waveform diagram showing a signal waveform at point d in FIG. As shown in the figure, the voltage V2 at the point b is level-converted and the A / D converter 2
Is input to As a result of performing such level conversion, A
The D / D-converted data D2 'is D2' = (ViM / VaH) D2 as compared with the value of D2 in the first embodiment. Therefore, Equation 1 is as follows.

Da = 255-D2 '(Equation 2).

The above operation is to obtain the complement of the 8-bit data of D2 ', and can be easily obtained by inverting 0 and 1. Therefore, as Da, the data holding circuit 8
Is inverted and output. By using the level conversion circuit in this manner, the calculation of the correction value becomes unnecessary, and the circuit configuration is simplified.

Next, a third embodiment will be described. FIG. 5 is a block diagram showing a third embodiment of the offset cancel circuit. 5, parts similar to those in FIG. 1 are given the same numbers as in FIG. The low-pass filter 9 removes noise components from the output signal of the differential amplifier 1. The switch SW is controlled by a control circuit (not shown).
When obtaining the offset, the output of the low-pass filter 9 is selected, and then the output of the differential amplifier 1 is selected. The following is the same as the first embodiment.

FIG. 6A shows the signal waveform at the point b in FIG. 5, and shows the time axis further enlarged than FIG. 2B.
As shown in the figure, noise due to the driving clock of the CCD image sensor is superimposed on the signal. If this is sampled as it is, an error due to noise occurs. However, the noise component is removed from the signal that has passed through the low-pass filter as shown in FIG. 6B, and the DC offset value can be sampled accurately. FIG. 6C shows A /
This is a sampling pulse input to the D converter 2.

Although the three embodiments have been described above, as another modified example, the output of the A / D converter 2 is taken into the CPU,
It is also possible to calculate a correction value and set it in the D / A converter 5.

[0030]

As described above, according to the present invention, since control is performed using digital data, stable and accurate DC offset can be canceled, and image processing which can be corrected by one control can be performed. There is an effect that a device can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of an offset cancel circuit.

FIG. 2 is a waveform chart showing signal waveforms at respective points in FIG.

FIG. 3 is a block diagram of a second embodiment of the offset cancel circuit.

FIG. 4 is a waveform chart showing a signal waveform at a point d in FIG. 3;

FIG. 5 is a block diagram of a third embodiment of the offset cancel circuit.

6 is a waveform chart showing a signal waveform at each point in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Differential amplifier, 2 ... A / D converter, 3 ... Data holding circuit, 4 ... Correction value calculation circuit, 5 ... D / A conversion circuit, 6 ... Resistor, 7 ... Level conversion circuit, 8 ... Data holding Circuit, 9 ...
Low-pass filter

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Koji Yorimoto 3-7-1, Fuuchi, Iwatsuki-shi, Saitama Prefecture Inside Xerox Corporation (72) Inventor Atsushi Takahashi 3-7-1, Fuuchi, Iwatsuki-shi, Saitama Fuji Inside Xerox Corporation (72) Inventor Yasuo Komatsu 3-7-1, Funai, Iwatsuki City, Saitama Prefecture Inside Fuji Xerox Co., Ltd. (72) Makoto Watanabe 3-7-1, Funai, Iwatsuki City, Saitama Prefecture Inside Fuji Xerox Co., Ltd. (56) reference Patent flat 4-113775 (JP, a) JP Akira 63-272169 (JP, a) JP flat 4-167668 (JP, a) (58 ) investigated the field (Int.Cl. ⁷ , DB name) H04N 1/407

Claims (1)

(57) [Claims] 1. An image processing apparatus for processing an image signal output from an image sensor, comprising: a differential amplifier for inputting the image signal to one input terminal; and an A / D converter for A / D converting an output signal of the differential amplifier. / D conversion means, correction value setting means for setting a correction value for canceling a DC offset based on output data of the A / D conversion means, D / A conversion of the correction value, and conversion of the differential amplifier. D / A conversion means for inputting to the other input terminal , wherein the differential amplifier and the
Between the A / D conversion means and the A / D conversion means;
/ A conversion means according to the level ratio per unit step
An image processing apparatus comprising level conversion means .