JPH06217139A - Image processor - Google Patents

Abstract

PURPOSE:To stably and exactly cancel DC offset by performing control while using digital data. CONSTITUTION:A CCD image sensor laterally reads one line of an original on a copying machine platen and outputs it as a serial signal. There are non- signal blocks on both sides of this image block, and this level V1 is correspondent to the DC offset. Before canceling, a set corrected value Da of a D/A converter 5 is set at a maximum output voltage VaH larger than the estimated maximum input voltage of the converter 5. Therefore, a voltage V2 at a point (b) becomes difference between the output voltage of the converter 5 and the voltage V1 and this is sampled and converted by an A/D converter 2. A data holding circuit 3 holds an output D2 synchronously with the center of the non- signal block of an input signal. A corrected value arithmetic circuit 4 calculates data corresponding to the output voltage of the converter 5 as an output, namely, calculates data Da corresponding to the voltage V1 from the output D2 of the circuit 3. Thus, the DC offset can be stably and exactly canceled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to a method for canceling a DC offset of an image signal input from an image sensor.

[0002]

2. Description of the Related Art Conventionally, in an electronic copying machine, an image scanner or the like, an image signal input from an image sensor such as a CCD includes a DC offset which differs depending on each image sensor. It also changes with age. The method for canceling the DC offset is as follows.

Japanese Unexamined Patent Publication No. 57-80869 or Japanese Unexamined Patent Publication No. 60-76876 discloses a method of cutting a direct current component by using a capacitor and fixing a DC level to a reference value by a clamp circuit. There is. In addition, JP-A-60-
Japanese Patent No. 28183 discloses a method of canceling a DC offset by sample-holding an offset level and subtracting the signal from the input signal.

[0004]

In the conventional offset cancel method as described above, the former clamp method causes an error in the clamp value because the image signal contains noise, and the clamp value is also clamped. As the element, it is necessary to use a high-speed element having a good switching characteristic, which causes a problem in component selection and cost.

In the latter sample-hold method,
There has been a problem that it is difficult to match the timing of sample and hold in order to perform accurate level detection.

An object of the present invention is to solve the above-mentioned problems of the prior art and to obtain an image processing apparatus capable of stably and accurately canceling a DC offset.

[0007]

According to the present invention, in an image processing apparatus for processing an image signal output from an image sensor, a differential amplifier for inputting the image signal to one input terminal,
A / D conversion means for A / D converting the output signal of the differential amplifier, and D based on the output data of the A / D conversion means
A correction value setting means for setting a correction value for canceling the C offset; and a D / A conversion means for D / A converting the correction value and inputting it to the other input terminal of the differential amplifier. Characterize.

[0008]

By such means, control is performed using digital data, so that stable and accurate DC offset cancellation is possible.

[0009]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an example of an offset cancel circuit of an image processing apparatus to which the present invention is applied. An image signal output from an image sensor such as a CCD is input to the negative input terminal of the differential amplifier 1.
Further, the output of the D / A converter 5 is connected to the positive input terminal, and the difference voltage between the two inputs is output.

The A / D converter 2 samples and holds the output voltage of the differential amplifier 1 and performs A / D conversion into, for example, 8 bits. This output data is taken into a memory or the like, processed by a signal, or output via a correction circuit or the like in the subsequent stage (not shown) according to the purpose. The data holding circuit 3 takes in and holds the output data of the A / D converter 2 in the no signal section of the image signal.

The correction value calculation circuit 4 calculates a correction value for canceling the DC offset based on the data from the data holding circuit 3. The D / A converter 5 D / A converts the output data (for example, 8 bits) of the correction value calculation circuit 4 and outputs it to the plus terminal of the differential amplifier 1. 6 is D
A resistor for generating the reference voltage Vref of the A / A converter 5.

Next, the operation will be described. Figure 2 (a) shows
The signal waveform in the point a of FIG. 1 is shown. Normal CCD
The image sensor laterally reads one line of a document on a platen of an electronic copying machine or the like and outputs it as a serial signal. FIG. 2A shows signal waveforms for one line before cancellation (left side) and after cancellation (right side).
In the figure, on both sides of the read image signal section, there is a no-signal section that is a section of the signal output from the sensor in the portion that does not detect light. The level V1 of this portion corresponds to the DC offset.

First, before cancellation, the correction value Da set in the D / A converter 5 is all 1 (25 in the case of 8 bits).
5), that is, the maximum output voltage (VaH) of the D / A converter is set. This is because even if the input image signal has the expected maximum voltage value, the output of the differential amplifier 1 is negative (A / D
This is to prevent it from falling below the allowable input voltage range of the converter). Therefore, the maximum output voltage of the D / A converter 5 needs to be higher than the expected maximum input voltage.

FIG. 2B shows the signal waveform at point b in FIG. The voltage V2 at the point b is V2 = (Va-V1). Here, Va is the output voltage of the D / A converter 5.
Also, since the image signal input is connected to the negative terminal,
The waveform is upside down. Signal at point b is A / D
The converter 2 constantly samples and performs A / D conversion.

The data holding circuit 3 latches the output D2 of the A / D converter in synchronization with the center of the no-signal section of the input signal. This timing signal is supplied from an image sensor control circuit (not shown). The correction value calculation circuit 3 obtains data corresponding to the voltage to be output by the D / A converter 5 in order to obtain the waveform as shown on the right side of FIG.

First, in order to set V2 in FIG. 2 (b) to 0, Va = V1 may be set. Therefore, in the correction value calculation circuit 3, it is only necessary to obtain the data Da corresponding to the voltage V1 from the output D2 of the data holding circuit 3 so as to satisfy the relation of the above equation. Va is as follows.

Va = V1 = VaH-V2.

In the above equation, Va is Va = VaH
× Da / 255, V2 is V2 = ViM × D2 / 255
It can be expressed as. ViM is an input voltage at which the A / D converter outputs all 1 (255). Therefore, the above equation becomes as follows.

VaH × Da / 255 = VaH−ViM × D2 / 255
.

∴Da = 255- (ViM / VaH) D2 (Equation 1).

Therefore, for example, if VaH is twice as large as ViM, Da can be obtained by subtracting 1/2 of D2 (shifted by 1 bit) from 255. In general, the calculation as in the above formula 1 can be executed by using a multiplier and an adder (subtractor). The circuit as described above enables stable and accurate DC offset cancellation.

Next, the second embodiment will be described. FIG. 3 is a block diagram showing a second embodiment of the offset cancel circuit. In FIG. 3, the same parts as in FIG. 1 are given the same numbers as in FIG. The level conversion circuit 7 multiplies the input voltage by (ViM / VaH). This (ViM
If the value of / VaH) is larger than 1, an amplifier is required, but if it is set to a value smaller than 1, the level conversion circuit 7 may be an attenuator using a simple resistor.

The switch SW is controlled by a control circuit (not shown). When the DC offset is obtained, the output of the level conversion circuit 7 is selected, and then the output of the differential amplifier 1 is selected. The data holding circuit 8 latches the output D2 of the A / D converter in synchronization with the center of the no-signal section of the input signal. This timing signal is supplied from an image sensor control circuit (not shown). The latched data is simply inverted and output to the D / A converter 5.

Next, the operation will be described. FIG. 4 is a waveform diagram showing the signal waveform at point d in FIG. As shown in the figure, the voltage V2 at the point b is level-converted and the A / D converter 2
Entered in. As a result of performing such level conversion, A
The D / D-converted data D2 'is D2' = (ViM / VaH) D2 as compared with the value of D2 in the first embodiment. Therefore, the equation 1 is as follows.

Da = 255-D2 '(Equation 2).

The above operation is to obtain the complement of 8-bit data of D2 ', which can be easily obtained by inverting 0 and 1. Therefore, Da is the data holding circuit 8
It is only necessary to invert the data and output. By using the level conversion circuit in this way, the calculation of the correction value becomes unnecessary, and the circuit configuration becomes simple.

Next, a third embodiment will be described. FIG. 5 is a block diagram showing a third embodiment of the offset cancel circuit. 5, the same parts as in FIG. 1 are assigned the same numbers as in FIG. The low pass filter 9 removes a noise component from the output signal of the differential amplifier 1. The switch SW is controlled by a control circuit (not shown), and DC
When obtaining the offset, the output of the low-pass filter 9 is selected, and then the output of the differential amplifier 1 is selected. The following is the same as the first embodiment.

FIG. 6 (a) shows the signal waveform at point b in FIG. 5, and the time axis is further expanded from FIG. 2 (b).
As shown in the figure, the signal carries noise due to the driving clock of the CCD image sensor. If this is sampled as it is, an error occurs due to noise, but the noise component is removed from the signal that has passed through the low-pass filter as shown in FIG. 6B, and the DC offset value can be accurately sampled. Note that FIG. 6C shows A /
The sampling pulse is input to the D converter 2.

Although the three embodiments have been described above, as another modification, the output of the A / D converter 2 is fetched into the CPU,
It is also possible to calculate a correction value and set it in the D / A converter 5.

[0030]

As described above, according to the present invention, since the control is performed by using the digital data, it is possible to cancel the DC offset in a stable and accurate manner, and the image processing which can be corrected by one-time control. The effect is that the device can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of an offset cancel circuit.

FIG. 2 is a waveform diagram showing a signal waveform at each point in FIG.

FIG. 3 is a block diagram of a second embodiment of an offset cancel circuit.

FIG. 4 is a waveform diagram showing a signal waveform at point d in FIG.

FIG. 5 is a block diagram of a third embodiment of an offset cancel circuit.

6 is a waveform diagram showing a signal waveform at each point in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Differential amplifier, 2 ... A / D converter, 3 ... Data holding circuit, 4 ... Correction value calculation circuit, 5 ... D / A conversion circuit, 6 ... Resistor, 7 ... Level conversion circuit, 8 ... Data holding Circuit, 9 ...
Low pass filter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Yorimoto 3-7-1, Fuchu, Iwatsuki City, Saitama Prefecture Fuji Zerox Co., Ltd. (72) Inventor Atsushi Takahashi 3-7-1, Fuchu, Iwatsuki City, Saitama Prefecture Fuji Zelocks Co., Ltd. (72) Inventor Yasuo Komatsu 3-7-1 Fuchu, Iwatsuki City, Saitama Prefecture Fuji-Zerox Co., Ltd. (72) Makoto Watanabe 3-7-1, Fuchu, Iwatsuki City, Saitama Prefecture Within Rocks Co., Ltd.

Claims (3)

[Claims] 1. An image processing apparatus for processing an image signal output from an image sensor, wherein: a differential amplifier for inputting the image signal to one input terminal; and A for A / D converting the output signal of the differential amplifier. A correction value setting means for setting a correction value for canceling the DC offset based on the output data of the A / D conversion means and the A / D conversion means, and D / A conversion of the correction value to convert the correction value of the differential amplifier. An image processing apparatus comprising: a D / A conversion means for inputting to the other input terminal. 2. A level conversion means according to a level ratio per unit step of the A / D conversion means and the D / A conversion means is provided between the differential amplifier and the A / D conversion means. The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus. 3. The image processing apparatus according to claim 1, further comprising low-pass filter means provided between the differential amplifier and the A / D conversion means.