JP2001358992A - Correlated double sampling circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a correlated double sampling circuit that solves the problem of settling time after a sample-and-hold circuit and excludes fluctuations in an output level due to a droop characteristic of the sample-and-hold circuit at a variable rate. SOLUTION: This correlated double sampling circuit is provided with a 1st analog/digital converter that receives an output of a CCD image sensor and samples the output for a field-through period of the sensor, a 2nd analog/ digital converter that receives the output of the CCD image sensor and samples the output for a signal output period of the sensor, and a subtractor that subtracts outputs of the 1st and 2nd analog/digital converters.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correlated double sampling (CDS) circuit used for processing an output signal of a CCD image sensor.
In particular, the present invention relates to a circuit for obtaining the output as digital data by an AD converter.

[0002]

2. Description of the Related Art FIG. 5 shows a signal output processing circuit of a CCD image sensor using a correlated double sampling circuit using a sample and hold circuit for an analog signal. FIG. 6 is a waveform diagram of each section for explaining the operation of correlated double sampling. It is.

Reference numeral 1 denotes a CCD image sensor, and Ec denotes a CCD image sensor signal output generated at a predetermined cycle.
This output signal is, as shown in FIG.
It is composed of three periods of a reset period, a feedthrough, and a signal output, and the difference between the feedthrough level and the signal output level is a CCD signal output in one pixel section.

A general configuration of a circuit for extracting a difference between a feedthrough level and a signal output level is a sample and hold circuit shown in FIG. 5 and a correlated double sampling circuit using a differential amplifier. The signal output Ec is sampled and held by the sample and hold circuit 4 via the buffer circuits 2 and 3 in synchronization with the clock CL2 (FIG. 6 (c)) generated during the signal output period. Will be retained.

Similarly, the signal output Ec is sampled and held by a sample and hold circuit 6 via a buffer circuit 5 in synchronization with a clock CL1 (FIG. 6 (b)) generated during a feed-through period. The signal is sampled and held by the sample and hold circuit 8 via the circuit 7 in synchronization with the clock CL2 generated during the signal output period, and is held as Ecf until the next cycle of the clock CL2.

Reference numeral 9 denotes a differential amplifier which calculates a difference between Ecc and Ecf, and outputs a CCD signal output Ed (FIG. 6D). Since Ecc and Ecf are updated in synchronization with the clock CL2, Ed also changes stepwise in synchronization with the clock CL2. An AD converter 10 converts the output Ed of the differential amplifier 9 into a digital signal D.

[0007]

In such a correlated double sampling circuit based on analog signal processing, if the common-mode rejection ratio of the differential amplifier 9 is low, the DC fluctuation of the input voltage is converted into an output level error. I will. In particular, the higher the speed of the amplifier, the more difficult it is to increase the common mode signal rejection ratio.

A CCD driven by a high-speed clock
In the image sensor, settling characteristics after the sample and hold circuit become a problem, and it is difficult to cope with higher-speed operation.

Further, when the clock rate is made variable, if the timing between the clocks of the sample and hold circuits and the timing of the clock of the AD converter and the clock of the sample and hold circuit change, the output level will be affected by the droop characteristic of the sample and hold circuit. There is a problem that changes.

In the configuration using three sample and hold circuits as shown in FIG. 5, the clock CL1 and the signal output level are sampled due to the restriction of the settling time of the first stage sample and hold output for sampling the feedthrough level. It is difficult to reduce the timing difference between the clocks CL2, which hinders an increase in the operation rate.

[0011]

Means for Solving the Problems In order to achieve the above object, a feature of the present invention described in claim 1 of the present invention is that
A first AD converter that inputs an output of a CD image sensor and samples a field through period of the sensor;
A second AD converter that inputs an output of the CCD image sensor and samples a signal output period of the sensor, and a subtractor that subtracts outputs of the first AD converter and the second AD converter are provided.

The present invention is characterized in that a first AD converter for inputting an output of a CCD image sensor and sampling a field through period of the sensor, and the CCD.
A second AD converter that receives an output of an image sensor and samples a signal output period of the sensor;
DA for supplying a reference voltage for changing a gain of at least one of the converter and the second AD converter
A converter and a subtracter for subtracting the outputs of the first and second AD converters are provided.

According to a third aspect of the present invention, there is provided a first AD converter for inputting an output of a CCD image sensor and sampling a field through period of the sensor;
A second AD converter that receives an output of an image sensor and samples a signal output period of the sensor;
D for supplying a reference voltage to change the input range of at least one of the converter and the second AD converter
An A converter and a subtractor for subtracting the outputs of the first and second AD converters are provided.

According to a fourth aspect of the present invention, there is provided a first AD converter for inputting an output of a CCD image sensor and sampling a field through period of the sensor;
A second AD converter that inputs an output of the image sensor and samples a signal output period of the sensor, a subtractor that subtracts outputs of the first and second AD converters, and at least one of the first AD converter and the second AD converter; And a multiplier provided between the subtractor.

According to a fifth aspect of the present invention, there is provided a first AD converter for inputting an output of a CCD image sensor and sampling a field through period of the sensor;
A second AD converter that inputs an output of the D image sensor and samples a signal output period of the sensor; a subtractor that subtracts outputs of the first and second AD converters; and at least one of the first AD converter and the second AD converter And an adder provided between the subtractor.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the basic configuration of a correlated double sampling circuit according to the present invention, and FIG. 2 is a waveform diagram of each section for explaining the operation.

In FIG. 1, reference numeral 11 denotes a first AD converter which inputs a CCD image sensor output Ec, samples Ec at the rising edge of a clock CL1 rising in synchronization with a feedthrough period, outputs data, and updates the previous data output. I do.

Reference numeral 12 denotes a second AD converter for inputting the CCD image sensor output Ec, which samples Ec at the rising edge of the clock CL2 which rises in synchronization with the signal output period, outputs data, and updates the previous data output. There is no problem even if a certain pipeline delay exists in the data output of the first and second AD converters.

Reference numeral 13 denotes a register for adjusting the timing of the data output of the first AD converter 11 and the data output of the second AD converter 12. The first register 13 is provided at the rising edge of the clock CL2 which rises in synchronization with the signal output period.
The data output of the D converter 11 is latched.

Reference numeral 14 denotes a digital subtractor, which is a 2A
The data output of the first AD converter 11 is subtracted from the data output of the D converter 12, and digital data D corresponding to the signal output of the CCD is output.

2A shows the waveform of the output signal Ec of the CCD image sensor, and FIG.
As in the case of (1), there are three periods: a reset period, a feedthrough, and a signal output.

FIG. 3B shows the waveform of the clock CL1 supplied to the first AD converter 11, which is supplied at the timing of sampling the level in the feedthrough period of FIG. (C) is the waveform of the clock CL2 supplied to the second AD converter 12, and is supplied at the timing of sampling the level during the signal output period of (a).

FIG. 3D shows output data of the first AD converter 11.
The result of the D conversion is output in synchronization with the rise of the clock CL1 in (b), and the previous output data is updated.

(E) is output data of the second AD converter 12. The result of AD conversion of the input signal level during the signal output period is output in synchronization with the rise of the clock CL2 in (c), and the previous output data is updated. Is done.

(F) is the output data of the register 13, and the data of the output data (d) of the first AD converter 11 is latched in synchronization with the rise of the clock CL2 in (c), and the previous output data is updated. .

(G) is a waveform of the digital data output D of the digital subtractor 14, and the first AD converter 1
1, the data output (e) of the second AD converter 12 and the data output (f) of the second AD converter 12 are input, and (f)-(e) is calculated.
The data is updated last time.

FIG. 3 shows an example of the configuration of a correlated double sampling circuit showing another embodiment of the present invention. The features of the second embodiment compared with the example of FIG. 1 are the first AD converter 11 and the second AD converter.
The point is that the D converter 12 has an external reference input.

Reference numeral 15 denotes a DA converter that supplies a reference voltage to the upper-level reference input REFT of the first AD converter 11, and 16 denotes a DA converter that similarly supplies a reference voltage to the lower-level reference input REFB of the first AD converter 11.

Reference numeral 17 denotes a DA converter for supplying a reference voltage to the upper-level reference input REFT of the second AD converter 12, and reference numeral 18 denotes a DA converter for supplying a reference voltage to the lower-level reference input REFB of the second AD converter 12.

By controlling the output values of these DA converters 15 to 18, it is possible to absorb the difference in gain and offset between the first AD converter 11 and the second AD converter 12. Further, by controlling the output values of the DA converters 15 to 18, the input ranges of the first AD converter 11 and the second AD converter 12 can be made variable.

FIG. 4 shows an example of the configuration of a correlated double sampling circuit showing still another embodiment of the present invention.
At least one of the outputs of the AD converter 12 and the subtractor 1
4 in that a multiplier for gain correction is provided.
Further, an adder for offset correction is provided between the multiplier and the subtractor as needed.

Reference numeral 19 denotes a register for holding gain correction data to be multiplied by output data of the register 13 for latching output data of the first AD converter 11, and reference numeral 20 denotes a first A converter.
A multiplier for multiplying output data of the D converter 11 by correction data of the register 19.

Reference numeral 21 denotes a register for holding offset correction data to be added to the output data of the multiplier 20, and reference numeral 22 denotes an adder for adding the correction data of the register 21 to the output data of the multiplier 20.

A register 23 holds gain correction data to be multiplied by the output data of the second AD converter 12, and a multiplier 24 multiplies the output data of the second AD converter 12 by the correction data of the register 23.

A register 25 holds offset correction data to be added to the output data of the multiplier 24, and an adder 26 adds the correction data of the register 25 to the output data of the multiplier 24.

With this configuration, even when an AD converter having no external reference input as shown in FIG. 3 is used, the first AD converter 11 and the second AD converter 12 are controlled by the set values of the registers 19, 21, 23, and 25.
It is possible to absorb the gain and offset differences between them.

In the embodiment of FIG. 4, the multiplier and the adder are of the first type.
Although provided for both the output data of the AD converter 11 and the output data of the second AD converter 12, a configuration of only one side may be used, and the adder may be omitted if there is no problem in the offset difference.

[0037]

As described above, according to the present invention, the problem of the settling time after the sample and hold circuit and the problem of the sample at the time of variable rate, which have been problems in the conventional correlated double sampling circuit. It is possible to eliminate a change in the output level due to the droop characteristic of the hold circuit.

Further, since the output delay time of the output data of the AD converter with respect to the input clock is shorter than the output settling time of the sample and hold circuit, the timing for sampling the field through level and the signal output are smaller than those of the conventional circuit. The time difference between the timings of sampling the levels can be further shortened, and the time for one pixel can be shortened.

Furthermore, by changing the reference voltage of the AD converter or providing a multiplier for performing gain correction on the output of the AD converter,
The problem of the common mode signal rejection ratio of the conventional differential amplifier can also be solved.

In addition, the offset difference can be absorbed by changing the reference voltage of the AD converter or by providing an adder for performing offset correction on the output of the AD converter.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a correlated double sampling circuit according to the present invention.

FIG. 2 is a waveform chart of each section for explaining the operation of the elements in FIG. 1;

FIG. 3 is a circuit configuration diagram showing another embodiment of the correlated double sampling circuit according to the present invention.

FIG. 4 is a circuit configuration diagram showing still another embodiment of the correlated double sampling circuit according to the present invention.

FIG. 5 is a general circuit configuration diagram of a conventional correlated double sampling circuit.

6 is a waveform chart of each part for explaining the operation of the element in FIG. 5;

[Explanation of symbols]

 Ec CCD image sensor output signal 11 First AD converter 12 Second AD converter 13 Register 14 Subtractor CL1 Feed-through synchronous clock CL2 Signal output synchronous clock D Subtractor output

Claims (5)

[Claims] 1. A first AD which receives an output of a CCD image sensor and samples a field through period of the sensor.
A correlated double sampling circuit comprising: a converter, a second AD converter that inputs an output of the CCD image sensor and samples a signal output period of the sensor, and a subtractor that subtracts outputs of the first AD converter and the second AD converter. . 2. A first AD which inputs an output of a CCD image sensor and samples a field through period of the sensor.
A converter, a second AD converter for inputting an output of the CCD image sensor and sampling a signal output period of the sensor, and the first AD converter or the second AD converter.
A DA converter for supplying a reference voltage for changing a gain of at least one of the converters,
A correlated double sampling circuit comprising: a subtracter for subtracting an output of an AD converter. 3. A first AD which inputs an output of a CCD image sensor and samples a field through period of the sensor.
A converter, a second AD converter for inputting an output of the CCD image sensor and sampling a signal output period of the sensor, and the first AD converter or the second AD converter.
A correlated double sampling circuit comprising: a D / A converter for supplying a reference voltage for changing at least one input range of the converter; and a subtracter for subtracting outputs of the first and second A / D converters. 4. A first AD which inputs an output of a CCD image sensor and samples a field through period of the sensor.
A converter, a second AD converter that inputs the output of the CCD image sensor and samples a signal output period of the sensor, a subtractor that subtracts the output of the first and second AD converters, and the first AD converter or the second AD converter. A correlated double sampling circuit comprising a multiplier provided between at least one of the converters and the subtractor. 5. A first AD which inputs an output of a CCD image sensor and samples a field through period of the sensor.
A converter, a second AD converter that inputs the output of the CCD image sensor and samples a signal output period of the sensor, a subtractor that subtracts the output of the first and second AD converters, and the first AD converter or the second AD converter. A correlated double sampling circuit comprising an adder provided between at least one of the converters and the subtractor.