KR100869855B1 - High-speed sampling structure for ccd image signal - Google Patents

Abstract

A high speed correlated double sampling structure of a CCD image signal is provided to remove uncertainty due to a process of a sampling clock and a change of voltage supply and temperature variation, thereby realizing high speed sampling. A clock correction unit(50) moves a level of a clock inputted from the outside and buffers. A clock correction unit outputs a clock having the same phase of the input by offsetting a delay time caused during the level movement or the buffering process by negative delay. A correlated double sampling unit(20) samples the reference signal and an analog image signal of a CCD image sensor by using a clock provided from the clock correction unit. And the correlated double sampling unit obtains the difference of two sampling signals. A variable gain unit amplifies a signal provided from the correlated double sampling unit.

Description

High-Speed Sampling Structure for CCD Image Signal

The present invention relates to a Correlated Double Sampling (CDS) technique applicable to an analog front end (AFE) chip for a CCD image sensor that receives an analog output signal of a CCD image sensor and converts it into a digital output. More particularly, the present invention relates to a high speed sampling structure of a CCD image signal capable of eliminating sampling errors caused by uncertainty caused by shaking of a sampling clock in the case of a high speed data input.

3 is a diagram illustrating one cycle of an output signal of a low frequency CCD image sensor.

Referring to FIG. 3, a clock A samples a pre-charge value corresponding to a reference signal, a clock B samples an analog image signal, and two consecutive samplings form a CCD image signal at a value corresponding to the difference. Correlation double sampling is performed.

Correlated double sampling removes noise by using a difference between the reference signal and an analog image signal, and is generally included in an analog front end chip in which a circuit for amplifying or attenuating an analog signal and converting it to digital is integrated on a single chip. Consists of.

Generally, the configuration of an analog front end circuit for sampling a signal input from a CCD image sensor will be described with reference to FIG. 1.

The analog front end circuit (100) comprises: clock converting means (10) for level converting, buffering and outputting a clock inputted from the outside; Correlated double sampling means (20) for sampling a reference signal and an analog image signal output from the CCD image sensor with a clock provided by the clock converting means (10) and obtaining a difference between the sampled reference signal and the analog image signal; Variable gain means (30) for amplifying the signal provided by the correlated double sampling means (20); And analog-to-digital converting means 40 for converting the signal provided from the variable gain means 30 into a digital data signal.

In order to sample the reference signal and the analog image signal output from the CCD image sensor in the analog front end circuit 100 configured as described above, a clock 1 for sampling the reference signal and a clock 2 for sampling the analog image are required. However, since the clock 2 is supplied outside the analog front end 100 chip, the clock converting means 10 converts the clock 1 and the clock 2 into clock A and clock B by level converting and buffering the clock 1 and the clock 2, respectively.

However, when leveling and buffering two input clocks 1 and 2 for correlated double sampling, as shown in Fig. 3, the output clock A and clock B have a constant delay time d. Is not constant with changes in process, supply voltage and temperature, resulting in uncertainty of sampling.

In fact, the waveforms of the clocks A and B outputted to the clocks 1 and 2 of the clock converting means 10 are delayed by d as compared to the input clocks 1 and 2 as shown in FIG. 4, and it can be confirmed that the clock waveform is uncertain. have.

Therefore, when the reference signal and the analog image signal value are sampled with the clock A and the clock B having such an uncertainty section in the sample and holder, the reference signal value and the analog image signal value are shaken, in particular, a high-speed CCD image signal. In this case, the delay of the sampling clock has a greater influence.

As shown in FIG. 5, in general, the high-speed CCD image signal changes the reference signal value and the analog image signal value faster than the low-speed CCD image signal of FIG. If the high-speed CCD image signal having such a characteristic is sampled with the clocks A and B, the reference signal value and the analog image signal value are shaken more than the low-speed CCD image signal.

Therefore, when sampling a low-speed CCD image signal using a conventional correlation sampling technique, this uncertainty interval does not have a significant effect on the accuracy of the sampling, but at high speeds, it causes a large influence on the correlation double sampled signal. There is a problem.

The present invention is to solve the problems of the prior art as described above, by offsetting the clock delay time d inevitably for the level shifting or buffering of the sampling clock, thereby eliminating the sampling error due to the time delay and the uncertainty interval of the sampling clock. Its purpose is to remove it.

In order to achieve the above object, the present invention provides a negative delay in clock delay time d generated during a process of level shifting or buffering sampling clocks 1 and 2 in the correlation double sampling of an output image of a high frequency CCD image sensor. It is characterized in that to implement to compensate for the clock correction means to compensate.

Preferably, the clock correction means includes a delay-locked loop that has a feedback loop therein and implements a negative delay to compensate for the delay time of the clock delay path.

Preferably, the clock correction means does not have an internal feedback loop, but an open loop clocking circuit capable of compensating the delay time of the clock delay path by implementing a negative delay time using an open loop. circuit).

As described above, according to the present invention, the phase of the output clocks (Clocks A and B) is made equal to the input clocks (Clocks 1 and 2) by the clock correction means, so that accurate sampling of high-speed CCD image signals of 15 MSPS or more is possible. There is an effect that accurate correlation double sampling can be performed.

The present invention is constructed as shown in FIG.

Hereinafter, the configuration of the present invention with reference to the drawings.

FIG. 6 is a diagram illustrating an analog front-end circuit according to the present invention, and FIG. 7 is a diagram schematically illustrating a fast correlation double sampling structure of a CCD image signal according to the present invention, and FIG. 8 is a clock correction apparatus of the present invention. Fig. 9 is a circuit diagram in which a delay lock loop is configured in the clock correction means of the present invention.

First, clock correction means 50 for level shifting or buffering a clock inputted from the outside, and offsetting the delay time generated in this process by implementing a negative delay to output a clock having the same phase as the input; Black level processing means (22) which receives the output of the following sample and hold means (21) during the black level search period of the CCD and obtains black level values of the reference signal and the image signal; The black level of each reference signal and the image signal provided by the black level processing means 22 is sampled according to the clock period of the clock correction means 50 to remove the black level from the reference signal and the image signal during the sampling period. Sample and hold means 21; Data synchronization and buffering means (23) for receiving a reference signal and an image signal from the sample and hold means (21) and outputting a difference between the two signals; Variable gain means 30 for amplifying the sampled signal and analog-to-digital converting means 40 for converting a signal provided from the variable gain means 30 into a digital data signal.

The clock correction means 50 further includes a delay locked loop 51 which implements a negative delay and cancels it to output a clock having the same phase as the input. For each of the two sampling clocks 1 and 2, The clock correction means 50 is configured.

In the high-speed correlation double sampling process of the CCD image signal of the present invention configured as described above, first, the clock correction means 50 converts and buffers the clocks 1 and 2 received from the outside, in this case, the delay locked loop. 51 compensates for the delay time of the clock delay path by implementing a negative delay in this process to compensate for the delay time.

As a result, the clocks 5 and 6 output from the clock correction means 50 have the same phase as the input clocks 1 and 2.

The clock 5 and the clock 6 output as described above are applied to the correlation double sampling means 20. The correlation double sampling means 20 obtains the black level values of the reference signal and the analog image signal input from the CCD image sensor. When the black level is removed from each reference signal and the analog image signal, and the difference between the two signal reference signals and the analog image signal from which the black level is removed is obtained and outputted to the variable gain means 30, the variable gain means 30 The amplified signal is amplified, and the amplified signal is converted into a digital data signal through an analog-digital converting means 40 and output.

Meanwhile, as shown in FIG. 9, the clock correction means 50 implements an open delay clock circuit 52, which is another circuit capable of compensating the delay time of the clock delay path by implementing a negative delay time. You can also get

1 is a view schematically showing a configuration for sampling a signal input from a conventional CCD image sensor

2 is a view schematically showing a clock path model of a conventional clock conversion means;

3 is a diagram showing one period of an output signal of a low frequency CCD image sensor;

FIG. 4 is a diagram showing waveforms of clock A and clock B outputted to clock 1 and clock 2 of the conventional clock converting means. FIG.

5 is a view showing the output waveform of a typical high frequency CCD image sensor

Figure 6 illustrates an analog front end circuit diagram in accordance with the present invention.

7 is a schematic diagram illustrating a fast correlation double sampling structure of a CCD image signal according to the present invention.

8 is a circuit diagram of a delay lock loop configured in the clock correction means of the present invention.

9 is a circuit diagram of a delay lock loop configured in the clock correction means of the present invention.

<Description of main parts of drawing>

100: analog front end circuit

10: clock conversion means 20: correlation double sampling means

21: sample and hold means 22: black level processing means

23: data synchronization and buffering means 30: variable gain means

40: analog digital conversion means 50: clock correction means

51: delay locked loop

52: open loop clocking circuit

Claims (3)

In the technique of performing the correlation double sampling of the reference signal and the image signal input to the analog front-end chip which converts the analog output signal of the CCD image sensor into a digital signal, respectively at different timings and different clocks, Clock correction means for level shifting or buffering a clock inputted from the outside, and offsetting a delay time generated in this process by implementing a negative delay to output a clock having the same phase as the input; Correlated double sampling means for sampling a reference signal of the CCD image sensor and an analog image signal with a clock provided by the clock correction means, and obtaining a difference between the two sampling signals; Variable gain means for amplifying the signal provided by the correlation double sampling means; And analog-to-digital conversion means for converting the signal provided from said variable gain means into a digital data signal. The method of claim 1, The clock correction means has a feedback loop therein, and implements a negative delay, so that the CCD image signal, characterized in that the delay lock loop (Delay-Locked Loop) to compensate for the delay time of the clock delay path Fast Correlated Double Sampling Structure The method of claim 1, The clock correction means does not have a feedback loop therein, but an open loop clocking circuit that compensates for the delay time of the clock delay path by implementing a negative delay time using an open loop. High-speed correlation double sampling structure of CCD image signal

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