JP2003274292A - Solid-state image pickup device and method of driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when various circuits are mixedly mounted on the same board as a solid-state image pickup element, a large current flows into the board of the solid-state image pickup device in synchronism with the rising or falling of an operational clock of each circuit, and a ground bounce phenomenon causes fluctuation of the voltage of the board. <P>SOLUTION: In the solid-stage image pickup device having a CDS circuit 12 and an A/D conversion circuit 13 mixedly mounted on the same board 15 as a solid-stage image pickup element 11, a relative phase relationship between the operational clock ϕ and the operational clocks ϕB and ϕC of the CDS circuit and A/D conversion circuit is suitably variably adjusted. Thereby sampling of the CDS circuit 12 and A/D conversion circuit 13 can be realized during such a period that the respective circuits are less influenced by clock noise generated by the operational clocks ϕA, ϕB and ϕC of the circuits. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and its driving method, and more particularly to a CDS circuit (Correlated Dome).
The present invention relates to a solid-state imaging device in which a uble Sampling Circuit (correlated double sampling circuit) and an analog / digital conversion circuit (hereinafter referred to as an A / D conversion circuit) are mixedly mounted on the same substrate as a solid-state imaging device, and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, CMOS image sensors and CCDs
Solid-state imaging devices represented by (Charge Coupled Device) image sensors have been attracting attention as image input devices for various electronic devices such as mobile terminals.

FIG. 5 shows an example of a system configuration of a solid-state image pickup device from a solid-state image pickup element to a digital image processing circuit.

In FIG. 5, incident light (image light) from a subject (not shown) is imaged on the image pickup surface of the solid-state image pickup device 102 by the lens 101. Solid-state image sensor 102
Photoelectrically converts incident light in pixel units and finally outputs it as an image signal. An image signal output from the solid-state image sensor 102 passes through a CDS circuit 103 and an A / D conversion circuit 104, and then a storage device 105 such as a field memory.
Then, in the digital image processing circuit 106, pixel interpolation, white balance, color correction, edge enhancement,
Various image processes such as image compression are performed.

From the viewpoint of downsizing and weight saving of mobile terminals, for example, mobile phones and PDAs (Personal Digital).
When a solid-state image pickup device is mounted as an image input device for a mobile terminal such as Assistants), a CDS circuit, an A / D conversion circuit, and even a digital image processing circuit are mixedly mounted on the same substrate as the solid-state image pickup element. In recent years, it has been particularly required to do so. If these circuits can be mixedly mounted on the same substrate (silicon substrate) as the solid-state imaging device, the yield is improved and the manufacturing cost is reduced, which is advantageous for reducing the cost of the mobile terminal. Further, since an interface circuit (I / O circuit) with the outside is not required, it is possible to reduce power consumption.

[0006]

However, when each circuit is mixedly mounted on the same substrate as the solid-state image pickup device, the operation clocks of the respective circuits become the same, and therefore, in synchronization with the rise or fall of the operation clock, A large current flows into the silicon substrate of the solid-state imaging device through the power supply terminal, and a voltage drop occurs due to the power supply common impedance of each circuit. In addition, since a large current also flows into the substrate terminal for making the silicon substrate a constant voltage, an inductance component due to a wiring connecting the substrate terminal and an external circuit, for example, a conductor such as an Au wire, causes a so-called ground bounce phenomenon. The voltage of the silicon substrate fluctuates.

In either case, the potential of the well forming each circuit fluctuates. Thereby, for example, when the potential of the well forming the solid-state image sensor changes,
Since the reference voltage of the photodiode that is performing photoelectric conversion fluctuates, the signal level of the image signal output from the solid-state image sensor may fluctuate and the image quality may deteriorate. Further, when the potential of the well in which each circuit is formed changes during the sampling period of the CDS circuit or the A / D conversion circuit, the sampling reference voltage changes, so that correct sampling is not performed and each output signal is output. Noise is mixed in, which also causes deterioration of image quality.

In order to prevent this, when each circuit is mixedly mounted on the same substrate as the solid-state image pickup device, a power supply terminal is provided for each circuit to reduce the common impedance as much as possible, or a plurality of board terminals are provided to reduce the inductance. Measures are taken to reduce the components. However, in either case, the number of external terminals of the solid-state imaging device is increased,
The area of the solid-state imaging device is increased, the number of I / O circuits is increased, and the like, which leads to an increase in manufacturing cost and a decrease in yield.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state image pickup device excellent in noise performance and less in image quality deterioration due to a change in well potential, and a driving method thereof. To provide.

[0010]

In order to achieve the above object, the present invention provides a solid-state image pickup device in which at least one of a noise removal circuit and an A / D conversion circuit is mixedly mounted on the same substrate as a solid-state image pickup device. The relative phase relationship of at least one of the operation clocks of the noise removal circuit and the A / D conversion circuit is adjustable with respect to the operation clock of the solid-state image sensor, and the phase relationship is adjusted appropriately.

At least one of the noise removal circuit and the A / D conversion circuit is adjusted by adjusting the relative phase relationship of the operation clock of at least one of the noise removal circuit and the A / D conversion circuit with respect to the operation clock of the solid-state image pickup device. In one circuit, the timing relationship can be set so that the circuit operation is performed during a period in which the influence of clock noise caused by the operation clock is small. In addition, since the rising timing and the falling timing of each operation clock are different, it is possible to disperse the through current, the charging / discharging current, etc. that instantaneously flow in synchronization with the rising and the falling. As a result, the peak value of the instantaneous current flowing into the solid-state imaging device through the power supply terminal can be suppressed to a small value.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a solid-state image pickup device according to an embodiment of the present invention. As is clear from FIG. 1, the solid-state imaging device according to the present embodiment includes a solid-state imaging device 11 including, for example, a CMOS image sensor,
CDS circuit 12 and A / D conversion circuit 1 which are the peripheral circuits
3 and the communication unit / timing generation circuit 14 are mixedly mounted on the same silicon substrate 15.

On the silicon substrate 15, the solid-state image pickup device 11 is provided.
There is provided a clock terminal 16 for externally taking in the master clock .phi.MST which is a reference for the operation of the above, a control terminal 17 for taking in a control command from the outside, and an output terminal 18 for outputting a digital output signal as an image pickup signal. The master clock φMST and the control command are input to the communication section / timing generation circuit 14 via the clock terminal 16 and the control terminal 17, respectively.

The communication unit / timing generation circuit 14 has a built-in clock generation circuit 19, and in the clock generation circuit 19, for example, three system operation clocks, that is, the operation of the solid-state image pickup device 11 is performed in response to an external control command. The clock φA, the operation clock φB of the CDS circuit 12 and the operation clock φC of the A / D conversion circuit 14 are generated based on the master clock φMST.

Here, as the operation clock φA, in the solid-state image pickup device 11, a vertical clock serving as a reference of vertical scanning for sequentially selecting the photosensitive pixels arranged in a matrix in a row unit, and each photosensitive pixel. A horizontal clock or the like serving as a reference for horizontal scanning for sequentially selecting the column by column.

The operation clock φB is a clamp pulse for clamping the feedthrough period including a noise component in the output signal of the solid-state image pickup device 11 in the CDS circuit 12 and a sampling pulse for sampling and holding the signal period. The operation clock φC is a sampling clock for sampling the signal level of the analog signal input in the A / D conversion circuit 14.

As described above, the solid-state image pickup device 11 is composed of a CMOS image sensor in which photosensitive pixels made up of a combination of photodiodes and MOS transistors are arranged in a matrix, and a signal obtained by photoelectric conversion at each photosensitive pixel. The electric charges are converted into electric signals in pixel units by vertical scanning and horizontal scanning based on the operation clock φA and output as image signals through signal lines.
This image signal is supplied to the CDS circuit 12.

As is well known, the CDS circuit 12 is a noise removing circuit for removing reset noise included in the output signal of the solid-state image pickup device 11, and clamps the feedthrough period of the output signal of the solid-state image pickup device 11 by the clamp pulse. After that, reset noise is removed by sampling and holding the signal period of the output signal by the sampling pulse.

The A / D conversion circuit 13 samples the analog output signal of the solid-state image pickup device 11 from which noise has been removed by the CDS circuit 12 at a sampling clock which is an operation clock φC, and A / D converts it into a digital output signal for output. To do. This digital output signal is output to the outside of the silicon substrate 15 via the output terminal 16.

FIG. 2 is a block diagram showing a concrete configuration example of the clock generation circuit 19. The clock generation circuit 19 according to the present example uses the frequency divider circuit 2 for each operation clock.
1, a delay circuit 22 and a pulse width adjusting circuit 23.

In the clock generation circuit 19, the frequency divider circuit 21 generates the operation clocks φA, φB and φC by dividing the master clock MCK with an appropriate frequency division ratio. The delay circuit 22 has operation clocks φA and φ.
Control their phase by delaying B and φC. The pulse width adjusting circuit 23 uses the operation clocks φA and φ.
The pulse width of B and φC, that is, the clock duty is controlled.

By controlling the phase in the delay circuit 22, the phase relationship among the operation clocks φA, φB and φC can be adjusted. That is, the delay circuit 22 uses the operation clock φ.
It has a function as an adjusting means capable of adjusting the relative phase relationship of A, φB, and φC. By the phase control by the delay circuit 22 and the pulse width control by the pulse width adjusting circuit 23, the rising timing and the falling timing of the operation clocks φA, φB, φC can be changed.

FIG. 3 shows a specific configuration example of the delay circuit 22. Here, as an example, the circuit configuration in the case of generating two output clocks for one input clock is shown, and since the circuits for generating two output clocks have basically the same configuration, Only one circuit configuration will be described.

The delay circuit 22 according to this example includes a plurality of delay elements serially connected to the clock input line 31, four delay elements 32-1 to 32-4 in this example.
And the input terminal of the delay element 32-1 in the first stage, the respective output terminals of the delay elements 32-1 to 32-4, and the clock output line 3.
Switch elements 34-1 to 34-5 connected between
It is configured to have and.

In the delay circuit 22, the switch element 34-1 is responsive to a control command given from the outside.
By turning on (closing) any one of ~ 34-5, the output point is changed, and the output clock delayed by the desired delay amount with respect to the input clock is generated. Here, the step size and range of the delay amount are the delay element 32-1.
~ 32-4 Depends on the individual delay amount and its quantity.

Next, the operation of the solid-state image pickup device having the above-described structure according to this embodiment will be described with reference to the timing chart of FIG.

First, an image signal is output from the solid-state image pickup device 11 in synchronization with the operation clock φA generated by the clock generation circuit 19 and supplied to the CDS circuit 12. CDS
The circuit 12 performs noise removal operation based on the operation clock φB generated by the clock generation circuit 19. Specifically, by utilizing the fact that the noise included in the feedthrough of the output signal of the solid-state image sensor 11 and the noise included in the signal have a correlation, the feedthrough of the output signal of the solid-state image sensor 11 is performed by the clamp pulse. After the period is clamped, the signal period of the output signal is sampled and held by the sampling pulse to cancel the noise component included in the output signal.

Here, in the clock generation circuit 19, by the phase control by the delay circuit 22 and the pulse width control by the pulse width adjusting circuit 23 of FIG. 2, the rising timing and the rising timing of the operation clocks φB and φC with respect to the operation clock φA. It is possible to adjust the falling timing.

Therefore, by appropriately adjusting the rising timing and the falling timing of the operation clock φB with respect to the operation clock φA, even if there are process variations in the solid-state image pickup element 11, the individual solid-state image pickup elements 11 can be processed. The sampling operation of the CDS circuit 12 can be performed in a stable period that is not affected by noise in the image signal. Further, by appropriately adjusting the rising timing and the falling timing of the operation clock φC with respect to the operation clock φA, the A / D conversion circuit 13 can be operated during a stable period of the output signal of the CDS circuit 12.
The sampling operation can be performed.

Further, in the clock generation circuit 19, not only the rising timing and falling timing of the operating clocks φB and φC can be adjusted with respect to the operating clock φA, but also the rising timing and falling timing of the operating clock φA can be adjusted. Therefore, the output signals of the respective circuits can be prevented from being disturbed by adjusting the rising timing and the falling timing of the operation clocks φA, φB, and φC.

As described above, the CDS circuits 12 and A
In a solid-state imaging device in which the A / D conversion circuit 13 is mixedly mounted on the same silicon substrate 15 as the solid-state imaging device 11, the operation clock φ of the solid-state imaging device 11 and each operation clock of the CDS circuit 12 and the A / D conversion circuit 13 By making it possible to adjust the relative phase relationship with φB and φC and adjusting the phase relationship as appropriate, it is possible to reduce the influence of clock noise generated due to the operation clocks φA, φB, and φC in each circuit. Since the CDS circuit 12 and the A / D conversion circuit 13 can perform sampling, it is possible to provide a solid-state imaging device having excellent noise resistance performance.

Further, since the operation clocks .phi.A, .phi.B, .phi.C have different rising timings and falling timings, it is possible to disperse a through current, a charging / discharging current, etc. which instantaneously flows in synchronization with the rising and falling timings. Therefore, the peak value of the instantaneous current flowing into the silicon substrate 15 of the solid-state imaging device through the power supply terminal can be suppressed to a small value. As a result, the fluctuation of the well potential can be suppressed to be small, and the noise due to the fluctuation of the well potential can be suppressed accordingly, so that the deterioration of the image quality can be suppressed.

Furthermore, by making the relative phase relationship with the respective operation clocks φB and φC variable by an external operation, adjustment can be made to cope with individual device differences due to process variations, etc. It is possible to set the optimum operation timing for the device.

From the above, the CDS circuit 12 and the A / D
Even when the conversion circuit 13 and the solid-state imaging device 11 are mounted on the same substrate 15 together, the effect of clock noise is small even if the external terminals of the solid-state imaging device are not increased or the area of the solid-state imaging device is not increased. Since high-quality images can be obtained, various electronic devices, especially mobile phones and PDAs
It is possible to provide a small-sized, lightweight, low-power-consumption solid-state imaging device suitable for mobile terminals such as.

Then, the solid-state image pickup device 1 is mounted by mounting the solid-state image pickup device on a portable terminal as its image input device.
Since the yield is improved and the manufacturing cost is reduced by embedding each circuit on the same substrate 15 as that of No. 1, it can greatly contribute to the cost reduction of the mobile terminal, and the interface circuit (I / O circuit) with the outside is unnecessary. Therefore, the power consumption of the mobile terminal can be greatly reduced.

In the above embodiment, the solid-state image sensor 1 is used.
The case where the CDS circuit 12 and the A / D conversion circuit 13 are both mounted on the same substrate 15 as 1 is applied to the solid-state imaging device, but the present invention is not limited to this. The same can be applied to a solid-state image pickup device in which only one of the A / D conversion circuits 13 is mounted.
In this case, the relative phase relationship between the operation clock φA of the solid-state image pickup device 11 and the operation clock φB of the CDS circuit 12 or the operation clock φC of the A / D conversion circuit 13 can be adjusted and appropriately adjusted. You can do it.

[0038]

As described above, according to the present invention,
In a solid-state imaging device in which at least one of a noise removal circuit and an A / D conversion circuit is mixedly mounted on the same substrate as the solid-state imaging device, at least the noise removal circuit and the A / D conversion circuit with respect to the operation clock of the solid-state imaging device. Since the relative phase relationship of one operation clock can be adjusted and adjusted appropriately, the optimum operation timing can be set for each circuit, so that the noise performance can be improved and the well potential It is possible to suppress image quality deterioration due to fluctuations.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration example of a clock generation circuit.

FIG. 3 is a block diagram showing a specific configuration example of a delay circuit.

FIG. 4 is a timing chart for explaining the operation of the solid-state imaging device according to the present embodiment.

FIG. 5 is a block diagram showing an example of a system configuration of a solid-state imaging device.

[Explanation of symbols]

11 ... Solid-state image sensor, 12 ... CDS circuit, 13 ... A / D
Conversion circuit, 14 ... Communication unit / timing generation circuit, 15 ...
Silicon substrate, 19 ... Clock generation circuit, 21 ... Dividing circuit, 22 ... Delay circuit, 23 ... Pulse width adjusting circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasuaki Hisamatsu             134, Kobe-cho, Hodogaya-ku, Yokohama-shi, Kanagawa               Sony LSI Design Stock Association             In-house (72) Inventor Keiji Mabuchi             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F-term (reference) 4M118 AA05 AB01 BA14 CA02 DD09                       FA06 FA50                 5C024 CX03 CY16 HX15 HX23

Claims (5)

[Claims] 1. At least one of a noise removing circuit for removing a noise component contained in an output signal of a solid-state image sensor and an A / D conversion circuit for analog / digital converting the output signal is on the same substrate as the solid-state image sensor. A solid-state image pickup device mounted on a solid-state image pickup device, comprising a phase adjustment capable of adjusting a relative phase relationship between an operation clock of the solid-state image pickup element and an operation clock of at least one of the noise removal circuit and the A / D conversion circuit. A solid-state imaging device having means. 2. The solid-state imaging device according to claim 1, wherein an operation clock of at least one of the noise removal circuit and the A / D conversion circuit is a sampling clock for sampling an output signal of the solid-state imaging device. apparatus. 3. The phase adjusting means has a delay means for delaying an operation clock of at least one of the noise removal circuit and the A / D conversion circuit by a predetermined delay amount with respect to an operation clock of the solid-state imaging device. The solid-state imaging device according to claim 1, wherein. 4. The phase adjusting means has a pulse width adjusting means for adjusting a pulse width of an operation clock of at least one of the noise removal circuit and the A / D conversion circuit with respect to an operation clock of the solid-state imaging device. The solid-state imaging device according to claim 3, wherein 5. A noise removal circuit for removing a noise component contained in an output signal of a solid-state image sensor and at least one of an A / D conversion circuit for analog / digital conversion of the output signal are on the same substrate as the solid-state image sensor. In the solid-state image pickup device mounted on, the relative phase relationship of the operation clocks of at least one of the noise removal circuit and the A / D conversion circuit is adjusted with respect to the operation clocks of the solid-state image pickup element. Method for driving solid-state imaging device.