JP2006303601A - Correlated double sampling circuit and solid-state imaging apparatus employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of canceling an offset of an input signal applied to a correlated double sampling circuit. <P>SOLUTION: The correlated double sampling circuit includes: an amplifier 16 with an input and an output; an input terminal receiving the input signal; an input capacitor 11 connected to the input terminal for first and second time phases; a feedback capacitor 18 connected to the output of the amplifier at the second time phase; a capacitor 15 connected between the amplifier input and a node for connection to the input capacitor and the feedback capacitor and for maintaining an offset cancel level for the second time phase; and a means for giving a first reference level to the capacitor maintaining the offset cancel level for the first time phase, and even when a circuit gain is varied, the correlated double sampling circuit cancels the offset of the input signal by applying the reference level to the capacitor maintaining the offset cancel level and varying the reference level with the circuit gain. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to, for example, a correlated double sampling circuit and a solid-state imaging device using the same, and a capacitor that holds an offset cancellation level is provided, and even when the circuit gain is varied, stable input signal offset cancellation is performed regardless of the gain. .

FIG. 7 shows a conventional CDS (Correlated Double Sampling Circuit) circuit 150 disclosed in Patent Document 2.
The CDS circuit 150 is set so as to switch SW (switch) and perform different operation modes.

During the sampling mode (reset) period in which the sampling operation is performed, feedback of gain 1 is applied, and the voltage follower is formed. During this reset period (q1), the input signal and the reference level (Vref) are sampled.
The amplifier that performs the hold operation with the amplifier, the hold mode (q2) period, the signal Vo of the output terminal Tout is:
[Equation 1]
Vo = Cs / Cfb (V1-V2) + Vref (1)

It is expressed.
Here, V1 and V2 are input signal levels from the CCD in the first and second time phases (q1 period, q2 period), respectively.

However, in equation (1), (V1−V2) is multiplied by the gain coefficient Cs / Cfb of the OP AMP 152, but the reference level Vref supplied from the reference power supply is not multiplied by gain. That is, V1 and V2 are related to gain, but Vref does not change even if the gain changes.
Therefore, when the gain of the circuit is controlled by changing at least one of the sampling (input) capacitor 151 and the feedback capacitor 154, and the reference level Vref of the reference power supply is changed to cancel the CCD offset, the reference power supply is supplied. The reference level Vref to be used must be changed greatly in accordance with the circuit gain, which is disadvantageous in obtaining stability.
USP 6,433,632 gazette JP 2001-28716 A

In an image sensor signal processing circuit or the like using a correlated double sampling circuit, an offset cancel state is maintained without changing the reference level Vref even when the circuit gain is variable.
In addition, the operation of the image sensor signal processing circuit is speeded up and stabilized.

The correlated double sampling circuit of the present invention is the correlated double sampling circuit, wherein the amplifier, the input terminal for receiving the image signal, the input capacitor connected to the input of the amplifier at the first and second time phases, A feedback capacitor connected to the output of the amplifier in a second time phase, and a node connected to the input capacitor and the feedback capacitor in the second phase time and connected to the input of the amplifier. And a means for inputting a first reference level to the capacitor holding the offset cancellation level in the first time phase.
The solid-state imaging device of the present invention is supplied with an image signal output from a solid-state imaging device, supplies the image signal to a correlated double sampling circuit, and supplies an output signal in which the offset of the input signal is canceled to a feedback circuit. A solid-state imaging device that calculates using a reference value and feeds back to correct an error in the black level of the input signal, wherein the correlated double sampling circuit includes an amplifier, an input terminal that receives the image signal, An input capacitor connected to the input of the amplifier in first and second time phases, a feedback capacitor connected to the output of the amplifier in the second time phase, and the input in the second phase time A capacitor that holds an offset cancellation level connected between a node to which the capacitor and the feedback capacitor are connected and the input of the amplifier. And Sita, in the first time phase, and a means for inputting a first reference level to the capacitor for holding the offset cancellation level.

In the correlated double sampling circuit of the present invention, the image sensor signal and the reference level Vref are multiplied by the same gain coefficient.
Therefore, the image sensor signal processing circuit using the correlated double sampling circuit according to the present invention can maintain the offset cancel state ideally without changing the reference level Vref even when the circuit gain is varied. In addition, the operation of the image sensor signal processing circuit can be speeded up and stabilized.
Furthermore, ideally, a configuration in which the charge transfer of the feedback capacitor from the reference level power supply is zero is possible, and low power consumption and good characteristics can be realized.

FIG. 1 shows a correlated double sampling circuit 10 which is an embodiment of the present invention.
The correlated double sampling circuit 10 includes an input capacitor C1 (11), a capacitor C3 (15) that holds an offset cancel level, a feedback capacitor C2 (18), OP AMP16, SW12, SW13, 14, and 17.
The input capacitor 11 is connected between the input terminal Tin and the node N1, SW13 is connected between the node N1 and GND (ground), and the node N1 is connected to one terminal of the SW12. The other terminal of SW12 is connected to node N2, which is connected to one terminal of SW14, one terminal of capacitor C3 (15) and one terminal of feedback capacitor C2 (18).
The other terminal of the capacitor 15 is connected to the inverting input terminal of the OP AMP 16 and one terminal of the SW 17. The other terminal of SW17 is connected to the output terminal Tout of OP AMP16 and the other terminal of feedback capacitor 18, and the non-inverting input terminal of OP AMP16 is connected to GND.

SW13, 14, and 17 are turned ON / OFF in synchronization with the control pulse φ1 (or also referred to as the first time phase), and SW12 is turned on in synchronization with the control pulse φ2 (or also referred to as the second time phase). / OFF operation, but the control pulse is out of phase and out of timing, and its detailed waveform and timing are shown in FIG.
During the first time phase, which is the time of sample (reset), SW13, 14, 17 are turned on to short-circuit, and at this time, SW12 is turned off and set to the open state. On the other hand, in the second time phase that is in the amplifier mode (hold), SW13, 14, and 17 are OFF and open, and SW12 is ON and shorted.
For example, a reference level (Vref) is supplied to one terminal of SW14 from a reference power supply, and is supplied to the node N2 in synchronization with the control pulse φ1.

Next, the operation of the correlated double sampling circuit 10 will be described with reference to the timing chart of FIG.
The first time phase φ1 of the sampling mode, that is, the voltage level of φ1 is “H” (high) during the period from time t0 to t1, time t4 to t5, etc., so SW13, 14, and 17 are turned on and short-circuited. Set to At this time, since the voltage level of φ2 is “L” (low) level, SW12 is turned OFF and is in an open state. During this period, the reset level V1 of the image sensor signal such as a CCD shown in FIG. 2A is sampled by the input capacitor C1 (11). Since SW14 is short-circuited, the reference level Vref is sampled by the feedback capacitor C2 (18) and the offset cancel level holding capacitor C3 (15). The output terminal Tout of the operational amplifier (OP AMP) 16 is connected to the inverting input terminal, and constitutes a feedback amplification circuit having a gain of 1. Further, since the non-inverting input terminal is grounded, the inverting input terminal has the same potential as the non-inverting dominant terminal and is virtually grounded. This signal ground level is buffered by OP AMP16 and supplied to feedback capacitor C2 and capacitor C3.

On the other hand, during the second time phase φ2 of the amplifier and hold mode, that is, during the period of time t2 to t3, time t6 to t7, etc., the voltage of φ2 is at “H” level (FIG. 2C), and the voltage of φ1 is “ L ″ level (FIG. 2B).
At this time, since the voltage of φ2 is at “H” level, SW12 is turned on and short-circuited. On the other hand, since the voltage of φ1 is at the “L” level, SW13, 14, and 17 are turned off and are in an open state.
In this SW connection state, a luminance level V2 of an image sensor signal such as a CCD is input (FIG. 2A). Since SW13, 14, and 17 are OFF and SW12 is ON, capacitors C1 (11) and C2 (15) are connected to OP AMP16. As a result, a feedback amplifier circuit is formed, and the following transfer function is realized.
[Equation 2]
Vo = C1 / C2 * (V1-V2 + Vref) (2)

Here, * represents a multiplication symbol.

From Equation (2), the difference between the reset level V1 and the luminance level V2 is amplified by the circuit gain C1 / C2 of the OP AMP16. Thereby, the low frequency noise of an image sensor can be removed like a prior art.
Furthermore, it is shown that the reference level Vref supplied from the reference power supply is also amplified with the circuit gain C1 / C2 of the OP AMP16.
Therefore, when the reset level V1, the luminance level V2, and the reference level Vref supplied from the reference power supply are simultaneously multiplied by the gain C1 / C2 of the OP AMP16 and the gain (gain) is varied, the reference level Vref becomes the reset level V1. Similar to the difference in luminance level V2, the same gain is multiplied and followed. Therefore, even when the gain is varied, it is not necessary to adjust the reference (voltage) level of the reference level Vref each time the gain changes, and an adjustment circuit associated therewith is not necessary.
Note that by making at least one of the input capacitor C1 and the feedback capacitor C2 variable, the circuit gain of the OP AMP 16 can be variably controlled.

  FIG. 3 shows another embodiment of the correlated double sampling circuit 30 of the present invention. The difference between the correlated double sampling circuit 30 and the correlated double sampling circuit 10 shown in FIG. 1 is that the feedback capacitor C2 (38) and the offset cancel level holding capacitor C3 (35) in the first time phase φ1. Is provided by signal ground directly without a buffer by the operational amplifier OP AMP36.

Next. The circuit configuration and operation of the correlated double sampling circuit 30 shown in FIG. 3 will be described.
The correlated double sampling circuit 30 includes an input capacitor C1 (31), an offset cancel level holding capacitor C3 (35), a feedback capacitor C2 (38), OP AMP36, SW32, SW33, 34 and SW37, 39, 40. Has been. The connection configuration of the SWs 37, 39, and 40 is different from the circuit configuration of FIG.
The input capacitor 31 is connected between the input terminal Tin and the node N1, SW33 is connected between the node N1 and GND (ground), and the node N1 is connected to one terminal of the SW32. The other terminal of SW32 is connected to node N2, which is connected to one terminal of SW34, one terminal of capacitor C3 (35) and one terminal of feedback capacitor C2 (38).
The other terminal of the capacitor 35 is connected to the inverting input terminal of the OP AMP 36 and one terminal of the SW 37. The other terminal of SW 37 is connected to the non-inverting input terminal of OP AMP 16 and GND. The other terminal of the feedback capacitor 38 is connected to one terminal of SW39 and SW40, the other terminal of SW39 is connected to GND, and the other terminal of SW40 is connected to the output terminal Tout of OP AMP36.

SW33, 34, 37, 39 are turned on / off in synchronization with the control pulse φ1 (first time phase), and SW32, 40 are turned on / off in synchronization with the control pulse φ2 (second time phase). Operate.
At the time of sample (reset), SW33, 34, and 37 are turned on to short-circuit, and at this time, SW32 and 40 are turned off and set to an open state. On the other hand, in the amplifier / hold mode, SWs 33, 34, and 37 are OFF and open, and SWs 32 and 40 are ON and shorted.
Further, for example, a reference level (Vref) is supplied to one terminal of the SW 34 from a reference power supply, and supplied to the node N2 in synchronization with the control pulse φ1, and a feedback capacitor C2 (38) and an offset cancel level holding capacitor C3 ( 35).

Next, the operation of the correlated double sampling circuit 30 will be described. However, since this circuit operation is basically the same as that of FIG. 1, detailed description thereof is omitted.
In the first time phase φ1 in the sampling mode, the SWs 33, 34, 37, and 39 are turned on and set to a short state. At this time, since the voltage level of φ2 is opposite to the voltage of φ1, the SWs 32 and 40 are turned off to be in an open state. During this period, for example, the reset level V1 of the image sensor signal is sampled by the input capacitor C1 (31). Since the SW 34 is short-circuited, the reference level (voltage) Vref is sampled by the feedback capacitor C2 (38) and the offset cancel level holding capacitor C3 (35).
At this time, the other terminals of the feedback capacitor C2 (38) and the offset cancel level holding capacitor C3 (35) are grounded to GND. Further, the inverting input terminal and the non-inverting input terminal of the OP AMP 36 are simultaneously grounded to GND.

On the other hand, during the second time phase φ2 in the amplifier / hold mode, the SWs 32 and 40 are turned on and short-circuited. On the other hand, during the same period, SW33, 34, 37 and 39 are turned off and opened.
In this SW connection state, for example, the luminance level V2 of the image sensor signal is input. Since SW33, 34, 37 and 39 are OFF and SW32 and 40 are ON, capacitors C1 and C2 are connected to OP AMP16. As a result, a feedback amplifier circuit is formed, and amplifier and hold operations are performed.
The transfer function at this time is the same as that in the equation (2), and the reference level Vref is multiplied by the gain of the OP AMP 36. Therefore, when the gain is varied, it is not necessary to adjust the level of the reference level Vref again.
Further, in this case, like the correlated double sampling circuit 10 shown in FIG. 1, the input offset of the operational amplifier is not canceled, but the circuit operates at a higher speed.

FIG. 4 shows a correlated double sampling circuit 50 according to another embodiment of the present invention.
This correlated double sampling circuit 50 differs from that of FIG. 1 in the connection configuration of SW and the reference level (Vref2) supplied to the feedback capacitor C2 (61) during sampling.
Next, the circuit configuration of the correlated double sampling circuit 50 shown in FIG. 4 will be described.
The input capacitor 51 is connected between the input terminal Tin and the node N1, SW53 is connected between the node N1 and GND (ground), and the node N1 is connected to one terminal of the SW52 and the feedback capacitor C2 (58). Yes. The other terminal of SW52 is connected to node N2, and this node N2 is connected to one terminal of SW54 and one terminal of capacitor C3 (55).
The other terminal of the capacitor C3 (55) is connected to the inverting input terminal of the OP AMP 56 and one terminal of the SW 59. The other terminal of the SW 59 is connected to the output terminal Tout of the OP AMP 16. The non-inverting input terminal of OP AMP is connected to GND.
The other terminal of feedback capacitor C2 (58) is connected to one terminal of SW60 and SW61, the other terminal of SW60 is connected to output terminal Tout of OP AMP56, and the other terminal of SW61 is set to reference level (voltage) Vref2. Connected to a reference power supply.

SW53, 54, 59, 61 are turned on / off in synchronization with the control pulse φ1 (first time phase), and SW52, 60 are turned on / off in synchronization with the control pulse φ2 (second time phase). Operate.
At the time of sampling (reset), SW53, 54, 59, 61 are turned on to be in a short state, and at this time, SW52, 60 are turned off to be in an open state. On the other hand, in the amplifier / hold mode, SWs 53, 54, 59 and 61 are OFF and open, and at that time SW 52 and 60 are ON and short.
For example, a reference level (Vref1) is supplied to one terminal of the SW 54 from a reference power supply, and is supplied to the node N2 in synchronization with the control pulse φ1. At the same time, the reference level Vref2 is supplied from the SW 61 to the feedback capacitor C2 (58), and the supplied reference levels (Vref1, Vref2) are sampled.

Next, the operation of the correlated double sampling circuit 50 will be described.
In the first time phase φ1 in the sampling mode, the SWs 53, 54, 59, 61 are turned on and set to the short state. At this time, since φ2 is in the opposite phase to φ1, SW52 and 60 are turned off to be in an open state. During this period, for example, the reset level V1 of the image sensor signal is sampled by the input capacitor C1 (51). Since the SW 54 is short-circuited, the reference level Vref1 is supplied to the offset cancel level holding capacitor C3 (55), and at the same time, the reference level Vref2 is supplied to the feedback capacitor C2 (58) and sampled. .
Since the SW 59 is short-circuited, the OP AMP 56 is configured such that the output terminal Tout is connected to the inverting input terminal and constitutes a feedback amplifier circuit having a gain of 1. Further, since the non-inverting input terminal is grounded, the inverting input terminal is also non-inverting capable. The potential is equal to the terminal and virtual grounding is performed.

On the other hand, during the second phase φ2 in the amplifier / hold mode, SWs 52 and 60 are turned on and short-circuited. On the other hand, since φ1 is in the opposite phase to φ, SW53, 54, 59, 61 are turned off and open.
In this SW connection state, for example, the luminance level V2 of the image sensor signal is input. Since SW53, 54, 59, and 61 are OFF and SW52 and 60 are in the ON state, capacitors C1 (51) and C2 (58) are connected to OP AMP16, thereby forming a feedback amplifier circuit. Is realized.
[Equation 3]
Vo = C1 / C2 * (V1-V2) + (C1 + C2) / C2 * Vref1
+ C2 / C2Vref2 (3)

However, in equation (3)
Vref2 = −Vref1

When the relationship becomes, it becomes as follows.
[Equation 4]
Vo = C1 / C2 * (V1-V2 + Vref1) (4)

This is the same as the transfer function of equation (2).
Therefore, even when the gain is varied, it is not necessary to adjust the voltage of the reference level Vref each time the gain changes, and an adjustment circuit associated therewith is not necessary.
Note that the circuit gain of the OP AMP 56 can be variably controlled by changing the value of at least one of the input capacitor C1 (51) and the feedback capacitor C2 (58).

FIG. 5 shows a correlated double sampling circuit 70 according to another embodiment of the present invention.
The correlated double sampling circuit 70 has a circuit configuration in which the reference level Vref supplied from the reference power supply is not supplied to the feedback capacitor.
Next, the circuit configuration of the correlated double sampling circuit 70 shown in FIG. 5 will be described.
The input capacitor C1 (71) is connected between the input terminal Tin and the node N1, SW73 is connected between the node N1 and GND (ground), and this node N1 is connected to one terminal of the SW72 and the feedback capacitor C2 (78). It is connected. The other terminal of SW72 is connected to node N2, and this node N2 is connected to one terminal of SW74 and one terminal of capacitor C3 (75).
The other terminal of the capacitor C3 (75) is connected to the inverting input terminal of the OP AMP 76 and one terminal of the SW 77. The other terminal of SW77 is connected to the output terminal Tout of OP AMP76. The non-inverting input terminal of OP AMP is connected to GND.
The other terminal of the feedback capacitor C2 (78) is connected to one terminal of SW79 and SW80, the other terminal of SW80 is connected to the output terminal Tout of OP AMP76, and the other terminal of SW79 is connected to GND.

SW73, 74, 77, 79 are turned on / off in synchronization with the control pulse φ1, and SW72, 80 are turned on / off in synchronization with the control pulse φ2.
At the time of sample (reset, φ1), SW73, 74, 77, 79 are turned on and shorted, and at this time, SW72, 80 are turned off and set to an open state. On the other hand, in the amplifier / hold mode (φ2), SWs 73, 74, 77, and 79 are OFF and open, and SW 72 and 80 are ON and shorted.
For example, a reference level (Vref1) is supplied to one terminal of SW74 from a reference power supply, and supplied to the node N2 in synchronization with the control pulse φ1. At the same time, SWs 73 and 79 are turned on and short-circuited to be connected to GND, so that the reference level (voltage) Vref is not supplied to the feedback capacitor C2 (78).

Next, the operation of the correlated double sampling circuit 70 will be described. However, since this circuit operation is basically the same as that of FIG. 1, detailed description thereof is omitted.
In the first time phase φ1 in the sampling mode, SWs 73, 74, 77, and 79 are turned on and set to a short state. At this time, since the voltage level of φ2 is in a phase opposite to φ1, SW72 and 80 are turned off and are in an open state. During this period, for example, the reset level V1 of the image sensor signal is sampled by the input capacitor C1 (71). Further, since the SW 74 is short-circuited, the reference level Vref is sampled by the offset cancel level holding capacitor C3 (75).
At this time, both terminals of the feedback capacitor C2 (78) are grounded to GND. Furthermore, since SW77 is ON and short-circuited, the inverting input terminal and the non-inverting input terminal of OP AMP 76 are connected to form a feedback amplifier circuit with a gain of 1.

On the other hand, during the second time phase φ2 in the amplifier / hold mode, SWs 72 and 80 are turned on and short-circuited. On the other hand, during the same period, SWs 73, 74, 77, and 79 are turned off and opened.
In this SW connection state, for example, the luminance level V2 of the image sensor signal is input. Since SW73, 74, 77 and 79 are OFF and SW72 and 80 are ON, capacitors C1 and C2 are connected to OP AMP 76. As a result, a feedback amplifier circuit is formed, and amplifier and hold operations are performed.
In this way, since the reference level Vref from the reference power source has no charge transfer to the feedback capacitor, more stable operation can be obtained.

The transfer function in the amplifier / hold mode is expressed by the following equation.
[Equation 5]
Vo = C1 / C2 * (V1-V2) + (C1 / C2 + 1) * Vref
... (5)

In this equation, the coefficient of the term of the reference level Vref supplied from the reference power supply is (C1 / C2 + 1), and becomes a value obtained by adding 1 to the gain C1 / C2, and the main signal (V1-V2), the reference level (Vref), and The gains are not exactly the same. However, if C1 / C2 is sufficiently larger than 1, this difference can be ignored.

Therefore, even when the gain is varied, it is not necessary to adjust the voltage level of the reference level Vref each time the gain changes, and an adjustment circuit associated therewith is also unnecessary.
Note that by making at least one of the values of the input capacitor C1 and the feedback capacitor C2 variable, the circuit gain of the OP AMP 76 can be variably controlled.

FIG. 6 shows an image sensor signal processing circuit 100 in which a correlated double sampling circuit 10 is applied to a solid-state imaging device according to another embodiment of the present invention.
As the image sensor signal processing circuit 100, the correlated double sampling circuit shown in FIGS. 3 to 5 other than FIG. 1 can be applied.
In the image sensor signal processing circuit of FIG. 6, for example, the output of the CCD image sensor 120 is connected to the input terminal Tin of the correlated double sampling circuit, and the output terminal of the correlated double sampling circuit is connected to the input of the variable gain amplifier 110. The The output of the variable gain amplifier 110 is connected to an ADC (analog / digital conversion circuit; A / D conversion circuit) 111 to output digital data.
The output terminal of the ADC 111 is connected to the output terminal Tout and the subtractor 113. The other input of the subtractor 113 is supplied with a reference code (data), and the output terminal for outputting the difference data is the logic circuit 114 in the next stage. Connected to.
The output terminal of the logic circuit 114 is connected to a DAC (digital / analog conversion circuit; D / A conversion circuit) 115, where a digital signal is converted into an analog signal. The output terminal of the DAC 115 is connected to the buffer 116, and the output of the buffer 116 is connected to the bypass capacitor 117 and the SW 104.

As described above, another variable amplifying circuit 110 is arranged after the correlated double sampling circuit (10). In general, the gain control of the correlated double sampling circuit at the front stage is coarse, and the gain control of the variable amplifier circuit 110 at the rear stage is often set finely.
Further, the analog signal (value) is converted into a digital value by the A / D conversion circuit 111 at the subsequent stage, and the output of the A / D conversion circuit 111 becomes the output of the image sensor signal processing circuit.
The output from the A / D conversion circuit 111 also passes through several circuit elements such as a subtractor 113, a logic circuit 114, a DA conversion circuit (DAC) 115, a buffer 116, a bypass capacitor 117, and the like to a correlated double sampling circuit. Returned.
This feedback system cancels not only the image sensor 120 but also the analog circuit offsets of the correlated double sampling circuit (10), the variable amplifier circuit 110, and the A / D converter circuit 111, and the black level as a reference is set. Converges to the specified reference code value.
The logic circuit 114 generates a correction amount for the error from the current reference black level error. The correction amount is converted into an analog amount by the D / A conversion circuit 115 and is fed back to the correlated double sampling circuit through the buffer 116 as a reference level (Vref). A bypass capacitor 117 that bypasses the buffer (116) output absorbs kickback due to switching of the correlated double sampling circuit and stabilizes the reference level Vref.
By using the above-described correlated double sampling circuit in the solid-state imaging device, even when the gain is varied, it is not necessary to adjust the voltage level of the reference level Vref each time the gain changes, and the adjustment circuit associated therewith is also unnecessary. Become.

It is a figure which shows the circuit structure of the correlation double sampling circuit which is the embodiment of this invention. 2 is a timing chart for explaining the operation of the correlated double sampling circuit according to the embodiment of the present invention shown in FIG. It is a figure which shows the circuit structure of the correlation double sampling circuit which is the other embodiment of this invention. It is a figure which shows the circuit structure of the correlation double sampling circuit which is the other embodiment of this invention. It is a figure which shows the circuit structure of the correlation double sampling circuit which is the other embodiment of this invention. It is a block diagram which shows the principal part of the solid-state imaging device using the correlated double sampling circuit which is the other embodiment of this invention. It is a figure which shows the circuit structure of the correlated double sampling circuit of a prior art example.

Explanation of symbols

10, 30, 50, 70, 150 ... correlated double sampling circuit, 11, 31, 51, 71, 101, 151 ... input capacitor, 12, 13, 14, 17, 32, 33, 34, 37, 39, 40 , 52, 53, 54, 59, 60, 61, 72, 73, 74, 77, 79, 80, 102, 103, 104, 107, 153, 155, 156... SW (switch), 15, 35, 55, 75, 105: Capacitor for holding offset cancel level, 16, 36, 56, 76, 106, 152 ... Operational amplifier (OP AMP), 18, 38, 58, 78, 108, 154 ... Feedback capacitor, 100 ... Image sensor signal Processing circuit 110... Variable gain amplifier 111... ADC (AD conversion circuit; analog-digital conversion circuit) 113 113 Subtractor 114. Circuit 115... DAC (DA conversion circuit; digital-analog conversion circuit), 116 buffer, 117 bypass capacitor (capacitance).

Claims (10)

In correlated double sampling circuit,
An amplifier,
An input for receiving an input signal; and an input capacitor connected to the input of the amplifier at first and second time phases;
A feedback capacitor connected to the output of the amplifier in the second time phase;
A capacitor for holding an offset cancellation level connected between a node to which the input capacitor and the feedback capacitor are connected and an input of the amplifier in the second phase time;
Means for inputting a first reference level to a capacitor that holds the offset cancellation level in the first time phase. The correlated double sampling circuit according to claim 1, wherein the means for inputting the reference level inputs the first reference level to the feedback capacitor in the first time phase. The correlated double sampling circuit according to claim 1, further comprising means for inputting a second reference level to the feedback capacitor in the first time phase. 4. The correlated double sampling circuit according to claim 3, wherein the first reference level and the second reference level are varied so as to cancel each other. The correlated double sampling circuit according to claim 1, wherein the gain of the correlated double sampling circuit changes a value to at least one of the input capacitor and the feedback capacitor. An image signal output from the solid-state imaging device is supplied, the image signal is supplied to a correlated double sampling circuit, and an output signal in which the offset of the image signal is canceled is supplied to a feedback circuit to perform calculation using a reference value. A solid-state imaging device that feeds back and corrects an error of the black level of the input signal,
The correlated double sampling circuit is
An amplifier,
An input for receiving the image signal; and an input capacitor connected to the input of the amplifier at first and second time phases;
A feedback capacitor connected to the output of the amplifier in the second time phase;
A capacitor for holding an offset cancellation level connected between a node to which the input capacitor and the feedback capacitor are connected and an input of the amplifier in the second phase time;
Means for inputting a first reference level to a capacitor holding the offset cancellation level in the first time phase. The solid-state imaging device according to claim 6, wherein the means for inputting the reference level inputs the first reference level to the feedback capacitor in the first time phase. The solid-state imaging device according to claim 6, wherein the correlated double sampling circuit further includes means for inputting a second reference level to the feedback capacitor in the first time phase. The solid-state imaging device according to claim 8, wherein the first reference level and the second reference level are varied so as to cancel each other. The solid-state imaging device according to claim 6, wherein a gain of the correlated double sampling circuit changes a value of at least one of the input capacitor and the feedback capacitor.

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