JP4121969B2 - Analog to digital converter - Google Patents

Description

  The present invention relates to an analog-digital converter. The present invention particularly relates to pipeline-type and cyclic-type analog-digital converters.

In recent years, various additional functions such as an image photographing function, an image reproducing function, a moving image photographing function, and a moving image reproducing function have been installed in portable devices such as mobile phones. Accordingly, there is an increasing demand for miniaturization and power saving of analog-digital converters (hereinafter referred to as “AD converters”). As a form of such an AD converter, a cyclic AD converter configured in a circulation type is known (see, for example, Patent Document 1). Patent Document 1 discloses a pipeline AD converter including two stages including a cyclic conversion portion.
JP-A-4-26229

  In the first stage of the AD converter shown in FIG. 1 of Patent Document 1, a sample and hold circuit S / H1 is provided in parallel with a system comprising a parallel A / D converter AD1 and a D / A converter DA1. Is provided. The analog input signal of this circuit is held for a predetermined period by this sample and hold circuit S / H1.

  However, since an operational amplifier is included in the constituent elements of the sample-and-hold circuit, the output voltage range of the sample-and-hold circuit tends to narrow when the voltage is low. In particular, in the first stage, which is most important in terms of the circuit configuration, characteristic degradation such as distortion due to narrowing of the output voltage range of the sample-and-hold circuit becomes large at low voltage, and the characteristics of the entire AD converter are increased. There is a problem that it gets worse.

  The present invention has been made in view of such circumstances, and an object of the present invention is to improve characteristics at the time of a low voltage in a pipeline type and a cyclic type AD converter.

  One embodiment of the present invention is an analog-digital converter. This analog-to-digital converter is an analog-to-digital converter that converts an input analog signal into a digital value by dividing it into a plurality of times, and has a plurality of stages that convert an input analog signal into a digital value of a predetermined number of bits, One or more of the plurality of stages is a stage that amplifies an analog signal input to the own stage by a single amplifying element, and the amplifying element samples and holds the analog signal input to the own stage. A first subtracting amplifier circuit that subtracts and amplifies a signal obtained by converting a digital value converted at its own stage into an analog value from the held analog signal, and one or more other stages among the plurality of stages Is a stage for amplifying an analog signal input to the stage by a plurality of amplifying elements, and one of the amplifying elements is 1 The amplifying element is a sample-and-hold circuit that samples and holds an analog signal input to the own stage, or an amplifier circuit that samples and amplifies the analog signal input to the own stage at a predetermined amplification rate. Another amplifying element is a second subtracting amplifying circuit that subtracts and amplifies a signal obtained by converting a digital value converted in its own stage into an analog value from a sample-and-hold circuit or an analog signal output from the amplifying circuit. It is.

  According to this aspect, the subtracting amplifier circuit of a stage samples and holds the input, and the sample hold circuit is mixed by mixing the stage from which the sample hold circuit previously provided in parallel with the AD converter circuit is removed. It is possible to improve the characteristics of the entire AD converter. Since the sample-and-hold circuit degrades signals outside the output range, removing this improves the characteristics at low voltage. The “amplifying element” includes an element that amplifies at a gain of 1 ×, that is, a sample hold circuit.

  The first subtracting amplifier circuit may directly sample the analog signal in synchronization with the timing of sampling the analog signal input to the stage for digital conversion. According to this, even if the sample-and-hold circuit provided conventionally is removed, it is possible to subtract the component converted at its own stage without error.

  The stage including the first subtracting amplifier circuit may be the first stage. According to this, it is possible to eliminate the characteristic deterioration that has occurred in the sample-and-hold circuit of the first stage that handles particularly large signals, and to improve the characteristics of the entire AD converter.

  Any stage among the plurality of stages may be a cyclic stage in which the output analog signal of the own stage is fed back to the input of the own stage. When a cyclic type stage is mixed, the circuit area can be reduced.

  The first subtracting amplifier circuit may hold the sampled analog signal until at least the conversion of the digital value converted at its own stage into the analog value is confirmed. According to this, a signal obtained by converting the digital value converted at its own stage into an analog value, which is input after the subtraction amplifier circuit enters the amplification period, is different from the sample value held by the subtraction amplifier circuit. Without subtraction, the same sample value can be subtracted and amplified.

  The first subtracting amplifier circuit may be amplified for a period longer than the auto-zero period. According to this, by setting the amplification period long, the settling time can be ensured, and high magnification amplification can also be performed.

  Note that any combination of the above-described constituent elements, and those in which the constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, characteristics at a low voltage are improved in a pipeline type or cyclic type AD converter.

(First embodiment)
In this embodiment, the AD converter circuit of the first stage converts 4 bits, and the AD converter circuit of the second stage converts 3 bits twice to convert 10 bits in total. It is an example of a converter.

  FIG. 1 shows a configuration of an AD converter according to the first embodiment. In the initial state, the first switch SW1 is on and the second switch SW2 is off. In this AD converter, the input analog signal Vin is input to the subtraction amplification circuit 13 and the first AD conversion circuit 11. The first AD conversion circuit 11 converts an input analog signal into a digital value and takes out the upper 4 bits (D9 to D6). The AD conversion circuit 11 may be a flash type for high-speed conversion. The first DA conversion circuit 12 converts the digital value converted by the first AD conversion circuit 11 into an analog value. The subtraction amplification circuit 13 samples the input analog signal Vin in synchronization with the sampling timing of the first AD conversion circuit 11, holds it for a predetermined period, and outputs the analog signal output from the first DA conversion circuit 12 from the held analog signal. Is amplified by 8 times. The predetermined period is a period that is at least equal to or longer than a period during which conversion data of the first DA conversion circuit 12 is determined.

  An analog signal input via the first switch SW1 is input to the second amplifier circuit 17 and the second AD conversion circuit 15. The second AD conversion circuit 15 converts the input analog signal into a digital value, and takes out 5 to 7 bits (D8 to D6) from the higher order. The second DA conversion circuit 16 converts the digital value converted by the second AD conversion circuit 15 into an analog value.

  The second amplifier circuit 17 amplifies the input analog signal by a factor of 2 and outputs the amplified signal to the second subtractor circuit 18. The second subtraction circuit 18 subtracts the output of the second DA conversion circuit 16 from the output of the second amplification circuit 17. The output of the second DA converter circuit 16 is amplified twice.

  Here, a method for amplifying the output of the second DA converter circuit 16 twice will be briefly described. The high potential side reference voltage VRT and the low potential side reference voltage VRB are supplied to the second AD conversion circuit 15 and the second DA conversion circuit 16 to generate a reference voltage range. The second AD converter circuit 15 uses this reference voltage range to generate reference voltages for a plurality of voltage comparison elements (not shown). The second DA conversion circuit 16 outputs a high potential side reference voltage VRT and a low potential side reference voltage VRB selectively to each of a plurality of capacitors (not shown) by the control from the second AD conversion circuit 15. Getting voltage. The ratio between the reference voltage range of the second AD conversion circuit 15 and the reference voltage range of the second DA conversion circuit 16 may be set to 1: 2.

  The third amplification circuit 19 amplifies the output of the second subtraction circuit 18 four times. At this stage, the first switch SW1 is turned off and the second switch SW2 is turned on. The output analog signal of the third amplifier circuit 19 is fed back to the second amplifier circuit 17 and the second AD converter circuit 15 via the second switch SW2. Instead of the second subtraction circuit 18 and the third amplification circuit 19, a subtraction amplification circuit similar to the first stage may be used. According to this, the circuit can be simplified. Thereafter, the above process is repeated, and the second AD conversion circuit 15 takes out 8 to 10 bits (D2 to D0) from the upper order. In this way, a 10-bit digital value is obtained. 5 to 10 bits (D5 to D0) from the top are obtained by the cyclic configuration.

  In the above description, the amplification factor of the second amplification circuit 17 is doubled and the amplification factor of the third amplification circuit 19 is four times. However, the second amplification circuit 17 is used as a sample hold circuit, and the amplification factor is three times. The amplification factor of the circuit 19 may be 8 times. In this way, it is sufficient that the number is 8 times before the next conversion of the second AD conversion circuit 15.

  FIG. 2 is a diagram showing a case where the subtracting amplifier circuit 13 is composed of a single-ended switched capacitor operational amplifier. FIG. 3 is a timing chart showing the operation of the subtraction amplification circuit 13. In FIG. 2, an input capacitor C1 is connected to the inverting input terminal of the operational amplifier 100, an input analog signal Vin is input via the Vin switch SW12, and the first DA converter circuit 12 is input via the VDA switch SW13. Output analog signal VDA is input. The non-inverting input terminal of the operational amplifier 100 is connected to the auto-zero potential. The output terminal and the inverting input terminal of the operational amplifier 100 are connected via a feedback capacitor C2. Further, an auto-zero switch SW11 is connected to the outside thereof, and the output terminal and the inverting input terminal of the operational amplifier 100 can be short-circuited.

  Next, the operation of the subtraction amplification circuit 13 shown in FIG. 2 will be described with reference to FIG. First, the auto-zero switch SW11 is turned on in order to set the auto-zero potential Vag. In this state, both the input side node N1 and the output side node N2 are at the auto-zero potential Vag. In order to sample the input analog signal Vin, the Vin switch SW12 is turned on and the VDA switch SW13 is turned off. At this time, the charge QA of the input side node N1 is expressed by the following equation (A1).

  QA = C2 (Vin−Vag) (A1)

  Next, in order to hold the voltage input to the input terminal of the input capacitor C1, that is, the input analog signal Vin sampled in the input capacitor C1, at the end of the auto-zero period, the Vin switch SW12 is turned off. . Next, when the conversion data of the first DA conversion circuit 12 is determined, the auto-zero switch SW11 is turned off to amplify the operational amplifier 100 by virtually grounding it. Thereafter, the VDA switch SW13 is turned on to subtract the output analog signal VDA from the first DA converter circuit 12. At this time, the charge QB of the input side node N1 is represented by the following equation (A2).

  QB = C2 (VDA−Vag) + C1 (Vout−Vag) (A2)

  Since the input node N1 does not have a path through which charges escape, QA = QB is obtained from the law of conservation of charge, and the following expression (A3) is established.

Vout = C2 / C1 (Vin−VDA) + Vag (A3)

  Therefore, when the auto-zero potential Vag is ideally the ground potential, the single-ended switched capacitor operational amplifier returns the difference between the input analog signal Vin and the output analog signal VDA of the first DA converter circuit 12 as feedback from the input capacitor C1. It can be amplified by the capacitance ratio with the capacitor C2. Of course, even if the auto-zero potential Vag is not the ground potential, an approximate value can be obtained. Although an example of a single-ended switched capacitor operational amplifier has been described, it is of course possible to configure it with a fully differential switched capacitor operational amplifier.

  FIG. 4 is a timing chart illustrating a first operation example of the AD converter according to the first embodiment. Hereinafter, description will be made in order from the top of the figure. The three signal waveforms indicate the first clock signal CLK1, the second clock signal CLK2, and the switch signal CLKSW. The frequency of the second clock signal CLK2 is twice the frequency of the first clock signal CLK1.

  The subtracting amplifier circuit 13 and the first AD converter circuit 11 sample the input analog signal Vin at the rising edge of the first clock signal CLK1 from low to high. The subtracting amplifier circuit 13 holds the sampled input analog signal Vin when the second clock signal CLK2 having a rising edge synchronized with the rising edge of the first clock signal CLK1 is high. Subtracts and amplifies when the same period is low, and performs auto-zero operation when the next period is low. The first AD converter circuit 11 performs a conversion operation when the second clock signal CLK2 having a rising edge synchronized with the rising edge of the first clock signal CLK1 is high, and outputs digital values D9 to D6, one of which. Auto zero operation when the previous period is low. The first DA conversion circuit 12 becomes indefinite when the second clock signal CLK2 having a rising edge synchronized with the rising edge of the first clock signal CLK1 is high, and holds the conversion confirmation data when it is low in the same cycle. .

  The first switch SW1 is turned on when the switch signal CLKSW is low and turned off when the switch signal CLKSW is high. The second switch SW2 is turned on when the switch signal CLKSW is high, and is turned off when the switch signal CLKSW is low. The second amplifier circuit 17 samples the input analog signal at the rising edge of the second clock signal CLK2 from low to high during the high period of the switch signal CLKSW. The analog signal is amplified when the second clock signal CLK2 immediately after sampling is low, and the auto-zero operation is performed when the second clock signal CLK2 immediately before sampling is high. The third amplifier circuit 19 samples the input analog signal at the falling edge of the second clock signal CLK2 synchronized with the falling edge of the switch signal CLKSW. The analog signal is amplified when the second clock signal CLK2 immediately after sampling is low, and the auto-zero operation is performed when the second clock signal CLK2 immediately before sampling is high. The second AD conversion circuit 15 samples the analog signal input at the rising edge of the second clock signal CLK2 from low to high. The second AD converter circuit 15 performs a conversion operation when the second clock signal CLK2 is high, and performs an auto-zero operation when the second clock signal CLK2 is low. The second DA converter circuit 16 holds the conversion confirmation data when the second clock signal CLK2 is low, and becomes indefinite when the second clock signal CLK2 is high.

  As shown in the figure, while the first AD conversion circuit 11 performs the conversion process on D9 to D6, the second AD conversion circuit 15 simultaneously converts the previously input D2 to D0. By such pipeline processing, the AD converter as a whole can output a 10-bit digital value once per cycle with reference to the first clock signal CLK1.

  FIG. 5 is a timing chart illustrating a second operation example of the AD converter according to the first embodiment. The second operation example is an example in which the amplification period of the subtraction amplifier circuit 13 is set longer than that in the first operation example. Hereinafter, description will be made in order from the top of the figure. The two signal waveforms indicate the first clock signal CLK1 and the second clock signal CLK2. The frequency of the second clock signal CLK2 is twice the frequency of the first clock signal CLK1.

  The subtracting amplifier circuit 13 and the first AD converter circuit 11 sample the input analog signal Vin at the rising edge of the first clock signal CLK1 from low to high. The subtracting amplifier circuit 13 holds the sampled input analog signal Vin when the second clock signal CLK2 having a rising edge synchronized with the rising edge of the first clock signal CLK1 is high. When the same period is low and the next period is high, subtraction amplification is performed, and when the period is low, auto-zero operation is performed. The first AD converter circuit 11 performs a conversion operation and outputs digital values D9 to D6 when the second clock signal CLK2 having a rising edge synchronized with the rising edge of the first clock signal CLK1 is high, and outputs the first clock signal D9 to D6. When the signal CLK1 is low, the auto-zero operation is performed when the second clock signal CLK2 is low. The first DA converter circuit 12 becomes indeterminate when the second clock signal CLK2 having a rising edge synchronized with the rising edge of the first clock signal CLK1 is high, and when it is low in the same cycle and high in the next cycle. Holds conversion confirmation data.

  The first switch SW1 is turned on when the first clock signal CLK1 is low, and is turned off when the first clock signal CLK1 is high. The second switch SW2 is turned on when the first clock signal CLK1 is high, and is turned off when the first clock signal CLK1 is low. The second amplifier circuit 17 samples the input analog signal at the falling edge of the second clock signal CLK2 from high to low during the low period of the first clock signal CLK1. The analog signal is amplified when the second clock signal CLK2 immediately after sampling is low, and the auto-zero operation is performed when the second clock signal CLK2 immediately before sampling is high. The third amplifier circuit 19 samples the input analog signal at the rising edge of the second clock signal CLK2 synchronized with the rising edge of the first clock signal CLK1. The analog signal is amplified when the second clock signal CLK2 immediately after sampling is high, and the auto-zero operation is performed when the second clock signal CLK2 immediately before sampling is low. The second AD conversion circuit 15 samples the analog signal input at the falling edge of the second clock signal CLK2 from high to low. The conversion operation is performed when the second clock signal CLK2 is low, and the auto-zero operation is performed when the second clock signal CLK2 is high. The second DA conversion circuit 16 holds the conversion confirmation data when the second clock signal CLK2 is high, and becomes indefinite when the second clock signal CLK2 is low.

  As shown in the figure, the second AD conversion circuit 15 simultaneously converts D2 to D0 inputted previously in the same cycle as the cycle in which the first AD conversion circuit 11 converts D9 to D6. By such pipeline processing, the AD converter as a whole can output a 10-bit digital value once per cycle with reference to the first clock signal CLK1.

  In the second operation example, the subtraction amplification time of the subtraction amplification circuit 13 can be made longer than that in the first operation example. As in the subtracting amplifier circuit 13 of FIG. 1, when a high amplification factor such as 8 times is required, the settling time becomes longer, and therefore it is preferable to operate at the timing as in the second operation example. Further, when the subtraction amplification circuit 13 does not require a high amplification factor, the settling time is shortened, and therefore the timing as in the first operation example may be used. As described above, according to the first embodiment, in a pipelined AD converter including two stages including a cyclic AD conversion portion, a sample conventionally provided in parallel with the first stage AD conversion circuit 11 is provided. The hold circuit can be deleted. This improves the characteristics, particularly the linear characteristics. Therefore, low voltage input is also possible. In addition, the circuit area can be reduced and the power consumption can be reduced.

(Second Embodiment)
This embodiment includes three stages in which 4 bits are converted by the AD converter circuit of the first stage, 3 bits are converted by the AD converter circuit of the second stage, and 3 bits are converted by the AD converter circuit of the third stage. It is an example of a pipeline type AD converter.

  FIG. 6 shows the configuration of the AD converter in the second embodiment. In this AD converter, the input analog signal Vin is input to the subtraction amplification circuit 13 and the first AD conversion circuit 11. The first AD conversion circuit 11 converts an input analog signal into a digital value and takes out the upper 4 bits (D9 to D6). The first DA conversion circuit 12 converts the digital value converted by the first AD conversion circuit 11 into an analog value. The subtraction amplification circuit 13 samples the input analog signal Vin in synchronization with the sampling timing of the first AD conversion circuit 11, holds it for a predetermined period, and outputs the analog signal output from the first DA conversion circuit 12 from the held analog signal. Is amplified by a factor of 4. The predetermined period is a period that is at least equal to or longer than a period during which conversion data of the first DA conversion circuit 12 is determined.

  The output analog signal of the subtraction amplification circuit 13 is input to the second amplification circuit 17 and the second AD conversion circuit 15. The second AD conversion circuit 15 converts the input analog signal into a digital value, and takes out 5 to 7 bits (D5 to D3) from the higher order. The reference voltage of the voltage comparison element in the second AD conversion circuit 15 is set to 1/2 that of the first AD conversion circuit 11. Originally, since the second AD conversion circuit 15 is 3-bit conversion, it must be amplified by 8 (2 to the 3rd power) by the subtraction amplification circuit 13. In this regard, if the reference voltage is set to ½ as described above, the amplification factor of the subtracting amplifier circuit 13 is quadrupled. The second DA conversion circuit 16 converts the digital value converted by the second AD conversion circuit 15 into an analog value. The second amplifier circuit 17 amplifies the input analog signal by a factor of 2 and outputs the amplified signal to the second subtractor circuit 18. The second subtraction circuit 18 subtracts the output of the second DA conversion circuit 16 from the output of the second amplification circuit 17. The output of the second DA converter circuit 16 is amplified twice.

  The third amplification circuit 19 amplifies the output of the second subtraction circuit 18 four times. The output analog signal of the third amplifier circuit 19 is output to the third AD conversion circuit 20. The third AD conversion circuit 20 converts the input analog signal into a digital value, and extracts 8 to 10 bits (D2 to D0) from the upper order. In this way, a 10-bit digital value is obtained in three stages.

  FIG. 7 is a timing chart illustrating an operation example of the AD converter according to the second embodiment. Hereinafter, description will be made in order from the top of the figure. The two signal waveforms indicate the first clock signal CLK1 and the second clock signal CLK2. The frequency of the second clock signal CLK2 is twice the frequency of the first clock signal CLK1.

  The subtracting amplifier circuit 13 and the first AD converter circuit 11 sample the input analog signal Vin at the rising edge of the first clock signal CLK1 from low to high. The subtracting amplifier circuit 13 holds the sampled input analog signal Vin when the second clock signal CLK2 having a rising edge synchronized with the rising edge of the first clock signal CLK1 is high. Subtracts and amplifies when the same period is low, and performs auto-zero operation when the next period is low. The first AD converter circuit 11 performs a conversion operation when the second clock signal CLK2 having a rising edge synchronized with the rising edge of the first clock signal CLK1 is high, and outputs digital values D9 to D6, one of which. Auto zero operation when the previous period is low. The first DA conversion circuit 12 becomes indefinite when the second clock signal CLK2 having a rising edge synchronized with the rising edge of the first clock signal CLK1 is high, and holds the conversion confirmation data when it is low in the same cycle. .

  The second amplifier circuit 17 and the second DA converter circuit 16 sample the input analog signal at the rising edge of the second clock signal CLK2 synchronized with the falling edge of the first clock signal CLK1. The second amplifier circuit 17 amplifies the analog signal when the second clock signal CLK2 immediately after sampling is high, and performs an auto-zero operation when the second clock signal CLK2 immediately before sampling is low. The second AD converter circuit 15 performs a conversion operation when the second clock signal CLK2 immediately after sampling is high, and performs an auto-zero operation when the second clock signal CLK2 immediately before sampling is low. The second DA conversion circuit 16 holds the conversion confirmation data when the first clock signal CLK1 is low and the second clock signal CLK2 is low, and becomes indefinite when the second clock signal CLK2 is high. The third amplifier circuit 19 samples the input analog signal at the falling edge of the second clock signal CLK2 from high to low while the first clock signal CLK1 is low. The analog signal is amplified when the second clock signal CLK2 immediately after sampling is low, and the auto-zero operation is performed when the second clock signal CLK2 immediately before sampling is high. The third AD converter circuit 20 samples the input analog signal Vin at the rising edge of the first clock signal CLK1 from low to high. The conversion operation is performed when the second clock signal CLK2 immediately after sampling is high, and the auto-zero operation is performed when the second clock signal CLK2 immediately before sampling is low.

  As shown in the figure, while the first AD conversion circuit 11 performs conversion processing on D9 to D6, the third AD conversion circuit 20 simultaneously converts D2 to D0 input last time. By such pipeline processing, the AD converter as a whole can output a 10-bit digital value once per cycle with reference to the first clock signal CLK1.

  As described above, according to the second embodiment, in the pipeline type AD converter including a plurality of stages, the sample hold circuit that is conventionally provided in parallel with the first AD conversion circuit 11 of the first stage is deleted. Can do. This improves the characteristics, particularly the linear characteristics. Therefore, low voltage input is also possible. In addition, the circuit area can be reduced and the power consumption can be reduced.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications can be made to combinations of each component and each processing process. Those skilled in the art will appreciate that such modifications are also within the scope of the present invention.

  Parameters such as the number of conversion bits of the AD converter circuit and its distribution, the amplification factor of the amplifier circuit, and the capacitance value described in each embodiment are merely examples, and other numerical values may be adopted for these parameters in the modification. Good.

  In the first embodiment, the two-stage cyclic AD converter has been described. In this respect, the present invention can also be applied to a cyclic type of one AD conversion circuit. That is, after the first AD conversion, the input is switched to the feedback side path, amplified by the amplifier circuit in the feedback circuit, and then the analog signal is input again to the AD converter circuit and the subtracting amplifier circuit. This also provides the same effect as that of the first embodiment.

  In the second embodiment, a three-stage pipelined AD converter has been described. In this respect, the number of stages is arbitrary, and when the number of conversion bits is large or when it is desired to improve the conversion accuracy, a multistage pipeline can be configured. Further, the timing shown in FIG. 7 is an example, and the subtracting amplifier circuit 13 may have a long amplification period in order to secure the settling time.

It is a figure which shows the structure of the AD converter in 1st Embodiment. It is a figure which shows the structure of a subtraction amplifier circuit. It is a timing chart which shows operation | movement of a subtraction amplifier circuit. It is a timing chart which shows the 1st operation example of the AD converter in 1st Embodiment. It is a timing chart which shows the 2nd operation example of the AD converter in 1st Embodiment. It is a figure which shows the structure of the AD converter in 2nd Embodiment. It is a timing chart which shows the operation example of the AD converter in 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 1st AD converter circuit, 12 1st DA converter circuit, 13 subtraction amplifier circuit, 15 2nd AD converter circuit, 16 2nd DA converter circuit, 17 2nd amplifier circuit, 18 2nd subtraction circuit, 19 3rd amplifier circuit, 100 operational amplifier, 20 3rd AD conversion circuit, C1, C2 capacitor, SW1, SW2, SW11-SW13 switch.

Claims (4)

An analog-digital converter that converts an input analog signal into a digital value by dividing it into multiple times,
A plurality of stages for converting an input analog signal into a digital value of a predetermined number of bits;
The first stage of the plurality of stages is a stage that amplifies an analog signal input to the stage by a single amplifying element,
The amplifying element samples and holds an analog signal input to the own stage, and subtracts and amplifies a signal obtained by converting a digital value converted by the own stage into an analog value from the held analog signal. A subtraction amplification circuit,
One or more of the plurality of stages is a cyclic type in which an analog signal input to the own stage is amplified by a plurality of amplification elements , and an output analog signal of the own stage is fed back to the input of the own stage. It is a stage,
One of the plurality of amplifying elements is a sample-and-hold circuit that samples and holds an analog signal input to the own stage, or an analog signal input to the own stage is sampled at a predetermined amplification factor. An amplifier circuit for amplifying,
The other amplifying elements of the plurality of amplifying elements subtract and amplify a signal obtained by converting a digital value converted at its own stage into an analog value from an analog signal output from the sample hold circuit or the amplifying circuit. An analog-digital converter characterized by being a two-subtraction amplifier circuit. 2. The analog-digital signal according to claim 1, wherein the first subtracting amplifier circuit directly samples the analog signal in synchronization with a timing of sampling the analog signal input to the stage for digital conversion. Converter . The first subtracting amplifier circuit, after sample an analog signal the input, until conversion to an analog value of the digital value converted by at least the self stage is determined, or claim 1, characterized in that the hold 2. The analog-digital converter according to 2 . The first subtracting amplifier circuit is longer than the auto-zero period, analog-to-digital converter according to any one of claims 1 to 3, characterized by amplification.

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