JP4097614B2 - Analog to digital converter - Google Patents

Description

  The present invention relates to an analog-digital converter. The present invention particularly relates to an analog-to-digital converter that has a plurality of stages and converts an analog signal into a digital signal by dividing it into a plurality of times.

In recent years, various additional functions such as an image photographing function, an image reproducing function, a moving image photographing function, and a moving image reproducing function have been installed in portable devices such as mobile phones. Accordingly, there is an increasing demand for miniaturization and power saving of analog-digital converters (hereinafter referred to as “AD converters”). As a form of such an AD converter, a cyclic AD converter configured in a circulation type is known (see, for example, Patent Document 1). Patent Document 1 discloses an AD converter having two stages including a cyclic conversion portion.
JP-A-4-26229

  In the first stage of the AD converter shown in FIG. 1 of Patent Document 1, a sample and hold circuit S / H1 is provided in parallel with a system comprising a parallel A / D converter AD1 and a D / A converter DA1. Is provided. The input analog signal of this circuit is held for a predetermined period by this sample and hold circuit S / H1.

  However, since an operational amplifier is included in the constituent elements of the sample-and-hold circuit, the output voltage range of the sample-and-hold circuit tends to narrow when the voltage is low. There is a problem that characteristic degradation such as distortion due to narrowing of the output voltage range of the sample-and-hold circuit becomes large at low voltage, and the characteristics of the entire AD converter deteriorate. On the other hand, if the sample-and-hold circuit is removed, the timing is shifted, and there is a problem that an unauthorized period in which neither autozero nor amplification is generated occurs in the amplifier circuit after subtraction. Here, the auto-zero is a period in which the input is sampled and no signal is output.

  The present invention has been made in view of such a situation, and an object thereof is to reduce a useless period during which auto-zero or amplification is not performed in an analog-digital converter.

  One embodiment of the present invention is an analog-digital converter. This analog-to-digital converter is an analog-to-digital converter that converts an input analog signal into a digital signal divided into a plurality of times by a plurality of stages, and each stage has an analog signal input to itself and a predetermined reference voltage. And an analog-to-digital conversion circuit for converting the digital signal into a digital value having a predetermined number of bits, and the timing of input of the analog signal to the analog-to-digital conversion circuit and the input timing of the predetermined reference voltage are first. It is set for each stage.

  According to this aspect, by setting the operation timing of the AD conversion circuit for each stage, it is possible to give a degree of freedom to the setting of the sample timing of an element such as an amplification circuit that amplifies an analog signal input to the AD conversion circuit. Can do. That is, the AD converter circuit and the amplifier circuit sample the input at the end of the auto-zero period. In order to synchronize the sampling point of the input signal in both circuits, if both circuits sample the input signal at substantially the same timing, the setting of the auto-zero period and the operation period of both circuits can be restricted, and there is a wasteful period. May occur. Even if the AD converter circuit samples the reference voltage and an input signal is input during the comparison operation period, the same output digital value as in the opposite case is obtained. Therefore, the amplifier circuit is substantially the same as the AD converter circuit. Thus, the restriction that the input signal is sampled at the same timing is released. Accordingly, it is possible to set an operation timing at which no unnecessary period occurs in the element. It is also possible to control them with a simple control signal.

  The AD converter circuit samples the analog signal at the end of the non-operation period and inputs a predetermined reference voltage during the comparison operation period or compares the sample by sampling the predetermined reference voltage at the end of the non-operation period. The analog signal may be input during the operation period or may be different depending on the configuration of each stage. By setting the operation timing of the AD conversion circuit according to the installation status of the amplification circuit of each stage, it is possible to set an operation timing that does not cause a useless period for the amplification element. The “non-operation period” includes an auto-zero period.

  Another aspect of the present invention is also an analog-digital converter. This analog-to-digital converter is an analog-to-digital converter that converts an input analog signal into a digital signal in a plurality of stages by a plurality of stages, and a first type stage that amplifies by one amplification element and two amplifications Each having at least one second type stage to be amplified by the element, and the AD converter circuit of the first type stage samples a predetermined reference voltage and outputs an analog signal to its own stage during the comparison operation period Is input, the AD converter circuit of the second type stage samples the analog signal input to its own stage, and a predetermined reference voltage is input during the comparison operation period.

  Yet another embodiment of the present invention is also an analog-digital converter. This analog-to-digital converter is an analog-to-digital converter that converts an input analog signal into a digital signal in multiple stages by multiple stages, and compares the analog signal input to its own stage with a predetermined reference voltage An AD conversion circuit that converts the digital signal to a digital value having a predetermined number of bits, and a subtraction that samples the analog signal, subtracts the analog signal corresponding to the converted digital value of the AD conversion circuit, and amplifies the analog signal at a predetermined amplification factor A first type stage including an amplifier circuit; an analog-to-digital conversion circuit that compares an analog signal input to its own stage with a predetermined reference voltage and converts the analog signal to a digital value of a predetermined number of bits; and the analog signal And a first amplifier circuit that amplifies or holds the signal at a predetermined amplification factor and the output analog signal. Each has at least one second type stage including a subtracting circuit that subtracts an analog signal corresponding to the converted digital value of the circuit and a second amplifier circuit that amplifies the output analog signal at a predetermined amplification factor. The AD converter circuit of the first type stage samples a predetermined reference voltage, and an analog signal is input to the own stage during the comparison operation period. The AD converter circuit of the second type stage It is preferable that the analog signal input to the stage is sampled and a predetermined reference voltage is input during the comparison operation period.

  Conventionally, in the stage of one amplifying element, the analog conversion signal and the amplifying element sampled an analog signal input at substantially the same timing, so the sampling timing of the amplifying element is accelerated, and immediately It was impossible to amplify, and a wasteful period occurred. In this regard, by adjusting the operation timing of the AD converter circuit of the first type stage, it is possible to prevent occurrence of useless periods during which auto zero or amplification is not performed in the constituent elements of the first type stage.

  Of the plurality of stages, the AD converter circuit of the first stage preferably samples a predetermined reference voltage and inputs an analog signal to its own stage during the comparison operation period. According to this, the first stage can be constituted by the first type stage. Therefore, the amplifier circuit provided in parallel with the AD converter circuit can be removed, and characteristic deterioration due to the output voltage range of the amplifier circuit can be prevented. In the first stage, since the largest signal is inputted, this characteristic deterioration is most likely to occur. However, if the first stage is used, it can be prevented.

  Of the plurality of stages, an output analog signal of the own stage may include a stage that feeds back to an input of the own stage. According to this, one stage can be used a plurality of times, and the circuit area can be reduced.

  Note that any combination of the above-described constituent elements, and those in which the constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, in the analog-digital converter, it is possible to reduce a useless period during which auto-zero or amplification is not performed.

  In a pipeline type or cyclic type AD converter that divides an input analog signal into a plurality of times and converts it into a digital signal, each stage constituting it performs one-step amplification or two-step amplification. In the following embodiments, an example of an AD converter in which one-step amplification and two-step amplification are mixed will be described. First, the basic configuration and basic operation of the 1-step amplification and 2-step amplification of the present invention will be described as the premise.

  FIG. 1 shows a basic configuration of one-step amplification. FIG. 1 shows one stage constituting the AD converter. The analog signal Vin input to this stage is sampled by the subtraction amplification circuit 16. The AD conversion circuit 12 converts the analog signal Vin into a digital value with a predetermined resolution. The AD conversion circuit 12 is a flash type including a plurality of comparators. A reference voltage for each voltage corresponding to LSB (Least Significant Bit) is supplied to the plurality of comparators. Each comparator compares the reference voltage with the sampled analog signal and outputs a Hi / Lo signal.

  The DA conversion circuit 13 converts the output of the comparator of the AD conversion circuit 12 into an analog signal. The subtraction amplification circuit 16 subtracts the output analog signal of the DA conversion circuit 13 from the sampled analog signal Vin, and amplifies it with a predetermined amplification factor. When the subtracting amplifier circuit 16 is composed of a switched capacitor operational amplifier, the analog signal Vin is sampled by a capacitor connected to the input terminal of the operational amplifier. The output analog signal of the subtraction amplification circuit 16 becomes the output analog signal Vout of this stage.

  Next, the operation timing of this stage will be described. FIG. 2 is a time chart showing an operation example of the circuit shown in FIG. 1 according to the present invention. In FIG. 2, the subtraction amplification circuit 16 and the AD conversion circuit 12 sample an input signal at a timing when the auto zero period is switched to the amplifier period. The subtraction amplification circuit 16 performs an auto-zero operation during the Hi period of the clock signal CLK, and performs subtraction amplification during the Lo period. The analog signal Vin is input during the Hi period, and the analog signal Vin is sampled at the falling edge from Hi to Lo. In the Lo period, the conversion confirmation data of the DA conversion circuit 13 is input.

  The AD conversion circuit 12 performs a comparison operation during the Hi period of the clock signal CLK and outputs a comparison result, and performs an auto-zero operation during the Lo period. A reference voltage is input to each comparator in the AD conversion circuit 12 during the Lo period, and the reference voltage is sampled at the rising edge from Lo to Hi. The analog signal Vin is input during the Hi period.

  The DA conversion circuit 13 is indefinite during the Hi period of the clock signal CLK, and holds the conversion confirmation data during the Lo period. The output of the AD conversion circuit 12 at the falling edge from Hi to Lo is held during the Lo period.

  Next, another operation timing of this stage will be described. FIG. 3 is a time chart showing an example of comparison operation of the circuit shown in FIG. In FIG. 3, this comparison operation example requires two clock signals CLK. The second clock signal CLK2 has a frequency twice that of the first clock signal CLK1.

  The subtraction amplifier circuit 16 performs subtraction amplification during the Lo period of the first clock signal CLK1, and performs auto-zero operation during the Hi period of the second clock signal CLK2 following that period. The subtracting amplifier circuit 16 samples the analog signal Vin at the falling edge of the second clock signal CLK2 from Hi to Lo during the Hi period of the first clock signal CLK1. Conversion confirmation data of the DA conversion circuit 13 is input during the subtraction amplification period, and an analog signal Vin is input during the auto-zero period. The Lo period of the second clock signal CLK2 in the Hi period of the first clock signal CLK1 is a useless period t in which neither auto-zero operation nor subtraction amplification is performed.

  The AD conversion circuit 12 performs an auto-zero operation during the Lo period of the first clock signal CLK1 and the Hi period of the second clock signal CLK2 following that period, and performs the comparison operation during the Lo period of the second clock signal CLK2 following that period. And output the comparison result. The AD conversion circuit 12 samples the analog signal Vin at the same timing as the subtraction amplifier circuit 16 samples the analog signal Vin. During the auto-zero period, the analog signal Vin is input to each comparator in the AD conversion circuit 12. A predetermined reference voltage is input during the comparison operation period.

  The DA conversion circuit 13 is indefinite during the Hi period of the first clock signal CLK1, and holds the conversion confirmation data during the Lo period. The output of the comparison result of the AD conversion circuit 12 is determined at the falling edge of the first clock signal CLK1 from Hi to Lo, and the determined data is held in the Lo period.

  Thus, in the comparison operation example, a useless period t in which neither the auto-zero operation nor the subtraction amplification is performed occurs in the subtraction amplification circuit 16. This is because the AD conversion circuit 12 and the subtraction amplification circuit 16 sample the analog signal Vin at the same timing. That is, after sampling the analog signal Vin at the same time, the AD conversion circuit 12 can immediately start the comparison operation with the reference voltage, whereas the subtraction amplification circuit 16 determines the conversion data by the DA conversion circuit 13. The subtraction amplification cannot be performed until the process is completed. Therefore, in the comparative operation example, the AD conversion circuit 12 and the subtraction amplification circuit 16 must be controlled by the second clock signal CLK2 that is earlier than the clock signal CLK used at the operation timing of FIG.

  On the other hand, in the operation example of the present invention, the comparator of the AD conversion circuit 12 samples the reference voltage and inputs the analog signal Vin during the comparison operation period. As a result, the subtracting amplifier circuit 16 does not need to rush the sample timing of the analog signal Vin, and can take a longer auto-zero period than the comparative operation example. At the same time, the comparison period of the AD conversion circuit 12 can be longer than that of the comparison operation example. Therefore, an early timing signal such as the second clock signal CLK2 in the comparative operation example is not necessary.

  FIG. 4 shows a basic configuration of two-step amplification. FIG. 4 shows one stage constituting the AD converter. The analog signal Vin input to this stage is sampled by the first amplifier circuit 11 and the AD conversion circuit 12. The first amplifier circuit 11 amplifies the sampled analog signal Vin with a predetermined amplification factor and outputs the amplified signal to the subtraction circuit 14 or the subtraction amplifier circuit 16. Alternatively, the sampled analog signal Vin is held for a predetermined period and output to the subtraction circuit 14 or the subtraction amplification circuit 16.

  The AD conversion circuit 12 converts the sampled analog signal Vin into a digital value with a predetermined resolution. The DA conversion circuit 13 converts the output of the AD conversion circuit 12 into an analog signal. At that time, the output of the AD conversion circuit 12 is amplified and converted into an analog signal according to the amplification factor of the first amplifier circuit 11. This amplification can be performed by adjusting the ratio between the reference voltage range supplied to the AD conversion circuit 12 and the reference voltage range supplied to the DA conversion circuit 13. Further, when the DA conversion circuit 13 is configured as a capacitor array type, it can also be performed by adjusting the number of capacitors.

  The subtraction circuit 14 subtracts the output analog signal of the DA conversion circuit 13 from the output analog signal of the first amplifier circuit 11. The second amplifier circuit 15 samples the output analog signal of the subtractor circuit 14 and amplifies it with a predetermined amplification factor. The output analog signal of the second amplifier circuit 15 becomes the output analog signal Vout of this stage. When the subtraction amplification circuit 16 is used in place of the subtraction circuit 14 and the second amplification circuit 15, the subtraction amplification circuit 16 samples the output analog signal of the first amplification circuit 11 and subtracts and amplifies it with a predetermined amplification factor. .

  Next, the operation timing of this stage will be described. FIG. 5 is a time chart showing an operation example of the circuit shown in FIG. In FIG. 5, the first amplifier circuit 11 amplifies the analog signal Vin sampled during the Hi period of the clock signal CLK, and performs an auto-zero operation during the Lo period. The analog signal Vin is input during the Lo period, and the analog signal Vin is sampled at the falling edge from Lo to Hi. A predetermined reference voltage is input during the Hi period.

  The AD conversion circuit 12 performs a comparison operation during the Hi period of the clock signal CLK and outputs a comparison result, and performs an auto-zero operation during the Lo period. The analog signal Vin is input to each comparator in the AD conversion circuit 12 during the Lo period, and the analog signal Vin is sampled at the falling edge from Lo to Hi. A predetermined reference voltage is input during the Hi period.

  The DA conversion circuit 13 is indefinite during the Hi period of the clock signal CLK, and holds the conversion confirmation data during the Lo period. The output of the AD conversion circuit 12 at the falling edge from Hi to Lo is held during the Lo period.

  The second amplifier circuit 15 performs an auto-zero operation during the Hi period of the clock signal CLK and performs amplification during the Lo period. At the falling edge of the clock signal CLK from Hi to Lo, the difference signal between the first amplifier circuit 11 and the DA converter circuit 13 is sampled, and a predetermined reference voltage is input during the Lo period. When the subtraction amplifier circuit 16 is used, the subtraction amplifier circuit 16 performs an auto-zero operation during the Hi period of the clock signal CLK and performs subtraction amplification during the Lo period. The output analog signal of the first amplifier circuit 11 is input during the Hi period, and the output analog signal is sampled at the falling edge from Hi to Lo. In the Lo period, the conversion confirmation data of the DA conversion circuit 13 is input.

  As described above, in the two-step amplification, the first amplifier circuit 11 and the AD conversion circuit 12 simultaneously sample the analog signal Vin, and the AD conversion circuit 12 performs a conversion operation in comparison with the analog signal Vin. The first amplifier circuit 11 holds or amplifies the analog signal Vin. Therefore, the second amplifier circuit 15 may sample the difference signal between the first amplifier circuit 11 and the DA converter circuit 13 after the conversion data of the DA converter circuit 13 is determined, and the useless period t does not occur. Further, during the conversion operation period of the AD conversion circuit 12, the first amplification circuit 11 amplifies the analog signal Vin, whereby the amplification factor of the second amplification circuit 15 can be lowered, and the second amplification circuit 15 is speeded up. be able to.

(First embodiment)
Next, the first embodiment will be described. The present embodiment is an example of a pipelined AD converter having four stages in which 4 bits are converted by the AD converter circuit of the first stage and 2 bits are converted by the AD converter circuits of the second to fourth stages. . The first stage has a one-step amplification, and the second and third stages have a two-step amplification.

  FIG. 6 shows the configuration of the AD converter in the first embodiment. In this AD converter, the input analog signal Vin is input to the first subtraction amplification circuit 26 and the first AD conversion circuit 22. The first AD conversion circuit 22 is of a flash type, and its resolution, that is, the number of conversion bits is 4 bits. The first AD conversion circuit 22 converts the input analog signal Vin into a digital value and takes out the upper 4 bits (D9 to D6). The first DA conversion circuit 23 converts the digital value converted by the first AD conversion circuit 22 into an analog value. The first subtraction amplification circuit 26 subtracts the output analog signal of the first DA conversion circuit 23 from the sampled input analog signal Vin, and amplifies it by a factor of two.

  The output analog signal of the first subtraction amplification circuit 26 is input to the third amplification circuit 27 and the second AD conversion circuit 28. The third amplifier circuit 27 and the second AD converter circuit 28 sample at the same timing. The third amplifier circuit 27 samples the input analog signal, amplifies it twice, and outputs it to the second subtraction circuit 30. The second AD conversion circuit 28 samples the input analog signal, converts it to a digital value, and takes out 5 and 6 bits (D5 and D4) from the higher order.

  Since the number of conversion bits in the second stage is 2 bits, the output of the first stage must be amplified by a factor of 4 (square of 2). In the first stage, the first subtraction amplification circuit 26 amplifies the signal twice. In addition, if the reference voltage of the comparator in the second AD converter circuit 28 is set to ½ that of the first AD converter circuit 22, the above four times can be realized.

  The second DA conversion circuit 29 converts the digital value converted by the second AD conversion circuit 28 into an analog value. At this time, the output of the second AD conversion circuit 28 is converted to an analog signal while being doubled. The second subtraction circuit 30 subtracts the output analog signal of the second DA conversion circuit 29 from the output analog signal of the third amplification circuit 27. The fourth amplification circuit 31 amplifies the output analog signal of the second subtraction circuit 30 by a factor of two. Instead of the second subtraction circuit 30 and the fourth amplification circuit 31, an integrated second subtraction amplification circuit 32 may be used. According to this, the circuit area can be reduced.

  The output analog signal of the fourth amplifier circuit 31 is input to the fifth amplifier circuit 33 and the third AD conversion circuit 34. The fifth amplifier circuit 33 and the third AD converter circuit 34 sample at the same timing. The fifth amplifier circuit 33 samples the input analog signal, amplifies it twice, and outputs it to the third subtractor circuit 36. The third AD conversion circuit 34 samples the input analog signal, converts it to a digital value, and takes out 7 to 8 bits (D3 and D2) from the higher order.

  The third DA conversion circuit 35 converts the digital value converted by the third AD conversion circuit 34 into an analog value. At this time, the output of the third AD conversion circuit 34 is converted to an analog signal while being amplified twice. The third subtraction circuit 36 subtracts the output analog signal of the third DA conversion circuit 35 from the output analog signal of the fifth amplification circuit 33. The sixth amplification circuit 37 amplifies the output analog signal of the third subtraction circuit 36 by a factor of two. Instead of the third subtraction circuit 36 and the sixth amplification circuit 37, an integrated third subtraction amplification circuit 38 may be used.

  The output analog signal of the sixth amplifier circuit 37 is input to the fourth AD conversion circuit 39. The fourth AD conversion circuit 39 samples the input analog signal, converts it to a digital value, and takes out 9,10 bits (D1 to D0) from the higher order. In this way, a 10-bit digital value is obtained in four stages.

  Next, the operation timing of the AD converter in the first embodiment will be described. FIG. 7 is a time chart illustrating an operation process of the AD converter according to the first embodiment. First, the operation timing of the first stage will be described. The first subtracting amplifier circuit 26 samples the input analog signal Vin at the falling edge of the clock signal CLK from Hi to Lo. The first subtraction amplification circuit 26 performs an auto-zero operation during the Hi period of the clock signal CLK, and subtracts the output analog signal of the first DA conversion circuit 23 from the input analog signal Vin sampled during the Lo period to amplify it. The second AD conversion circuit 28 samples a predetermined reference voltage at the rising edge of the clock signal CLK from Lo to Hi. The second AD conversion circuit 28 performs a comparison operation during the Hi period of the clock signal CLK, and performs an auto-zero operation during the Lo period. The input analog signal Vin is input to the falling edge of the clock signal CLK from Hi to Lo. The first DA conversion circuit 23 holds the conversion confirmation data during the Lo period of the clock signal CLK, and becomes indefinite during the Hi period.

  Next, the operation timing of the second stage will be described. The third amplifier circuit 27 and the second AD converter circuit 28 sample the output analog signal of the first subtracting amplifier circuit 26 at the rising edge of the clock signal CLK from Lo to Hi. The third amplifier circuit 27 amplifies the analog signal sampled during the Hi period of the clock signal CLK, and performs an auto-zero operation during the Lo period. The second AD conversion circuit 28 performs a comparison operation during the Hi period of the clock signal CLK, and performs an auto-zero operation during the Lo period. The second DA conversion circuit 29 holds the conversion confirmation data during the Lo period of the clock signal CLK, and becomes indefinite during the Hi period.

  The fourth amplifier circuit 31 samples a difference signal between the output analog signal of the third amplifier circuit 27 and the output analog signal of the second DA converter circuit 29 at the falling edge of the clock signal CLK from Hi to Lo. The fourth amplifier circuit 31 amplifies the analog signal sampled during the Lo period of the clock signal CLK, and performs an auto-zero operation during the Hi period. When the second subtracting amplifier circuit 32 is used, the second subtracting amplifier circuit 32 samples the output analog signal of the third amplifier circuit 27 at the falling edge of the clock signal CLK from Hi to Lo. The second subtracting amplifier circuit 32 subtracts and amplifies the output analog signal of the second DA converter circuit 29 from the analog signal sampled during the Lo period of the clock signal CLK, and performs an auto-zero operation during the Hi period.

  Next, the operation timing of the third stage will be described. The fifth amplifier circuit 33 and the third AD converter circuit 34 sample the output analog signal of the fourth amplifier circuit 31 at the rising edge of the clock signal CLK from Lo to Hi. The fifth amplifier circuit 33 amplifies the analog signal sampled during the Hi period of the clock signal CLK, and performs an auto-zero operation during the Lo period. The third AD conversion circuit 34 performs a comparison operation during the Hi period of the clock signal CLK, and performs an auto-zero operation during the Lo period. The third DA conversion circuit 35 holds the conversion confirmation data during the Lo period of the clock signal CLK, and becomes indefinite during the Hi period.

  The sixth amplifier circuit 37 samples the difference signal between the output analog signal of the fifth amplifier circuit 33 and the output analog signal of the third DA converter circuit 35 at the falling edge of the clock signal CLK from Hi to Lo. The sixth amplifier circuit 37 amplifies the analog signal sampled during the Lo period of the clock signal CLK, and performs auto-zero operation during the Hi period. When the third subtracting amplifier circuit 38 is used, the third subtracting amplifier circuit 38 samples the output analog signal of the fifth amplifier circuit 33 at the falling edge of the clock signal CLK from Hi to Lo. The third subtraction amplification circuit 38 subtracts and amplifies the output analog signal of the third DA conversion circuit 35 from the sampled analog signal during the Lo period of the clock signal CLK, and performs auto-zero operation during the Hi period.

  The fourth AD converter circuit 39 of the fourth stage samples the output analog signal of the sixth amplifier circuit 37 at the rising edge of the clock signal CLK from Lo to Hi. The fourth AD conversion circuit 39 performs a comparison operation during the Hi period of the clock signal CLK, and performs an auto-zero operation during the Lo period. As described above, the four AD conversion circuits 22, 28, 34, and 39 perform the conversion operation of the different input analog signals Vin with the same clock, thereby realizing the pipeline processing.

  Next, another operation timing of the AD converter according to the first embodiment will be described. FIG. 8 is a time chart illustrating an operation process in a comparative example of the AD converter according to the first embodiment. Since the timing after the second stage is the same as the timing of FIG. 7, only the first stage will be described. In the comparative example, two clock signals CLK are required. The frequency of the second clock signal CLK2 is twice the frequency of the first clock signal CLK1.

  The first subtraction amplifier circuit 26 samples the input analog signal Vin at the falling edge from Hi to Lo every other cycle of the second clock signal CLK2. The first subtraction amplification circuit 26 subtracts the output analog signal of the first DA conversion circuit 23 from the sampled input analog signal Vin and amplifies it during the Lo period of the first clock signal CLK1. The auto-zero operation is performed during the Hi period of the second clock signal CLK2 in the Hi period of the first clock signal CLK1. The Lo period of the second clock signal CLK2 in the Hi period of the first clock signal CLK1 is a useless period t in which neither autozero nor amplification is performed.

  The first AD conversion circuit 22 samples the input analog signal Vin at the same timing as the timing at which the first subtraction amplification circuit 26 samples the input analog signal Vin. The first AD converter circuit 22 performs an auto-zero operation during the Lo period of the first clock signal CLK1 and the Hi period of the second clock signal CLK2 following that period, and performs the comparison operation during the Lo period of the second clock signal CLK2 following that period. And output the comparison result. The first DA conversion circuit 23 holds the conversion confirmation data during the Lo period of the first clock signal CLK1, and becomes indefinite during the Hi period.

  As described above, in the comparative example, a useless period t in which neither auto-zero nor subtraction amplification is performed occurs in the first subtraction amplification circuit 26. This is because the first AD conversion circuit 22 and the first subtraction amplification circuit 26 sample the analog signal Vin at the same timing. That is, after sampling the analog signal Vin at the same time, the first AD converter circuit 22 can immediately start the comparison operation with the reference voltage, whereas the first subtracting amplifier circuit 26 is controlled by the first DA converter circuit 23. Subtraction amplification cannot be performed until conversion data is determined. Therefore, in the comparative example, the first AD converter circuit 22 and the first subtraction amplifier circuit 26 must be controlled by the second clock signal CLK2 earlier than the clock signal CLK used at the operation timing of FIG.

  On the other hand, in the operation example of the present invention shown in FIG. 7, the first AD converter circuit 22 samples the reference voltage and inputs the analog signal Vin during the comparison operation period. As a result, the first subtracting amplifier circuit 26 does not need to rush the sample timing of the analog signal Vin, and can take a longer auto-zero period than the comparative example. Therefore, an early timing signal such as the second clock signal CLK2 in the comparative operation example is not necessary.

  As described above, according to this embodiment, it is possible to operate the pipeline AD converter in which the one-step amplification stage and the two-step amplification stage are mixed without generating a useless period t. Further, it is not necessary to generate a special second clock signal CLK for controlling the one-step amplification stage, and all stages can be controlled with the common clock signal CLK. Further, by configuring the first stage with one-step amplification, the characteristics of the entire AD converter can be improved. That is, the signal input to the first stage is the largest signal because it is the signal before passing through the subtracting circuit. When an amplifier circuit is provided in parallel with the AD converter circuit as in the case of two-step amplification, there is a possibility that the characteristics are deteriorated depending on the output voltage range of the amplifier circuit. In particular, when the power supply voltage of the amplifier circuit decreases, the output voltage range becomes narrower and the tendency becomes stronger.

  Further, as described above, the two-step amplification can amplify the input signal in parallel with the AD conversion of the stage. Therefore, the amplification factor of the amplification circuit at the second step can be reduced, and the speed of the amplification circuit can be increased. Therefore, the frequency of the clock signal CLK itself can be increased. As described above, according to the present embodiment, it is possible to achieve both improvement in characteristics and high speed without generating a useless period t.

(Second Embodiment)
In the second embodiment, 4 bits are converted in a non-cyclic-type preceding stage by 1-step amplification, 2 bits are converted in 2-stage amplification by a cyclic-type subsequent stage, and the subsequent stage makes three rounds to make a total. It is an example of an AD converter that outputs 10 bits.

  FIG. 9 shows the configuration of the AD converter in the second embodiment. In this AD converter, first, the preceding stage will be described. The input analog signal Vin is input to the first AD conversion circuit 42 and the first subtraction amplification circuit 46. The first AD conversion circuit 42 is of a flash type, and its resolution, that is, the number of conversion bits is 4 bits. The first AD conversion circuit 42 samples the input analog signal Vin, converts it into a digital value, takes out the upper 4 bits (D9 to D6), and outputs them to an encoder (not shown) and the first DA conversion circuit 43. The first DA conversion circuit 43 converts the digital value converted by the first AD conversion circuit 42 into an analog value. The first subtraction amplification circuit 46 samples the input analog signal Vin, subtracts the output analog signal of the first DA conversion circuit 43 from the input analog signal Vin, and amplifies the input signal twice.

  Next, the latter stage will be described. The first switch SW1 and the second switch SW2 are switches that are alternately turned on and off. When the first switch SW1 is on and the second switch SW2 is off, an analog signal input from the first subtracting amplifier circuit 46 of the previous stage through the first switch SW1 is the third amplifier circuit 47 and the second AD converter. It is input to the circuit 48. The second AD conversion circuit 48 is also of a flash type, and its resolution, that is, the number of bits including one redundant bit is 3 bits. The reference voltage of the comparator in the second AD conversion circuit 48 is set to ½ of the first AD conversion circuit 42. The output analog signal of the second AD conversion circuit 48 and the first subtraction amplification circuit 46 is sampled and converted into a digital value, and the 5 and 6 bits (D5 and D4) are taken out from the higher order. Output to the circuit 49.

  The second DA conversion circuit 49 converts the digital value converted by the second AD conversion circuit 48 into an analog value. At that time, the digital value is amplified by a factor of 2 and converted to an analog value. The third amplifying circuit 47 samples the output analog signal of the first subtracting amplifying circuit 46, amplifies it twice, and outputs it to the second subtracting circuit 50. The second subtraction circuit 50 subtracts the output analog signal of the second DA conversion circuit 49 from the output analog signal of the third amplification circuit 47 and outputs the result to the fourth amplification circuit 51.

  The fourth amplification circuit 51 amplifies the output analog signal of the second subtraction circuit 50 by a factor of two. At this stage, the first switch SW1 is turned off and the second switch SW2 is turned on. The output analog signal of the fourth amplifier circuit 51 is fed back to the third amplifier circuit 47 and the second AD converter circuit 48 via the second switch SW2. The second subtracting circuit 50 and the fourth amplifying circuit 51 may use an integrated second subtracting amplifying circuit 52. Thereafter, the above-described processing is repeated, and the second DA converter circuit 49 extracts 7, 8 bits (D3, D2) from the higher order and 9,10 bits (D1, D0) from the upper order. In this way, a 10-bit digital value is obtained. The upper 5 to 10 bits are obtained by a cyclic subsequent stage.

  Next, the operation timing of the AD converter in the second embodiment will be described. FIG. 10 is a time chart illustrating an operation process of the AD converter according to the second embodiment of the present invention. Hereinafter, description will be made in order from the top of the figure. The three signal waveforms indicate the first clock signal CLK1, the second clock signal CLK2, and the switch signal CLKSW. The first clock signal CLK1 controls the operations of the first subtraction amplification circuit 46, the first AD conversion circuit 42, and the first DA conversion circuit 43. The second clock signal CLK2 controls the operations of the third amplifier circuit 47, the fourth amplifier circuit 51, the second AD converter circuit 48, and the second DA converter circuit 49. The switch signal CLKSW performs on / off control of the first switch SW1 and the second switch SW2.

  The frequency of the second clock signal CLK2 is three times the frequency of the first clock signal CLK1. The second clock signal CLK2 may be generated by multiplying the first clock signal CLK1 using a PLL or the like based on the first clock signal CLK1. After the rise of the second clock signal CLK2 is synchronized with the rise of the first clock signal CLK1, the second fall of the second clock signal CLK2 is synchronized with the next fall of the first clock signal CLK1, and the next second time. The rising edge is synchronized with the next rising edge of the first clock signal CLK1. Since the frequency of the second clock signal CLK2 is three times the frequency of the first clock signal CLK1, the conversion processing speed by the subsequent stage is also three times the conversion processing speed by the previous stage. Since the accuracy of analog processing such as subtraction and amplification in conversion processing with higher bits greatly affects the overall conversion accuracy, higher accuracy is required for the previous stage responsible for this. Therefore, in the configuration of the present embodiment, the conversion processing speed of the subsequent stage, which does not require processing accuracy as much as the previous stage, can be increased from the processing speed of the previous stage.

  The first subtraction amplifier circuit 46 samples the input analog signal Vin at the falling edge of the first clock signal CLK1. The first subtraction amplification circuit 46 subtracts the output analog signal of the first DA conversion circuit 43 from the sampled input analog signal Vin and amplifies it during the Lo period of the first clock signal CLK1. Auto zero operation is performed during the Hi period of the first clock signal CLK1. The first AD conversion circuit 42 samples a predetermined reference voltage at the rising edge of the first clock signal CLK1. The first AD conversion circuit 42 performs a conversion operation during the Hi period of the first clock signal CLK1 and outputs digital values D9 to D6, and performs an auto-zero operation during the Lo period. The first DA conversion circuit 13 holds the conversion confirmation data during the Lo period of the first clock signal CLK1, and becomes indefinite during the Hi period.

  The first switch SW1 is turned on when the switch signal CLKSW is Hi, and is turned off when the switch signal CLKSW is Lo. The second switch SW2 is turned on when the switch signal CLKSW is Lo, and is turned off when the switch signal CLKSW is Hi.

  The third amplifier circuit 47 and the second AD converter circuit 48 sample the input analog signal at the rising edge of the second clock signal CLK2. The third amplifier circuit 47 amplifies the analog signal sampled during the Hi period of the second clock signal CLK2, and performs an auto-zero operation during the Lo period. During the period in which the second AD conversion circuit 48 converts the least significant bit D1, 0, it is not amplified. The fourth amplifier circuit 51 samples the difference signal between the output analog signal of the third amplifier circuit 47 and the output analog signal of the second DA converter circuit 49 at the falling edge of the second clock signal CLK2. The fourth amplifier circuit 51 amplifies the analog signal sampled during the Lo period of the second clock signal CLK2, and performs an auto-zero operation during the Hi period. When the second subtracting amplifier circuit 52 is used instead of the fourth amplifier circuit 51, the second subtracting amplifier circuit 52 samples the output analog signal of the third amplifier circuit 47 at the falling edge of the second clock signal CLK2. . The second subtraction amplification circuit 52 subtracts and amplifies the output analog signal of the second DA conversion circuit 49 from the sampled analog signal during the Lo period of the second clock signal CLK2. Auto zero operation is performed during the Hi period. No amplification is performed in the next half clock period after the second AD conversion circuit 48 converts D1 and D0.

  The second AD conversion circuit 48 samples the input analog signal at the rising edge of the second clock signal CLK2. The second AD conversion circuit 48 performs a conversion operation during the Hi period of the second clock signal CLK2, outputs 3 bits including redundant bits, and performs an auto-zero operation during the Lo period. The second DA conversion circuit 49 holds the conversion confirmation data during the Lo period of the second clock signal CLK2, and becomes indefinite during the Hi period. When the output of the second AD conversion circuit 48 is D1, D0, the conversion operation is not performed.

  The auto-zero period of the first subtracting amplifier circuit 46, the third amplifier circuit 47, the fourth amplifier circuit 51, the first AD converter circuit 42, and the second AD converter circuit 48 is a state in which an input signal is being sampled. As shown in the figure, while the second AD conversion circuit 48 converts D5, D4 and D3, D2, the first AD conversion circuit 42 simultaneously converts the next input analog signal Vin. By such pipeline processing, the AD converter as a whole can output a 10-bit digital value once per cycle with reference to the first clock signal CLK1.

  Next, another operation timing of the AD converter according to the second embodiment will be described. FIG. 11 is a time chart illustrating an operation process in a comparative example of the AD converter according to the second embodiment. Since the timing of the subsequent stage is the same as the timing of FIG. 10, only the preceding stage will be described. In the comparative example, the third clock signal CLK3 is further required. The frequency of the third clock signal CLK3 is twice the frequency of the first clock signal CLK1.

  The first subtracting amplifier circuit 46 samples the input analog signal Vin at every other falling edge of the third clock signal CLK3. The first subtraction amplification circuit 46 subtracts the output analog signal of the first DA conversion circuit 43 from the sampled input analog signal Vin during the Lo period of the first clock signal CLK1, and amplifies it. The auto-zero operation is performed during the Hi period of the third clock signal CLK3 in the Hi period of the first clock signal CLK1. The Lo period of the third clock signal CLK3 in the Hi period of the first clock signal CLK1 is a useless period t in which neither autozero nor amplification is performed.

  The first AD conversion circuit 42 samples the input analog signal Vin at the same timing as the timing at which the first subtraction amplification circuit 46 samples the input analog signal Vin. The first AD conversion circuit 42 performs an auto-zero operation during the Lo period of the first clock signal CLK1 and the Hi period of the third clock signal CLK3 following that period, and performs the comparison operation during the Lo period of the third clock signal CLK3 following that period. And output the comparison result. The first DA conversion circuit 43 holds the conversion confirmation data during the Lo period of the first clock signal CLK1, and becomes indefinite during the Hi period.

  As described above, in the comparison operation example, a useless period t in which neither autozero nor subtraction amplification is performed occurs in the first subtraction amplification circuit 46. This is because the first AD conversion circuit 42 and the first subtraction amplification circuit 46 sample the analog signal Vin at the same timing. That is, after sampling the analog signal Vin at the same time, the first AD converter circuit 42 can immediately start the comparison operation with the reference voltage, whereas the first subtracting amplifier circuit 46 is controlled by the first DA converter circuit 43. Subtraction amplification cannot be performed until conversion data is determined. Therefore, in the comparative example, the first AD conversion circuit 42 and the first subtraction amplification circuit 46 must be controlled by the third clock signal CLK3 that is earlier than the first clock signal CLK used at the operation timing of FIG.

  On the other hand, in the operation example of the present invention shown in FIG. 10, the first AD conversion circuit 42 samples the reference voltage and inputs the analog signal Vin during the comparison operation period. As a result, the first subtracting amplifier circuit 46 does not need to rush the sample timing of the analog signal Vin, and can take a longer auto-zero period than the comparative example. Therefore, an early timing signal such as the third clock signal CLK3 in the comparative operation example is not necessary.

  As described above, according to the present embodiment, the AD converter in which the acyclic type one-step amplification stage and the cyclic type two-step amplification stage are mixed is operated without generating a useless period t. Can be made. In addition, the acyclic stage can be controlled by one first clock signal CLK in one step amplification. Further, by configuring the first stage with one-step amplification, the characteristics of the entire AD converter can be improved. That is, the signal input to the first stage is the largest signal because it is the signal before passing through the subtracting circuit. When an amplifier circuit is provided in parallel with the AD converter circuit as in the case of two-step amplification, there is a possibility that the characteristics are deteriorated depending on the output voltage range of the amplifier circuit. In particular, when the power supply voltage of the amplifier circuit decreases, the output voltage range becomes narrower and the tendency becomes stronger.

  Further, as described above, the two-step amplification can amplify the input signal in parallel with the AD conversion of the stage. Therefore, the amplification factor of the amplification circuit at the second step can be reduced, and the speed of the amplification circuit can be increased. Therefore, the frequency of the first clock signal CLK1 and the second clock signal CLK2 can be increased. As described above, according to the present embodiment, it is possible to achieve both improvement in characteristics and high speed without generating a useless period t.

(Third embodiment)
In the third embodiment, a one-step amplification stage is further added to the AD converter of the second embodiment. Four bits are converted in the first stage of the one-step amplification, and the second stage of the one-step amplification. This is an example of an AD converter that outputs 2 bits in total and outputs 12 bits in total by converting 2 bits 3 times in a cyclic third stage by 2-step amplification.

  FIG. 12 shows the configuration of the AD converter in the third embodiment. The description after the second stage basically corresponds to the description of the second embodiment. However, the number of conversion bits in the second stage is different from that in the previous stage in the second embodiment from 4 bits to 2 bits. If the reference voltage of the second stage AD converter circuit and the reference voltage of the third stage AD converter circuit are set to be the same, the amplification factor of the second stage is quadrupled as shown in FIG. For the added first stage, the description of the preceding stage of the second embodiment is valid as it is. The operation timing is basically the same as that of the time chart shown in FIG. The first stage AD conversion circuit 62, DA conversion circuit 63, and subtraction amplification circuit 66 are controlled by the first clock signal CLK1. Each component of the second stage may be controlled by the first clock signal CLK1 or the second clock signal CLK2.

  As described above, according to the present embodiment, an AD converter in which two stages of one-step amplification and a cyclic stage are mixed in two-step amplification is operated without generating a useless period t. be able to. Further, by configuring the first stage with one-step amplification, it is possible to improve the characteristics of the entire AD converter. Further, as described above, the two-step amplification can speed up the entire AD converter. As described above, according to the present embodiment, it is possible to achieve both improvement in characteristics and high speed without generating a useless period t.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications can be made to combinations of each component and each processing process. Those skilled in the art will appreciate that such modifications are also within the scope of the present invention.

  The parameters such as the number of conversion bits of the AD conversion circuit and the distribution thereof, the amplification factor of the amplification circuit, and the like described in the above embodiment are merely examples, and other numerical values may be adopted for these parameters in the modification. Further, the number of stages of the entire AD converter, the number of stages of one-step amplification, the number of stages of two-step amplification, the number of cyclic stages, and the number of acyclic stages can be arbitrarily set.

It is a figure which shows the basic composition of 1 step amplification. 2 is a time chart showing an operation example of the circuit of the present invention according to the present invention. 2 is a time chart showing an example of comparison operation of the circuit shown in FIG. It is a figure which shows the basic composition of 2 step amplification. 5 is a time chart illustrating an operation example of the circuit illustrated in FIG. 4. It is a figure which shows the structure of the AD converter in 1st Embodiment. It is a time chart which shows the operation | movement process in this invention of the AD converter in 1st Embodiment. It is a time chart which shows the operation | movement process in the comparative example of the AD converter in 1st Embodiment. It is a figure which shows the structure of the AD converter in 2nd Embodiment. It is a time chart which shows the operation | movement process in this invention of the AD converter in 2nd Embodiment. It is a time chart which shows the operation | movement process in the comparative example of the AD converter in 2nd Embodiment. It is a figure which shows the structure of the AD converter in 3rd Embodiment.

Explanation of symbols

  22 1st AD conversion circuit, 23 1st DA conversion circuit, 26 1st subtraction amplification circuit, 27 3rd amplification circuit, 28 2nd AD conversion circuit, 29 2nd DA conversion circuit, 30 2nd subtraction circuit, 31 4th amplification circuit, 32 2nd subtraction amplifier circuit, 33 5th amplifier circuit, 34 3rd AD converter circuit, 35 3rd DA converter circuit, 36 3rd subtractor circuit, 37 6th amplifier circuit, 38 3rd subtractor amplifier circuit, 39 4th AD converter circuit.

Claims (5)

An analog-to-digital converter that converts an input analog signal into a digital signal divided into a plurality of times by a plurality of stages,
At least one of the plurality of stages is
A first AD conversion circuit that samples a predetermined reference voltage, compares the first analog signal input to its own stage with the reference voltage, and converts the reference voltage into a digital value having a predetermined number of bits;
A first DA conversion circuit for converting a digital signal output from the first AD conversion circuit into a first output analog signal;
A first subtraction amplification circuit that samples the first analog signal, subtracts the first output analog signal from the first analog signal, and amplifies the subtraction result at a predetermined amplification rate;
The sample operation in the first AD converter circuit and the sample operation in the first subtraction amplifier circuit are performed at different timings, and the first analog signal is supplied to the first AD converter circuit during the comparison operation period in the first AD converter circuit. Entered,
At least one other stage among the plurality of stages is
A first amplifying circuit that samples a second analog signal input to its own stage and amplifies or holds it at a predetermined gain;
A second AD conversion circuit that samples the second analog signal, compares the second analog signal with a predetermined reference voltage, and converts the second analog signal into a digital value having a predetermined number of bits;
A second DA conversion circuit for converting a digital signal output from the second AD conversion circuit into a second output analog signal;
A second subtracting amplifier circuit that samples a third analog signal output from the first amplifier circuit, subtracts the second output analog signal from the third analog signal, and amplifies the subtraction result at a predetermined amplification rate; or A subtracting circuit that subtracts the second output analog signal from the third analog signal; and a second amplifying circuit that samples the analog signal output from the subtracting circuit and amplifies the analog signal at a predetermined amplification rate.
The analog-digital converter, wherein the sampling operation in the first amplifier circuit and the sampling operation in the second AD converter circuit are performed at the same timing . The second AD converter circuit samples the second analog signal at the end of the non-operation period, and a predetermined reference voltage is input during the comparison operation period, and the first AD conversion circuit receives the end of the non-operation period. analog-to-digital converter according to claim 1, wherein the sample child a predetermined reference voltage to. The first AD converter circuit samples a predetermined reference voltage, and the first analog signal is input during a comparison operation period. The second AD conversion circuit samples the second analog signal, and performs a comparison operation period. The analog-digital converter according to claim 1 , wherein a predetermined reference voltage is input therein. Among the plurality of stages, AD conversion circuit of the first stage stage samples the predetermined reference voltage, one of claims 1 to 3, characterized in that said first analog signal during the comparison operation period is input An analog-digital converter described in 1. Wherein among the plurality of stages, the output analog signal of its own stage, analog-to-digital converter according to claim 1, characterized in that it comprises a stage which is fed back to the input of its own stage 4.

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