KR101662688B1 - Pipeline analog-digital converter - Google Patents

Abstract

A pipelined analog-to-digital converter according to an embodiment of the present invention includes first to Nth (N is an integer of 2 or more) analog-to-digital conversion stages connected in series, and a pipe for converting an analog input signal into a digital output signal A line analog-to-digital converter, wherein the first analog-to-digital conversion stage comprises an operational amplifier, first and second capacitors, a sample and hold amplifier (SHA) and a multiplier digital- The sampling circuit includes a non-inverting input terminal of the operational amplifier connected to the ground terminal during sampling of the analog input signal, and a non-inverting input terminal of the inverting input terminal of the operational amplifier, And the output terminal are directly connected, the operational amplifier can be reset.

Description

[0001] PIPELINE ANALOG-DIGITAL CONVERTER [0002]

The present invention relates to a pipelined analog-to-digital converter.

Analog-to-digital converters for converting analog signals to digital signals are being applied in various fields such as signal processing, wireless communication, and display. In particular, a pipelined analog-to-digital converter employing a pipeline structure has been proposed to realize a high resolution and an operation speed. A typical pipelined analog-to-digital converter can include a plurality of stages, a sample and hold amplifier (SHA) for sampling and holding analog input signals, and a plurality of stages. Each stage may include a Multiplying Digital-to-Analog Converter (MDAC) and a Flash Analog-Digital Converter (FADC).

Various methods have been proposed to reduce the power consumption and circuit area of pipelined analog-to-digital converters. For example, there has been proposed a method in which a first stage of a multi-flying digital-to-analog conversion circuit samples and inputs an analog input signal without a sample-and-hold circuit or switches a operational amplifier to an operational amplifier to turn off an operational amplifier during a sampling operation . However, when the sample-and-hold circuit is removed, errors occur in the sampling time of the multi-flying digital-to-analog conversion circuit and the flash digital-to-analog conversion circuit in the first stage of sampling the analog input signal, have. Further, when a switch is connected to the operational amplifier, there is a problem that a predetermined settling time is required until the operational amplifier operates after the switch is connected.

One of the technical problems to be solved by the technical idea of the present invention is to provide a sampling circuit having one operational amplifier and a plurality of capacitors to provide a sample and hold circuit and a first stage multi- And to provide a pipelined analog-to-digital converter with reduced performance and at the same time excellent performance.

A pipelined analog-to-digital converter according to an embodiment of the present invention includes first to Nth (N is an integer of 2 or more) analog-to-digital conversion stages connected in series, and a pipe for converting an analog input signal into a digital output signal A first analog-to-digital conversion stage comprises an operational amplifier, first and second capacitors, a sample and hold amplifier (SHA) and a multiplier digital-to-analog conversion circuit And a sampling circuit for providing a multiplying digital-to-analog converter (MDAC), wherein the sampling circuit connects a non-inverting input terminal of the operational amplifier to a ground terminal during sampling of the analog input signal, By directly connecting the inverting input terminal and the output terminal of the amplifier, the operational amplifier can be reset.

In some embodiments of the present invention, each of the second to Nth analog to digital conversion stages may include two or more multiplying digital-to-analog conversion circuits sharing one operational amplifier.

In some embodiments of the present invention, each of the first to Nth analog to digital conversion stages may include two or more Flash Analog-Digital Converters (FADCs) that share one comparator have.

In some embodiments of the present invention, the two or more flash analog-to-digital conversion circuits included in each of the first to Nth analog to digital conversion stages may share a voltage divider circuit for generating a predetermined reference voltage .

In some embodiments of the present invention, a digital error correction section for generating the digital output signal based on a digital signal output by the two or more flash analog-digital conversion circuits; As shown in FIG.

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In some embodiments of the present invention, the sampling circuit may sample the analog input signal by connecting the plurality of capacitors between an input signal terminal to which the analog input signal is transmitted and an inverting input terminal of the operational amplifier .

In some embodiments of the present invention, the sampling circuit may hold the sampled signal by connecting the plurality of capacitors in parallel between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier.

In some embodiments of the present invention, the sampling circuit includes a first capacitor of the plurality of capacitors connected between an inverting input terminal and an output terminal of the operational amplifier, and an input signal terminal to which a predetermined reference signal is transmitted, And a second capacitor of the plurality of capacitors is connected between the inverting input terminals of the amplifier to amplify the held signal.

A pipelined analog-to-digital converter according to an embodiment of the present invention includes first to Nth (N is an integer of 2 or more) stages connected in series with each other, The analog-to-digital converter of claim 1, wherein the first stage comprises a single operational amplifier and a sampling circuit for sampling, holding and amplifying the analog input signal, the first and second capacitors being implemented as first and second capacitors, The operational amplifier can be reset by connecting the noninverting input terminal of the operational amplifier to the ground terminal while sampling the analog input signal and directly connecting the inverting input terminal and the output terminal of the operational amplifier.

In some embodiments of the present invention, the sampling circuit may connect at least one of the first and second capacitors to at least one of the input terminals of the operational amplifier while sampling, holding, and amplifying the analog input signal.

In some embodiments of the present invention, the sampling circuit may include a flip-around sample and hold amplifier implemented with the one operational amplifier and the first and second capacitors.

In some embodiments of the present invention, the second through N stages may include two or more far-flying digital-to-analog conversion circuits sharing an operational amplifier.

In some embodiments of the present invention, each of the first through N stages may include two or more flash analog-to-digital conversion circuits sharing a single comparator.

A pipelined analog-to-digital converter according to an embodiment of the present invention has first through N stages connected in series with each other, the first stage receiving an analog input signal, the second through N stages A converter for receiving a residue analog signal from a previous stage and generating a plurality of digital signals; And a digital error correcting unit for correcting errors included in the plurality of digital signals to generate a digital output signal; Wherein the first stage includes a sample-and-hold circuit and a multi-flying digital-to-analog conversion circuit that constitute the input stage of the converter section share the operational amplifier and the first and second capacitors, Wherein at least one of the input terminals of the operational amplifier is coupled to at least one of the first and second capacitors while the sampling circuit is operating, The sampling circuit may reset the operational amplifier by connecting a noninverting input terminal of the operational amplifier to a ground terminal while sampling the analog input signal and directly connecting an inverting input terminal and an output terminal of the operational amplifier .

In some embodiments of the invention, the sampling circuit may reset the operational amplifier while sampling the analog input signal.

In some embodiments of the present invention, the sampling circuit may sequentially repeat the sampling operation for sampling the analog input signal, the holding operation for holding the sampled signal, and the amplifying operation for amplifying the held signal.

In some embodiments of the present invention, the second through N stages may include two or more far-flying digital-to-analog conversion circuits sharing an operational amplifier.

In some embodiments of the present invention, each of the first through N stages may include two or more flash analog-to-digital conversion circuits sharing a single comparator.

According to various embodiments of the present invention, the sampling circuit that provides the function of the sample and hold circuit to sample and hold the analog input signal and the function of the multiplying digital-to-analog conversion circuit includes one operational amplifier and a plurality of capacitors . The sampling circuit can reset the operational amplifier while sampling the analog input signal. Thus, it is possible to provide a pipelined analog-to-digital converter that minimizes the memory effect in the sampling circuit and reduces circuit area and power consumption without sampling errors.

The various and advantageous advantages and effects of the present invention are not limited to the above description, and can be more easily understood in the course of describing a specific embodiment of the present invention.

Figure 1 is a simplified block diagram of a pipelined analog-to-digital converter in accordance with an embodiment of the present invention.
Figure 2 is a simplified block diagram of a first stage that may be included in a pipelined analog-to-digital converter in accordance with an embodiment of the invention.
3 is a simplified circuit diagram of a sampling circuit that may be included in a first stage of a pipelined analog-to-digital converter in accordance with an embodiment of the present invention.
4A to 4C are circuit diagrams for explaining the operation of the sampling circuit shown in FIG.
5 is a simplified block diagram of second to Nth stages that may be included in a pipelined analog-to-digital converter in accordance with an embodiment of the present invention.
6 is a simplified circuit diagram of a multi-flying digital-to-analog conversion circuit that may be included in the second through N stages of a pipelined analog-to-digital converter in accordance with an embodiment of the present invention.
Figs. 7A and 7B are circuit diagrams for explaining the operation of the multi-flying digital-analog conversion circuit shown in Fig.
Figure 8 is a simplified circuit diagram of a flash analog-to-digital conversion circuit that may be included in the second through N stages of a pipelined analog-to-digital converter in accordance with an embodiment of the present invention.
9 is a block diagram illustrating a pipelined analog-to-digital converter in accordance with an embodiment of the present invention.
10 is a timing diagram illustrating the operation of a pipelined analog-to-digital converter according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

The embodiments of the present invention may be modified into various other forms or various embodiments may be combined, and the scope of the present invention is not limited to the embodiments described below. Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings may be exaggerated for clarity of description, and the elements denoted by the same reference numerals in the drawings are the same elements.

Figure 1 is a simplified block diagram of a pipelined analog-to-digital converter in accordance with an embodiment of the present invention.

1, a pipeline analog-to-digital converter 1 according to the present embodiment includes a converter section 20 having N stages 20-1 to 20-N connected in series with each other, And a digital error correction unit 30 for generating a digital output signal Dout by using the digital signals Dout (1) to Dout (N) generated by the respective digital signals Dout (1) to Dout (N).

The converter section 20 includes N stages 20-1 to 20-N connected in series, and each of the stages 20-1 to 20-N receives digital signals Dout (1) to Dout (N) Lt; / RTI > The first stage 20-1 can receive the analog input signal Vin and the second to Nth stages 20-2 to 20-N can receive the analog input signal Vin from the previous stages 20-1 to 20- (N-1) Can receive the analog residual signal outputted by the analog-to-digital converter.

Each of the stages 20-1 to 20-N samples an analog residual signal transmitted from the analog input signal Vin or previous stages 20-1 to 20- (N-1) using a circuit for sampling an analog signal . The first stage 20-1 can sample and hold the analog input signal Vin using a sample and hold circuit and the second to Nth stages 20-2 to 20- 20-1 to 20- (N-1). The analog-digital conversion circuit included in each of the stages 20-1 to 20-N can convert the sampled analog signal into digital signals Dout (1) to Dout (N). The analog-digital conversion circuit included in each of the stages 20-1 to 20-N may be a flash analog-to-digital converter (FADC).

On the other hand, each of the stages 20-1 to 20-N may include a digital-analog conversion circuit for converting the digital signals Dout (1) to Dout (N) back into analog signals. In one embodiment, each of the stages 20-1 to 20-N may include a multiplying digital-to-analog converter (MDAC). The MDAC included in each of the first to (N-1) th stages 20-1 to 20- (N-1) may generate an analog residual signal, The analog residual signals generated in each of the first to Nth stages 20-1 to 20- (N-1) may be transferred to the analog inputs to the second to Nth stages 20-2 to 20-N. The N-th stage 20-N connected at the last may not include the MDAC.

In particular, in various embodiments of the present invention, the MDAC included in the first stage 20-1 is provided as one sampling circuit with a sample and hold amplifier (SHA) that samples and holds the analog input signal Vin . That is, the first stage 20-1 may include one sampling circuit that provides the functions of SHA and MDAC, and the sampling circuit included in the first stage 20-1 may include one operational amplifier and a plurality As shown in FIG.

Each of the second to N-th stages 20-2 to 20-N may include a plurality of MDACs. A plurality of MDACs included in each of the stages 20-2 to 20-N share one operational amplifier can do. The first to N-th stages 20-1 to 20-N may include a plurality of FADCs. A plurality of FADCs included in each of the stages 20-1 to 20-N may share one comparator can do. For example, if the second stage 20-2 includes two MDACs and two FADCs, the two MDACs included in the second stage 20-2 may share one operational amplifier, Two FADCs can share a single comparator. When each of the stages 20-1 to 20-N includes two FADCs, each stage 20-1 to 20-N can generate two different DAC codes from different analog signals.

The digital error correcting unit 30 receives the digital signals Dout (1) to Dout (N) generated by the stages 20-1 to 20-N and generates a digital output signal Dout by applying an error correction algorithm have. When the pipelined analog-digital converter 1 shown in Fig. 1 is applied to the field of wireless communication technology, the digital error corrector 30 corrects an error caused by a wireless communication channel, such as multipath interference, Can be applied to each of the digital signals Dout (1) to Dout (N).

Figure 2 is a simplified block diagram of a first stage that may be included in a pipelined analog-to-digital converter in accordance with an embodiment of the invention.

The first stage 100 may include an SHA & MDAC 110 that receives and samples the analog signal Vin (1) and an FADC 120 that generates a digital signal Dout (1) from the sampled analog signal. The analog signal Vin (1) input to the first stage 100 may be a signal that has not passed through another stage. That is, the analog signal Vin (1) input to the first stage 100 can correspond to the analog input signal Vin shown in Fig.

The SHA & MDAC 110 may include a sampling circuit for sampling, holding and amplifying the analog signal Vin (1). The sampling circuit included in the SHA & MDAC 110 may be implemented with one operational amplifier and a plurality of capacitors. That is, in a pipelined analog-to-digital converter according to an embodiment of the present invention, the first stage may have one sampling circuit that together provide the functions of SHA and MDAC, and the one sampling circuit may be a single operational amplifier Implementation can minimize circuit area and power consumption. Further, unlike the case where the SHA sampling and holding the analog signal Vin (1) is included in the first stage 100, thereby sampling the analog signal Vin (1) to MDAC without SHA in the first stage 100, Errors due to time differences can be eliminated.

The FADC 120 included in the first stage 100 may include a plurality of FADC circuits sharing a single comparator. For example, if the FADC 120 includes two FADC circuits sharing a single comparator, then one comparator can operate at twice the operating speed of a single FADC circuit, Can be reduced. In addition, two FADC circuits sharing a comparator can improve linearity by sharing one voltage divider circuit that generates a reference voltage.

As described above, in the pipelined analog-to-digital converter according to the embodiment of the present invention, the first stage 100 samples the signals sampled and held by SHA and SHA, which sample and hold the analog signal Vin (1) (1), and an MDAC that converts the digital signal Dout (1) generated by the FADC back to analog to generate a first analog output signal V _OUT (1). That is, the first stage 100 includes MDAC and FADC included in the first stage of the general pipeline analog-to-digital converter, and SHA connected to the input of the first stage to sample and hold the analog input signal Vin It can be called a block. At this time, in order to prevent an increase in circuit area and power consumption, the first stage 100 can implement SHA and MDAC with one operational amplifier. The first analog output signal V _RES (1) output by the SHA & MDAC 110 of the first stage 100 may be delivered to a second stage coupled with the first stage 100 as a residual signal .

Figures 3a and 3b are simplified circuit diagrams of a sampling circuit that may be included in a first stage of a pipelined analog-to-digital converter in accordance with an embodiment of the present invention, Figures 4a-4c illustrate a sampling circuit Which is a circuit diagram for explaining the operation of the first embodiment. Hereinafter, the operation of the sampling circuit will be described with reference to FIGS. 3A, 3B and 4A to 4C.

The sampling circuit 115 according to the embodiment shown in FIG. 3A is included in the SHA & MDAC block 110 of the first stage 100 shown in FIG. 2 to sample, hold, and amplify the analog signal Vin (1) Circuit. That is, the sampling circuit 115 can perform both the functions of the SHA and the MDAC. As shown in FIG. 3A, the sampling circuit 115 may include one operational amplifier U1, a plurality of capacitors C1 and C2, and a plurality of switch elements SW1 to SW6. Each of the plurality of switch elements SW1 to SW6 can be selectively turned on in each period? 1 to? 4 shown in FIG. The output voltage Vout of the operational amplifier U1 may be the output voltage V _OUT (1) of the first stage 100 shown in FIG. 2 and may be transmitted as a residual signal to a second stage connected to the first stage 100 May be passed to the FADC 120 and used to generate the DAC code.

Meanwhile, the sampling circuit 115 'according to the embodiment shown in FIG. 3B may have a structure similar to the sampling circuit 115 shown in FIG. 3A. Unlike the sampling circuit 115 shown in FIG. 3A, the sampling circuit 115 'according to the embodiment of FIG. 3B receives the differential input signals V _IP and V _IM and generates output signals V _OP and V _OM . Since the differential input signals V _IM and V _IP are received, the sampling circuit 115 'according to the embodiment of FIG. 3B may have better noise characteristics than the sampling circuit 115 according to the embodiment of FIG. The inverting input terminal and the non-inverting input terminal of the operational amplifier U1` may be connected to a capacitor and a switch circuit having a symmetrical structure with each other.

Hereinafter, the operation of the sampling circuit 115 shown in Fig. 3A will be described with reference to Figs. 4A to 4C.

Fig. 4A is a circuit diagram for explaining the operation during the sampling period of the sampling circuit 115. Fig. The sampling period is represented by? 1, and during the sampling period? 1, the switch elements SW1 to SW3 are turned on and the remaining switch elements SW4 to SW6 are turned off. Therefore, the sampling circuit 115 can be represented by an equivalent circuit as shown in Fig. 4A.

Referring to FIG. 4A, the analog signal Vin (1) may be applied to the capacitors C1 and C2, respectively. One end of the capacitors C1 and C2 may be connected to the analog signal Vin (1) and the other end may be connected to the inverting input terminal of the operational amplifier U1. Since the noninverting input terminal of the operational amplifier U1 is connected to the ground terminal, if the operational amplifier U1 is ideal, the other end of the capacitors C1 and C2 can be connected to the ground terminal. Therefore, the capacitors C1 and C2 can sample the analog signal Vin (1).

On the other hand, during the sampling period? 1, the operational amplifier U1 can be reset by connecting the output terminal of the operational amplifier U1 to the inverting input terminal of the operational amplifier U1. Therefore, the memory effect of the operational amplifier U1 can be minimized.

Next, during the holding period? 2, the switch elements SW4 and SW5 are turned on and the other switch elements SW1-SW3 and SW6 are turned off. Therefore, the sampling circuit 115 can be represented by an equivalent circuit as shown in Fig. 4B. The capacitors C1 and C2 can be connected between the inverting input terminal and the output terminal of the operational amplifier U1 and the analog signal sampled in the capacitors C1 and C2 during the sampling period? 1 can be held. That is, during the sampling period? 1 and the holding period? 2, the sampling circuit 115 can operate as SHA to sample and hold the analog signal Vin (1). The output voltage Vout of the operational amplifier U1 can be held at V _HOLD during the holding period? 2.

During the period? 3 to? 4, the switch elements SW5 and SW6 are turned on and the remaining switch elements SW1 to SW4 are turned off. Therefore, as shown in FIG. 4C, the sampling circuit 115 can provide the function of the MDAC by performing the amplifying operation according to the ratio of the capacitors C1 and C2. D in the voltage D * V _REF applied to the capacitor C1 may be a DAC code output from the FADC 120 connected to the sampling circuit 115 and the voltage V _RES (1) output from the operational amplifier U1 during the period? May be provided to the second stage 20-2 as an analog residual signal.

That is, the sampling circuit 115 operates as SHA during periods? 1 -? 2 and can operate as MDAC during periods? 3 -? 4. The sampling circuit 115 according to the embodiment of the present invention not only removes the memory effect by resetting the operational amplifier U1 during the sampling period? 1, but also removes the memory effect of the capacitors C1 and C2 at the inverting input terminal of the operational amplifier U1 during the period? At least one continues to be connected so that the offset can be removed. Also, unlike the conventional configuration in which the SHA is removed to reduce the power consumption and circuit area of the pipelined analog-to-digital converter, the sampling circuit 115 operates like a SHA during periods? 1 -? 2, . Thus, a pipelined analog-to-digital converter that can eventually convert high frequency analog signals to digital can be implemented.

On the other hand, as shown in Figs. 4A to 4C, in the actual circuit, the parasitic capacitor Cp may exist between the non-inverting input terminal and the inverting input terminal of the operational amplifier U1. The parasitic capacitor Cp may affect the first analog residual signal V _RES (1) that the sampling circuit 115 transfers to the next stage. The analog residual signal V _RES (1) generated during the period? 3 -? 4 during which the sampling circuit 115 performs the amplification operation with the MDAC can be expressed as Equation 1 below.

On the other hand, the analog residual signal V _RES output in the general MDAC circuit during the amplification operation can be expressed by the following equation (2).

Therefore, by comparing Equations (1) and (2), it can be seen that the error is much less in Equation (1). In the case of using a structure in which the values of C1 and C2 are equal to each other and 1.5 bits per stage are used, the sampling circuit 115 according to the embodiment of the present invention generates errors Can be reduced by about 50%. That is, the error can be reduced compared to the conventional structure without resetting the operational amplifier U1 between the period? 2 in which the sampling circuit 115 operates in the holding mode and the period? 3 in which the operation in the amplification mode starts.

5 is a simplified block diagram of second to Nth stages that may be included in a pipelined analog-to-digital converter in accordance with an embodiment of the present invention. Although the embodiment of FIG. 5 shows the second stage 200, the embodiment of FIG. 5 differs from the second through N-th stages 20-2 through 20-N of the N stages 20-1 through 20- To 20-N, respectively. The first stage 100 shown in FIG. 2 may be connected to the front end of the second stage 200.

Referring to FIG. 5, the second stage 200 may receive the analog signal Vin (2) from the first stage 100 at the front end. As described above, the first stage 100 outputs the digital signal Dout (1) to the digital error correcting unit 30 and the analog residual signal V _RES (1) to the second stage. That is, the analog signal Vin (2) transmitted to the second stage 200 may be the first analog residual signal V _RES (1) output from the first stage.

The analog signal Vin (2) delivered to the second stage 200 may be sampled and amplified by the MDAC 210. The signal sampled and amplified by the MDAC 210 may be delivered to a third stage output to V _OUT (2) and coupled to the second stage 200.

Meanwhile, the MDAC 210 may include two MDAC circuits sharing an operational amplifier for sampling and amplification. In one embodiment, the MDAC 210 may include a first capacitor circuit operating as a first MDAC circuit and a second capacitor circuit operating as a second MDAC circuit, wherein the first capacitor circuit and the second capacitor The circuit can share an op amp. While the first capacitor circuit samples an analog signal, the second capacitor circuit may be coupled to an operational amplifier to perform an amplification operation, while the second capacitor circuit samples the analog signal while the first capacitor circuit And can be connected to an operational amplifier to perform an amplifying operation. Hereinafter, the operation of the MDAC 210 will be described with reference to FIGS. 6, 7A, and 7B.

6 is a simplified circuit diagram of a multi-flying digital-to-analog conversion circuit that may be included in the second through N stages of a pipelined analog-to-digital converter in accordance with an embodiment of the present invention. That is, the circuit shown in Fig. 6 may be a circuit included in the MDAC 210 of the second stage 200 shown in Fig.

Referring to FIG. 6, the MDAC 210 may include a first capacitor circuit 213 and a second capacitor circuit 215. Each of the capacitor circuits 213 and 215 may include a plurality of capacitors C1a, C2a, C1b and C2b. The capacitors C1a, C2a, C1b and C2b are connected to switch elements SW1a, SW2a, SW3a, SW4a, SW5a, SW6a and SW1b , SW2b, SW3b, SW4b, SW5b, and SW6b for sampling or amplifying operations. The first and second capacitor circuits 213 and 215 may share one operational amplifier U2. In FIG. 6, the input signal Vin (2) applied to the MDAC 210 may be the first analog residual signal V _RES (1) output from the first stage 100. The output voltage Vout of the operational amplifier U2 may correspond to the output voltage V _OUT (2) of the second stage 200 shown in Fig.

Figs. 7A and 7B are circuit diagrams for explaining the operation of the multi-flying digital-analog conversion circuit shown in Fig. Referring first to Fig. 7A, an equivalent circuit of the first capacitor circuit 213 and the second capacitor circuit 215 is shown during the period? 1 -? 2.

During the period? 1 -? 2, the switch elements SW1a, SW2a, and SW3a in the first capacitor circuit 213 are turned on and the switch elements SW4a, SW5a, and SW6a can be turned off. Further, the switch elements SW1b, SW2b, and SW3b are turned off in the second capacitor circuit 215, and the switch elements SW4b, SW5b, and SW6b can be turned on. Therefore, as shown in FIG. 7A, the capacitors C1a and C2a of the first capacitor circuit 213 are connected to the operational amplifier U2 to perform the amplifying operation so that the operational amplifier U2 can output the second analog residual signal V _RES (2) have. D2 at the applied D2 * V _REF applied to the capacitor C1a for the amplification operation may be the second DAC code generated in the FADC 120 of the first stage 100. [ On the other hand, the second capacitor circuit 215 can sample the second analog residual signal V _RES (2) output from the output terminal of the operational amplifier U2 to the capacitors C1b and C2b.

Next, referring to FIG. 7B showing the operation of the first and second capacitor circuits 213 and 215 during the period? 3 to? 4, the switch elements SW1a, SW2a and SW3a are turned off in the first capacitor circuit 213, The elements SW4a, SW5a and SW6a are turned on so that the capacitors C1a and C2a can sample the analog signal Vin (2). On the other hand, in the second capacitor circuit 215, the switch elements SW1b, SW2b and SW3b are turned on and the switch elements SW4b, SW5b and SW6b are turned off. The capacitors C1b and C2b are connected to the operational amplifier U2, can do. The voltage D3 * V _REF applied to the capacitor C1b during the amplification operation may be D3 generated by the FADC 220 included in the second stage 200. [ The analog residual signal V _RES (3) generated in the operational amplifier U2 by the amplifying operation can be transmitted to the third stage 20-3.

That is, as shown in FIGS. 7A and 7B, the first and second capacitor circuits 213 and 215 can alternately perform amplification and sampling operations. Therefore, it is possible to implement the functions of a plurality of MDAC circuits in one MDAC 210, thereby reducing circuit area and power consumption. The operational amplifier U2 can not be reset between the sampling operation and the amplifying operation, and a memory effect according to the parasitic capacitor may occur. However, as described above, since the MDAC 210 sharing the operational amplifier as shown in FIG. 6 is applied to the second and later stages of the pipelined analog-to-digital converter, the memory effect according to the parasitic capacitors affects the digital output signal The impact can be small.

5, the output of the MDAC 210 is again converted into a digital signal by the FADC 220 and delivered to the MDAC 210 while the digital output signal D _OUT (2) of the second stage 200, To the digital error correcting unit 30 as shown in FIG. As the MDAC 210 alternately performs sampling and amplification operations using the first and second capacitor circuits 213 and 215 sharing one operational amplifier U2, the FADC 220 shares one comparator A plurality of FADC circuits may be included. This will be described below with reference to Fig.

Figure 8 is a simplified circuit diagram of a flash analog-to-digital conversion circuit that may be included in the first to Nth stages of a pipelined analog-to-digital converter in accordance with an embodiment of the present invention. 8, the FADC 220 according to the present embodiment includes a comparator circuit 221 sharing one comparator 222, a voltage divider circuit 223 for generating a reference signal and supplying it to the comparator circuit 221 ), And a delay circuit 225.

The voltage divider circuit 223 can generate the reference signals V _REFP and V _REFM necessary to generate the upper and lower bits of the digital signal output by the FADC 220, respectively. The comparator circuit 221 samples the reference signals V _REFP and V _REFM during periods _Φ1 and _Φ3 and outputs the reference signals V _REFP and V _REFM and the input signals V _INP and V _INM using the operational amplifier U3 during periods Φ2 and Φ4 The difference can be amplified and output. The input signals V _INP and V _INM may be signals output from the SHA & MDAC 110 or MDAC 210 included in each of the first through N-th stages 20-1 through 20-N.

The output of the comparator 222 may be transmitted to the first delay circuit 226 and the second delay circuit 227 included in the delay circuit 225, respectively. The first and second delay circuits 226 and 227 may include a D-flip flop and the outputs of the first and second delay circuits 226 and 227 may be provided to the digital error correction section 30, the SHA & MDAC 110 and MDAC 210, respectively.

9A and 9B are block diagrams illustrating a pipelined analog-to-digital converter in accordance with an embodiment of the present invention.

The pipeline analog-to-digital converter 10 according to the embodiment shown in FIG. 9A includes a converter unit 300 having first and second stages 100 and 200 and a plurality of stages 100 and 200 of the converter unit 300, And a digital error correcting unit 400 for correcting errors of the digital signals Dout (1) and Dout (2) outputted from the digital signals Dout (1) and Dout (2). In FIG. 9A, the pipelined analog-to-digital converter 10 is illustrated as being implemented with two stages 100 and 200, but may alternatively include three or more stages.

The pipeline analog-digital converter 10 'according to the embodiment shown in FIG. 9B has a converter unit 300 and a digital error corrector 400 (FIG. 9B) in the same manner as the pipeline analog-digital converter 10 shown in FIG. ). However, in the embodiment of FIG. 9B, the pipelined analog-to-digital converter 10 'may receive the differential input signals V _IM and V _IP and generate a digital output signal D _OUT , unlike the embodiment of FIG. 9A. Therefore, it is possible to have a relatively excellent noise characteristic.

A typical pipelined analog-to-digital converter may include a sample and hold circuit (SHA) that samples and holds an analog input signal, and a plurality of stages coupled in series with the SHA, each of which includes one MDAC and one FADC can do. In the embodiment of the present invention, in order to reduce the circuit area and the power consumption and to reduce the error of the digital output signal Dout according to the sampling error, in general, the MDAC included in the first stage can be implemented so as to share one operational amplifier with the SHA have. Also, MDACs included in the second and third stages in a general pipelined analog-to-digital converter can be implemented to share one operational amplifier, and the FADCs included in each stage can also be implemented to share a single comparator .

Hereinafter, the pipelined analog-digital converter 10 will be described with reference to FIG. 9A. The description with reference to FIG. 9A can be similarly applied to the pipelined analog-digital converter 10 'shown in FIG. 9B.

9A, in a pipelined analog-to-digital converter 10 according to an embodiment of the present invention, the first stage 100 may include a SHA & MDAC 110 and a first FADC 120, The second stage 200 may include the MDAC 210 and the second FADC 220. The SHA & MDAC 110 included in the first stage 100 may include a sampling circuit 115 that can sample, hold, and amplify the analog input signal Vin. The sampling circuit 115 may be implemented with one operational amplifier U1 and a plurality of capacitors C1 and C2 as shown in FIG. 3A. Similarly, the SHA & MDAC 110 of the pipelined analog-to-digital converter 10 'shown in FIG. 9B may include a sampling circuit 115' as in the embodiment shown in FIG. 3B.

The first FADC 120 may be implemented by sharing one comparator 222 as shown in FIG. The first FADC 120 and the second FADC 220 may have similar structures. The digital signals Dout (1) and Dout (2) generated in the first FADC 120 and the second FADC 220 can be transmitted to the digital error correction unit 400.

The analog signal output by the SHA & MDAC 110 in the first stage 100 may be transmitted to the MDAC 210 of the second stage 200. 5, the analog signal transmitted to the MDAC 210 of the second stage 200 may be an analog residual signal generated by the SHA & MDAC 110. [ 6, the MDAC 210 may include first and second capacitor circuits 213 and 215 and the first and second capacitor circuits 213 and 215 may comprise one operational amplifier U2 . ≪ / RTI >

The pipeline analog-to-digital converter 10 according to the embodiment of the present invention includes a SHA for sampling and holding the analog input signal Vin and a SHA & MDAC 110 for implementing the MDAC as a single circuit, ). The SHA & MDAC 110 may include one sampling circuit 115 that provides both SHA and MDAC functions, and in particular, the sampling circuit 115 may be implemented as one operational amplifier U1 to reduce circuit area and power consumption Can be reduced. Since the SHA is integrally provided with the MDAC without omitting it, the sampling error of the analog input signal Vin can be reduced as compared with the structure in which the SHA is omitted, thereby converting the analog input signal Vin of high frequency into the digital output signal Dout .

The sampling circuit 115 included in the SHA & MDAC 110 may be the circuit shown in FIG. 3A. As described with reference to FIGS. 4A to 4C, the operational amplifier U1 is reset during the sampling operation to minimize the memory effect can do. Further, since the capacitor is continuously connected to the input terminal of the operational amplifier U1, the offset can be eliminated, and the problem that the offset is amplified together during the amplification operation can be solved.

Meanwhile, the MDAC 210 and the FADCs 120 and 220 may be implemented as circuits sharing an operational amplifier or a router, which are components of a circuit, thereby reducing the total circuit area and power consumption. The linearity can be improved by generating and sharing the reference voltages V _REFP and V _REFM with one voltage divider circuit 223 in the _FADCs 120 and 220.

10 is a timing diagram illustrating the operation of a pipelined analog-to-digital converter according to an embodiment of the present invention.

10, the sampling circuit 115 included in the SHA & MDAC 110 of the first stage 100 samples the analog input signal Vin at the period? 1 of the clock signal CLK that starts operation, Hold the sampled signal. At this time, the first FADC 120 generates a first DAC code by sampling a signal held by the sampling circuit 115, and outputs the first DAC code to the SHA & MDAC 110 during the period < RTI ID = 0.0 & The code can be passed to SHA & MDAC (110).

During the period? 3 -? 4, the MDAC 210 of the second stage 200 may sample the output of the SHA & MDAC 110. At period? 4, the first FADC 120 may sample the output of the SHA & MDAC 110 to generate a second DAC code. The first FADC 120 generates the first FADC 1 during the first phase 4 during the first phase? 4 so that the first capacitor circuit 213 of the MDAC 210 can perform the amplifying operation during the second phase? 1 -? 2 after the first phase? 2 DAC code to the first capacitor circuit 213 of the MDAC 210.

Meanwhile, during the second phase 2, the second FADC 220 samples the analog residual signal V _RES (2) output by the first capacitor circuit 213 of the MDAC 210 to generate a third DAC code during the second phase 3 - Can be generated. The third DAC code may be transferred to the second capacitor circuit 215 of the MDAC 210 during the second phase 3 to 4 and the second capacitor circuit 215 may use the third DAC code to generate the analog residual signal V _RES (3). On the other hand, the second FADC 220 may generate the fourth DAC code during the third phase? 1 -? 2 using the analog residual signal V _RES (3) generated by the second capacitor circuit 215. The digital error correction unit 400 may correct and sum the codes output from the first and second FADCs 120 and 220 and output the final digital output signal D _OUT at the rising edge of the third Φ 3.

The present invention is not limited to the above-described embodiment and the accompanying drawings, but is intended to be limited by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

1, 10: Pipeline analog-to-digital converter
20, 300: converter section
30, 400: digital error correction unit
100: first stage
200: second stage
110: SHA & MDAC
120: 1st FADC
210: MDAC
220: 2nd FADC

Claims (19)

A pipelined analog-to-digital converter for converting first to Nth (N is an integer of 2 or more) analog-to-digital conversion stages in series and converting an analog input signal into a digital output signal,
The first analog-to-digital conversion stage includes an operational amplifier, first and second capacitors, a sample and hold amplifier (SHA), and a multiplying digital-to-analog converter , ≪ / RTI > MDAC)
The sampling circuit includes a non-inverting input terminal of the operational amplifier while connecting the inverting input terminal and the output terminal of the operational amplifier to the ground terminal while sampling the analog input signal, Line analog-to-digital converter.
The method according to claim 1,
Wherein each of said second through Nth analog to digital conversion stages comprises two or more multiplying digital-to-analog conversion circuits sharing an operational amplifier.
The method according to claim 1,
Wherein each of the first through Nth analog digital-to-analog conversion stages comprises two or more Flash Analog-Digital Converters (FADCs) sharing one comparator.
The method of claim 3,
Wherein the two or more flash analog-to-digital conversion circuits included in each of the first to Nth analog to digital conversion stages share a voltage dividing circuit for generating a predetermined reference voltage.
The method of claim 3,
A digital error correcting section for generating the digital output signal based on the digital signal outputted by the two or more flash analog-digital converting circuits; To-analog converters.
delete The method according to claim 1,
Wherein the sampling circuit samples the analog input signal by connecting the first and second capacitors between an input signal terminal to which the analog input signal is transmitted and an inverting input terminal of the operational amplifier.
8. The method of claim 7,
Wherein the sampling circuit holds the sampled signal by connecting the first and second capacitors in parallel between an inverting input terminal of the operational amplifier and an output terminal of the operational amplifier.
9. The method of claim 8,
The sampling circuit may include a first capacitor connected between an inverting input terminal and an output terminal of the operational amplifier and connected between an input signal terminal to which a predetermined reference signal is transmitted and an inverting input terminal of the operational amplifier, A pipelined analog-to-digital converter that amplifies a connected and held signal.
A pipelined analog-to-digital converter comprising first to Nth (N is an integer of 2 or more) stages connected in series with each other and for converting an analog input signal into a digital output signal,
The first stage includes a sampling circuit implemented with one operational amplifier and first and second capacitors for sampling, holding and amplifying the analog input signal,
The sampling circuit includes a non-inverting input terminal of the operational amplifier while connecting the inverting input terminal and the output terminal of the operational amplifier to the ground terminal while sampling the analog input signal, Line analog-to-digital converter.
11. The method of claim 10,
The sampling circuitry connects at least one of the first and second capacitors to at least one of the input terminals of the operational amplifier while sampling, holding, and amplifying the analog input signal.
11. The method of claim 10,
Wherein the sampling circuit comprises a flip-around sample and hold circuit (Flip Around Sample and Hold Amplifier) implemented with the one operational amplifier and the first and second capacitors.
11. The method of claim 10,
Wherein said second through N stages comprise two or more far-flying digital-to-analog conversion circuits sharing an operational amplifier.
11. The method of claim 10,
Wherein each of said first through N stages comprises two or more flash analog-to-digital conversion circuits sharing a single comparator.
Wherein the first stage receives analog input signals and the second through N stages receive residue analog signals from a previous stage to generate a plurality of digital signals < RTI ID = 0.0 > A converter unit for generating an output signal; And
A digital error correction unit for correcting errors included in the plurality of digital signals to generate a digital output signal; / RTI >
Wherein the first stage includes a sample-and-hold circuit and a multiplier digital-to-analog converter circuit that constitute the input stage of the converter section and share the operational amplifier and the first and second capacitors, - Provides analog conversion circuit as one sampling circuit,
During operation of the sampling circuit, at least one of the input terminals of the operational amplifier is coupled to at least one of the first and second capacitors,
The sampling circuit includes a non-inverting input terminal of the operational amplifier while connecting the inverting input terminal and the output terminal of the operational amplifier to the ground terminal while sampling the analog input signal, Line analog-to-digital converter.
16. The method of claim 15,
The sampling circuitry resets the operational amplifier during sampling of the analog input signal.
16. The method of claim 15,
Wherein the sampling circuit sequentially repeats a sampling operation of sampling the analog input signal, a holding operation of holding the sampled signal, and an amplifying operation of amplifying the held signal.
16. The method of claim 15,
Wherein said second through N stages comprise two or more far-flying digital-to-analog conversion circuits sharing an operational amplifier.
16. The method of claim 15,
Wherein each of said first through N stages comprises two or more flash analog-to-digital conversion circuits sharing a single comparator.

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