JP2737680B2 - Sample hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a circuit for sampling and holding an output signal from a charge-coupled device for one pixel.

[0002]

2. Description of the Related Art In general, a charge-coupled device (Charge-coupled device)
The output signal from the Coupled Device (hereinafter referred to as CCD) is correlated double sampling (Correlated Double Sampling) for each pixel.
Sampling; hereinafter, referred to as CDS). Conventionally, in a sample-and-hold circuit that performs the CDS processing, a sampling clock (hereinafter, referred to as a CDS clock) is created by a circuit of a different system from an output signal from a CCD.

[0003] Japanese Patent Application Laid-Open No. 62-258570 discloses a system for reproducing a clock from a composite video signal. According to this method, a clock can be reproduced from the received composite video signal.

[0004]

In the above-mentioned conventional sample and hold circuit, since it is necessary to externally input a CDS clock whose phase relationship with the output signal from the CCD is fixed strictly, a dedicated circuit must be provided. No. Therefore, there is a disadvantage that the amount of hardware increases.

In addition, the method described in the above-mentioned patent publication requires a clock to be input in advance on the transmitting side of the composite video signal, and cannot be applied to the case where the output signal from the CCD is sampled and held. .

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a sample and hold circuit capable of reducing the amount of hardware.

[0007]

A sample and hold circuit according to the present invention determines a reference level portion serving as a reference of a charge accumulation level portion in a waveform of an output signal from a charge-coupled device for one pixel by a transition timing of a clamp signal. A sample and hold circuit for holding the value of the charge accumulation level, wherein the delay means delays the output signal for a predetermined time, and the clamp signal is generated according to a phase difference between the delay signal and the output signal. And a clamp signal generating means.

[0008]

In a sample and hold circuit for holding a charge accumulation level value by determining a reference level portion serving as a reference of a charge accumulation level portion in a waveform of an output signal from a charge-coupled device for one pixel at a transition timing of a clamp signal. , The output signal of the CCD is delayed by the delay line 1 for a predetermined time. The comparator 2 generates a clamp signal according to the phase difference between the delay signal and the output signal.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a sample and hold circuit according to the present invention. In the figure, a sample and hold circuit according to one embodiment of the present invention is:
A delay line 1 for delaying an output signal 10 of a CCD (not shown) for a predetermined time, a comparator 2 for comparing the voltage level of the delay signal with the output signal 10, and a rising timing of an output signal 20 which is a result of the comparison. And a clamp and hold circuit 3 for holding the value of the voltage level of the output signal 10.

Here, in the sample and hold circuit of this embodiment, the output of the delay line 1 and the comparator 2
Level clipper circuits 41 and 42 are inserted between the inputs. This is to prevent a malfunction of the comparator 2 due to a change in the voltage level of the output signal 10 from the CCD.

That is, the level clipper circuit 41
It is configured to include a diode D1 connected to a power supply voltage of 0.5 [V]. If the voltage between both ends of the diode D1 is 0.6 [V], 0.5−0.6 = −0.1. Therefore, the level clipper circuit 41 outputs the negative input of the comparator 2 from −0.1 [V]. Does not drop (minimum value is -0.1
[V]).

The level clipper circuit 42 has a voltage of -0.3.
It is configured to include a diode D2 connected to the power supply voltage of [V]. The voltage between both ends of the diode D2 is 0.6
If [V], then -0.3 + 0.6 = 0.3, so
In the level clipper circuit 42, the positive input of the comparator 2 does not exceed 0.3 [V] (the maximum value is 0.3 [V]).
It works like this.

As described above, the level clipper circuits 41 and 42 suppress fluctuations in the voltage levels of the output signal 10 from the CCD and the output signal 11 which is a delayed output, thereby preventing the comparator 2 from malfunctioning.

The operation of the sample and hold circuit according to this embodiment having the above configuration will be described with reference to FIG. FIG. 2 is a waveform diagram of each part of the sample and hold circuit of FIG. 1, and shows an output signal 10 of the CCD, an output signal 11 of the delay line 1, and an output signal 20 of the comparator 2.

In FIG. 1, an output signal 10 is a waveform of an output signal from a CCD for one pixel. This output signal 10
In the waveform of ( 1 ), the portion rising from -0.5 [V] to +0.5 [V] is called a reset edge,
This is caused by the crosstalk of the reset pulse for resetting the accumulated charge of. Then, after the output signal 10 becomes 0 [V] by this reset, CC
The voltage level becomes negative in accordance with the amount of accumulated charge of D. In the figure, the voltage level is -0.5 [V], but the voltage level fluctuates.

Here, the clamp and hold circuit 3 determines the portion of 0 [V] of the waveform of the output signal 10 as a reference level, and thereafter holds the charge accumulation level. In this embodiment, the voltage level of the output signal 10 is compared with the voltage level of the output signal 11 of the delay line 1 to determine the 0 [V] portion of the waveform as the reference level. Is used as a clamp signal.

That is, the output signal 20 generated in accordance with the phase difference between the output signal 10 and the output signal 11 is input to the clamp and hold circuit 3 as a clamp signal.
The 0 [V] portion of the waveform of the output signal 10 is determined as the reference level at the rising timing of the low level from 0 to the high level.

In order to make the rising timing of the output signal 20 coincide with the 0 [V] portion of the waveform of the output signal 10, a delay line (not shown) is connected to the clamp / hold circuit 3.
It is assumed that it is provided inside.

According to the configuration described above, it is not necessary to externally input a CDS clock whose phase is strictly fixed to the output signal from the CCD. Therefore, there is no need to provide an external dedicated circuit for generating the CDS clock.

Although the rising timing of the clamp signal is used in this embodiment, it is obvious that the falling timing may be used.

[0022]

As described above, according to the present invention, since the CDS clock is generated from the output signal itself from the CCD, there is no need to provide an external dedicated circuit for generating the CDS clock, and the amount of hardware is reduced. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a sample and hold circuit according to an embodiment of the present invention.

FIG. 2 is a waveform chart showing the operation of each unit in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Delay line 2 Comparator 3 Clamp hold circuit 41, 42 Level clipper circuit

Claims (3)

(57) [Claims] 1. A sample for holding a charge accumulation level value by determining a reference level portion serving as a reference for a charge accumulation level portion in a waveform of an output signal from a charge-coupled device for one pixel at a transition timing of a clamp signal. A hold circuit, comprising: delay means for delaying the output signal for a predetermined time; and clamp signal generation means for generating the clamp signal according to a phase difference between the delay signal and the output signal. Sample hold circuit. 2. The clamp signal generation unit includes a comparison unit that compares a voltage level between the delay signal and the output signal, and outputs a signal that changes in response to a change in the comparison result as the clamp signal. The sample and hold circuit according to claim 1, wherein: 3. The sample and hold circuit according to claim 2, further comprising a level fluctuation suppressing unit for suppressing a voltage level fluctuation of each of said delay signal and said output signal.