JP2002152550A - Clamp control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the flicker in a video by reducing the fluctuation of a clamp level after clamp control convergence. SOLUTION: The clamp level of an input video signal s clamped to a clamp control level by a digital control clamp circuit 32, and converted into a digital signal by an A/D converter 12. The clamp level is compared with a clamp set level by an error detector 16, a mean value is calculated by a mean value calculating circuit 34, and components in core ring amounts or less are removed by a core ring processing circuit 36. The processed result is inputted to an integrator 18, and the integrated value is fed back to the clamp circuit 32 as the clamp control level. At that time, even when the detection signal of the error detector 16 is changed only by a value corresponding to 1 control level width (w) of the clamp control level, it is removed by the core ring processing circuit 36, and the processed result is inputted to the integrator 18. Thus, it is possible to prevent the fluctuation of the clamp control level to be fed back to the clamp circuit 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp control circuit for controlling a clamp circuit in a video signal input processing circuit.

[0002]

2. Description of the Related Art A conventional clamp control circuit 100 is shown in FIG.
As shown in the figure, the analog control clamp circuit 10, A / D
(Analog / digital) converter 12, clamp control signal generation circuit 14, error detector 16, integrator 18, D / A
(Digital / Analog) converter 20 and LPF (Low Pass Filter) 22. 24 is A / D
This is a video processing block that processes a digital video signal output from the converter 12.

The analog control clamp circuit 10
6A shows a clamp level (eg, a black reference pedestal) for an analog video signal input to the terminal 26 during a period T2 designated by a clamp pulse as shown in FIG. Level) to the clamp control voltage. The A / D converter 12 converts the analog video signal clamped by the analog control clamp circuit 10 into a digital video signal.

[0006] The clamp control signal generation circuit 14
6 based on the synchronization signal (for example, a horizontal synchronization signal and a vertical synchronization signal separated from the input video signal) input to FIG.
(B) A clamp pulse and a clamp level detection signal as shown in (c) are generated. The period T2 specified by the clamp pulse is, for example, as shown in FIG. 6B, a period starting from a point in time when the set period T1 has elapsed from the fall of the horizontal synchronizing signal and having an end point immediately before the start of the video signal. Thus, the pulse period of the clamp level detection signal is a period from immediately after the end point of the color burst to immediately before the start point of the period T2, as shown in FIG.

The error detector 16 inputs a clamp level (for example, a pedestal level) of an output signal of the A / D converter 12 and a terminal 30 based on the clamp level detection signal generated by the clamp control signal generation circuit 14. The clamp setting levels are compared, and the difference is detected. Integrator 18
Integrates the detection signal of the error detector 16 and outputs the D / A converter 2
0 converts the integrated signal of the integrator 18 into an analog signal.
The LPF 22 limits the frequency band of the output signal of the D / A converter 20 and feeds it back to the analog control clamp circuit 10 as a clamp control voltage.

On the other hand, with the digitization of analog circuits, a clamp circuit IC for setting a clamp level with a digital set value has been used instead of the analog control clamp circuit 10 of FIG. For example, in a video signal processing circuit, a digitally controlled clamp circuit is often built in a video amplifier or an A / D converter. In such a case, it is necessary to control the clamp circuit with digital data.

[0007]

However, in the case of the digitally controlled clamp circuit, the clamp control level becomes discontinuous even after the clamp control has converged, so that the clamp level of the video signal fluctuates due to this discontinuity. However, there is a problem that the image flickers.

That is, the clamp control circuit 100 shown in FIG.
Is converted to a clamp control circuit 102 as shown in FIG. 7, specifically, a digital control clamp circuit 32 is provided instead of the analog control clamp circuit 10, and the D / A converter 20 and the LPF 22 are omitted. , Digital control clamp circuit 3
In the case where the clamp control level is fed back to 2, the clamp control level is a digital value. Therefore, even if the clamp control converges, there is a level fluctuation of one control level width w, resulting in discontinuity as shown in FIG. .

For this reason, the optimum level of the clamp control level is X, the clamp set level is Y, and the change of one control level width w of the clamp control level is the two quantization level widths of the output signal of the A / D converter 14. Assuming that the clamp control level after the convergence of the clamp control fluctuates between X and X-1 as shown in FIG. 9A in response to the change, the A / D converter 14 responds to this level fluctuation. The clamp level of the output signal also fluctuates between Y-1 and Y + 1 as shown in FIG. 2B, causing flickering of the image.

In the circuit shown in FIG. 7, a change in one control level width w of the clamp control level is an n quantization level width (n is 2) other than the two quantization level width of the output signal of the A / D converter 14.
Is an integer other than. ), The same level fluctuation caused flickering of the image. For example, when n = 1, the clamp control level is
When the level changes as shown in (a), the A / D converter 1
4 is Y and Y-1 or Y + 1
When the clamp control level fluctuates as shown in FIG. 9A when n = 3, the clamp level of the output signal of the A / D converter 14 becomes Y.
+1 and Y-2 or between Y + 2 and Y-1,
This was causing flickering of the image.

Also, in the circuit shown in FIG.
When the clamp control voltage fed back to the analog control clamp circuit 10 fluctuates as shown by the dotted line in FIG. 8, the clamp level of the output signal of the A / D converter 14 also fluctuates according to this fluctuation, and the image flickers. There was a problem that caused it.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in the clamp control of the digital control clamp circuit, it is possible to suppress the fluctuation of the clamp level after the convergence of the clamp control, and to reduce the flicker of the image. It is an object of the present invention to provide a clamp control circuit. Another object of the present invention is to provide a clamp control circuit capable of suppressing fluctuation of a clamp level after convergence of a clamp control in a clamp control of an analog control clamp circuit and reducing flickering of an image. It is.

[0013]

According to a first aspect of the present invention, there is provided a digital control clamp circuit for clamping a clamp level of an analog input video signal to a digital clamp control level during a clamp control period designated by a clamp pulse. An A / D converter for converting an output signal of a digital control clamp circuit into a digital signal; a clamp for generating a clamp pulse and a clamp level detection signal based on a synchronization signal and outputting the generated clamp pulse to the digital control clamp circuit A control signal generation circuit;
Error detection for detecting a difference by comparing a clamp level of an output signal of an A / D converter with a preset clamp setting level in a detection period designated by a clamp level detection signal generated by the clamp control signal generation circuit. Vessels,
A coring processing circuit for performing a coring process on a detection signal of the error detector with a threshold set to a level width equal to or more than one control level of a clamp control level and less than two control levels as a coring amount, and a coring processing circuit And an integrator for integrating the signal subjected to the coring processing in step (1) and outputting the integrated value as a clamp control level to the digital control clamp circuit.

In such a configuration, after the analog input video signal has its clamp level clamped to the clamp control level by the digital control clamp circuit, the analog input video signal has an A level.
It is converted to a digital signal by a / D converter. When the video signal converted to the digital signal is input to the error detector, the clamp level is compared with the clamp set level, and a difference is detected. When this detection signal is input to the coring processing circuit, components below the coring amount are removed and input to the integrator, and the integrated value is fed back to the digital control clamp circuit as a clamp control level.
At this time, even if the clamp level of the output signal of the A / D converter fluctuates by a value (for example, two quantization level widths) corresponding to one control level width of the clamp control level, this level fluctuation is caused by the coring processing. Since it is removed by the circuit and input to the integrator, the clamp control level does not fluctuate and A
The fluctuation of the clamp level of the output signal of the / D converter is suppressed. Therefore, it is possible to suppress the fluctuation of the clamp level after the convergence of the clamp control and reduce the flicker of the image.

According to a second aspect of the present invention, in the first aspect of the present invention, in order to set the clamp level of the input video signal to a pedestal level, the digital control clamp circuit is provided with an analog input signal during a clamp control period designated by a clamp pulse. The pedestal level of the video signal is clamped to a digital clamp control level, and the error detector detects A / D during the detection period specified by the clamp level detection signal.
The pedestal level of the output signal of the D converter is compared with a preset clamp setting level to detect a difference.

According to a third aspect of the present invention, there is provided an analog control clamp circuit for clamping a clamp level of an analog input video signal to an analog clamp control voltage during a clamp control period specified by a clamp pulse, and an output of the analog control clamp circuit. An A / D converter for converting a signal into a digital signal, a clamp control signal generation circuit for generating a clamp pulse and a clamp level detection signal based on a synchronization signal, and outputting the generated clamp pulse to an analog control clamp circuit; An error detector that compares a clamp level of an output signal of the A / D converter with a preset clamp setting level to detect a difference during a detection period designated by a clamp level detection signal generated by the control signal generation circuit; , A preset threshold value for the detection signal of this error detector A coring processing circuit for coring process as a coring amount, an integrator for integrating the coring processed signal in the coring circuit, D / A converting the signal integrated by the integrator to an analog signal
A converter and an LPF for limiting a frequency band of an output signal of the D / A converter and outputting the same as a clamp control voltage to an analog control clamp circuit.

In such a configuration, after the analog input video signal has its clamp level clamped to the clamp control level by the analog control clamp circuit, A / A
It is converted to a digital signal by a D converter. When the video signal converted to the digital signal is input to the error detector, the clamp level is compared with the clamp set level, and a difference is detected. When this detection signal is input to the coring processing circuit, a component equal to or less than the coring amount is removed and input to the integrator. The integrated value obtained by the integrator is converted into an analog signal by the D / A converter, is limited to a predetermined frequency band by the LPF, and is fed back as a clamp control voltage to the analog control clamp circuit. At this time,
Even if the clamp level of the output signal of the A / D converter fluctuates by a value corresponding to the threshold value set as the coring amount of the coring processing circuit, the level fluctuation is removed by the coring processing circuit and the integrator is removed. , The clamp control voltage does not change and the change in the clamp level of the output signal of the A / D converter is suppressed. Therefore, it is possible to suppress the fluctuation of the clamp level after the convergence of the clamp control and reduce the flicker of the image.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the analog control clamp circuit is provided so that the clamp level of the input video signal is set to the pedestal level during the clamp control period designated by the clamp pulse. The pedestal level of the video signal is clamped to the analog clamp control voltage, and the error detector detects the pedestal level of the output signal of the A / D converter and the preset clamp setting during the detection period specified by the clamp level detection signal. The level is compared to detect a difference.

According to a fifth aspect of the present invention, in the first, second, third or fourth aspect, an average value calculating circuit is inserted between the error detector and the coring processing circuit in order to stabilize the circuit operation. Then, the average value calculation circuit calculates the average value of the detection signal of the error detector in a certain period.

According to a sixth aspect of the present invention, in the fifth aspect of the present invention, in order to simplify the configuration of the average value calculation circuit as one horizontal scan period in which a fixed period can be easily formed, the average value calculation circuit includes one horizontal scan period. The average value of the detection signal of the error detector during the period is calculated.

According to a seventh aspect of the present invention, in order to stabilize the circuit operation and to simplify the structure of the average value calculation circuit as one vertical scanning period in which a fixed period can be easily formed. , The average value calculation circuit calculates the average value of the detection signal of the error detector during one vertical scanning period.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of a clamp control circuit according to the present invention. In FIG. 1, the same parts as those in FIGS.
In FIG. 1, reference numeral 1 denotes a clamp control circuit. The clamp control circuit 1 includes a digital control clamp circuit 32, A /
D converter 12, clamp control signal generation circuit 14, error detector 16, average value calculation circuit 34, coring processing circuit 3
6 and an integrator 18. Reference numeral 24 denotes a video processing block that processes a digital video signal output from the A / D converter 12.

The digital control clamp circuit 32 includes:
With respect to the analog video signal shown in FIG. 6A input to the terminal 26, the clamp level (for example, pedestal level) of the period T2 designated by the clamp pulse shown in FIG. Clamp to the clamp control level fed back from 18. A /
The D converter 12 includes the digital control clamp circuit 32
Converts the analog video signal clamped by the above into a digital video signal. The clamp control signal generation circuit 14
Generates a clamp pulse and a clamp level detection signal as shown in FIGS. 6B and 6C based on a synchronization signal input to the terminal 28 (for example, a horizontal synchronization signal or a vertical synchronization signal separated from the input video signal). I do.

The error detector 16 detects a clamp level (for example, a pedestal level) of an output signal of the A / D converter 12 and a terminal 30 based on the clamp level detection signal generated by the clamp control signal generation circuit 14. Are compared with each other and the difference is detected. The average value calculation circuit 34 calculates and outputs the average value of the detection signal of the error detector 16 for a certain period (for example, one vertical scanning period or one horizontal scanning period).

The coring processing circuit 36 performs coring processing on the output signal of the average value calculation circuit 34 using a preset threshold value as a coring amount. The threshold value set as the coring amount is, specifically, a control level width w of not less than one control level and less than two control levels of a clamp control level fed back from the output side of the integrator 18 to the digital control clamp circuit 32. Is set to Therefore, the coring processing circuit 36
Has an input / output characteristic as shown in FIG. 2, and outputs 0 when the level of an input value from the output side of the average value calculation circuit 34 is -1 or more and +1 or less, and is -2 or less and +2 or more. In the case of, the input value is output as it is.

The integrator 18 integrates the output signal of the coring processing circuit 36, and feeds back the integrated value as a clamp control level to the digital control clamp circuit 32. For example, when the output signal of the coring processing circuit 36 is a 0-level signal, a predetermined value is fed back from the integrator 18 to the digital control clamp circuit 32 as a clamp control level, and the output signal of the coring processing circuit 36 is output. Is a signal other than the 0 level,
A value obtained by increasing or decreasing a value corresponding to the amount of change from the level from the set value is fed back to the digital control clamp circuit 32 as a clamp control level.

Next, the operation of FIG. 1 will be described with reference to FIGS. (1) In FIG. 1, after the analog video signal input to the terminal 26 is clamped to the clamp control level by the digital control clamp circuit 32,
The digital signal is converted by the A / D converter 12. When the video signal converted to a digital signal by the A / D converter 12 is input to the error detector 16, the clamp level is compared with the clamp set level input to the terminal 30, and a difference is detected.

(2) When the detection signal detected by the error detector 16 is input to the average value calculation circuit 34, the average value calculation circuit 34 calculates the average value for a certain period (for example, one vertical scanning period or one horizontal scanning period). Is calculated and input to the coring processing circuit 36.

(3) When the level of the output signal of the average value calculation circuit 34 is greater than or equal to -1 and less than or equal to +1, the signal of 0 level which is suppressed by the coring processing circuit 36 and is supplied to the integrator 18 as shown in FIG. Since the input is input, the clamp control level fed back from the integrator 18 to the digital control clamp circuit 32 becomes a constant value as shown in FIG. 3 and does not change. 3, the dotted line represents the clamp control level of FIG.

(4) When the level of the output signal of the average value calculation circuit 34 is less than or equal to -2 and greater than or equal to +2, the coring processing circuit 36 keeps the level of the output signal of the average value calculation circuit 34 as shown in FIG. Output to the integrator 18. For this reason, the clamp control level fed back from the integrator 18 to the digital control clamp circuit 32 changes the error detector 1
The clamp control is performed in a direction which changes in accordance with the detection signal of No. 6 and in which the detection signal becomes 0.

(5) As is clear from the above (3) and (4), the clamp control level converges within the range of the control level range from one control level to less than two control levels set by the coring processing circuit 36. Since the clamp control is performed as described above and the clamp control level is constant and does not fluctuate after the clamp level converges, the fluctuation of the clamp level of the output signal of the A / D converter 12 is suppressed to reduce the flicker of the image. be able to.

FIG. 4 shows a second embodiment of the clamp control circuit according to the present invention. The same reference numerals as in FIGS. 1 and 5 denote the same parts, and a description thereof will be simplified. 4, reference numeral 1a denotes a clamp control circuit. The clamp control circuit 1a includes an analog control clamp circuit 10, an A / D converter 12, a clamp control signal generation circuit 14, an error detector 16, an average value calculation circuit 34, and a core. Ring processing circuit 36, integrator 18, D /
An A converter 20 and an LPF 22 are provided. 24
Is a video processing block for processing a digital video signal output from the A / D converter 12.

The analog control clamp circuit 10 clamps the analog video signal input to the terminal 26 as shown in FIG. 6A for a period T2 designated by a clamp pulse as shown in FIG. A level (for example, a pedestal level) is clamped to a clamp control voltage fed back from the LPF 22. The A / D converter 12 converts the analog video signal clamped by the analog control clamp circuit 10 into a digital video signal. The clamp control signal generation circuit 14 generates a signal shown in FIG. 6 based on a synchronization signal input to the terminal 30 (for example, a horizontal synchronization signal or a vertical synchronization signal separated from an input video signal).
(B) A clamp pulse and a clamp level detection signal as shown in (c) are generated.

On the basis of the clamp level detection signal generated by the clamp control signal generation circuit 14, the error detector 16 outputs a clamp level (for example, a pedestal level) of the output signal of the A / D converter 12 and a terminal 28. Are compared with each other and the difference is detected. The average value calculation circuit 34 calculates and outputs the average value of the detection signal of the error detector 16 for a certain period (for example, one vertical scanning period or one horizontal scanning period).

The coring processing circuit 36 performs a coring process on the output signal of the average value calculation circuit 34 using a predetermined threshold value as a coring amount. The threshold value set as the coring amount is specifically described in FIG.
Is set to a voltage value corresponding to the control level width of not less than one control level and less than two control levels shown in the embodiment.
For this reason, the coring processing circuit 36 has input / output characteristics as shown in FIG. 2, and when the level of the input value from the output side of the average value calculation circuit 34 is -1 or more and 0 or less, 0 is set. When the value is -2 or less and +2 or more, the input value is output as it is.

The integrator 18 integrates the output signal of the coring processing circuit 36. For example, when the output signal of the coring processing circuit 36 is a 0-level signal, a predetermined value is output from the integrator 18 as an integrated value, and the output signal of the coring processing circuit 36 is a signal other than the 0 level. In some cases, a value obtained by increasing or decreasing a value corresponding to the amount of change from the 0 level from a set value is output as an integral value. The D / A converter 20 converts the integrated value of the integrator 18 into an analog signal. The LPF 22 limits the frequency band of the output signal of the D / A converter 20, and feeds back the analog control clamp circuit 10 as a clamp control voltage.

Next, the operation of FIG. 4 will be described. (1) In FIG. 4, after the analog video signal input to the terminal 26 is clamped to a clamp control voltage by the analog control
The signal is converted into a digital signal by the D converter 12. This A /
When the video signal converted to a digital signal by the D converter 12 is input to the error detector 16, the clamp level is compared with the clamp set level input to the terminal 28, and a difference is detected.

(2) When the detection signal detected by the error detector 16 is input to the average value calculation circuit 34, the average value calculation circuit 34 calculates the average value for a certain period.
It is input to the coring processing circuit 36.

(3) When the level of the output signal of the average value calculation circuit 34 is greater than or equal to -1 and less than or equal to +1, a signal of 0 level which is suppressed by the coring processing circuit 36 and is supplied to the integrator 18 as shown in FIG. Since this is input, the clamp control voltage fed back from the integrator 18 to the analog control clamp circuit 10 via the D / A converter 20 and the LPF 22 does not fluctuate at a constant value.

(4) When the level of the output signal of the average value calculation circuit 34 is -2 or less and +2 or more, the coring processing circuit 36 keeps the level of the output signal of the average value calculation circuit 34 as shown in FIG. Output to the integrator 18. For this reason, the clamp control voltage fed back from the integrator 18 to the analog control clamp circuit 10 via the D / A converter 20 and the LPF 22 changes according to the detection signal of the error detector 16, and this detection signal becomes 0 The clamp control is performed in a certain direction.

(5) As is clear from the above (3) and (4), the clamp control is performed so that the clamp control voltage converges within the threshold value set by the coring processing circuit 36, and after the clamp level converges. Since the clamp control voltage is constant and does not fluctuate, the fluctuation of the clamp level of the output signal of the A / D converter 12 can be suppressed to reduce the flicker of the image.

In the embodiment shown in FIGS. 1 and 4, an average value calculation circuit is inserted between the error detector and the coring processing circuit, and the average value calculation circuit performs a certain period (for example, one vertical scanning period or one vertical scanning period). The circuit operation is stabilized by calculating the average value of the detection signal of the error detector for one horizontal scanning period) and outputting the average value to the coring processing circuit. However, the present invention is not limited to this. Instead, it is also possible to use a case where the average value calculation circuit is omitted and the detection signal of the error detector is directly output to the coring processing circuit.

[0043]

According to the first aspect of the present invention, a digital control clamp circuit, an A / D converter, a clamp control signal generation circuit,
Comprising an error detector, a coring processing circuit and an integrator,
The clamp level of the input video signal is converted to a digital signal after being clamped to the clamp control level, the clamp level is compared with the clamp set level, the difference is detected, and signal components smaller than the coring amount are removed from the detected signal and integrated. The integrated value is fed back to the digital control clamp circuit as the clamp control level. At this time, even if the clamp level of the output signal of the A / D converter changes by a value (for example, two quantization level widths) corresponding to one control level width of the clamp control level,
Since the signal is removed by the coring processing circuit and input to the integrator, the clamp control level does not change, and the level change of the clamp level of the output signal of the A / D converter is suppressed. Therefore, it is possible to suppress the fluctuation of the clamp level after the convergence of the clamp control and reduce the flicker of the image.

According to a second aspect of the present invention, in the first aspect of the present invention, the digital control clamp circuit clamps the pedestal level of the input video signal to the clamp control level during the clamp control period specified by the clamp pulse. However, in the detection period designated by the clamp level detection signal, the pedestal level of the output signal of the A / D converter is compared with a preset clamp set level to detect a difference, so that the input video signal The clamp level can be a pedestal level serving as a black reference.

According to a third aspect of the present invention, there is provided an analog control clamp circuit, an A / D converter, a clamp control signal generation circuit, an error detector, a coring processing circuit, an integrator, a D / A converter, and an LPF. The clamp level of the input video signal is converted to a digital signal after being clamped to the clamp control level, the clamp level is compared with the clamp set level, the difference is detected, and signal components smaller than the coring amount are removed from the detected signal and integrated. The integrated value is converted to an analog signal to limit the frequency band, and the value is fed back to the analog control clamp circuit as a clamp control voltage. At this time, even if the clamp level of the output signal of the A / D converter fluctuates by a value corresponding to the coring amount (threshold) of the coring processing circuit, this level fluctuation is removed by the coring processing circuit. Since the signal is input to the integrator, the level fluctuation of the clamp level of the output signal of the A / D converter is suppressed. Therefore, it is possible to suppress the fluctuation of the clamp level after the convergence of the clamp control and reduce the flicker of the image.

According to a fourth aspect of the present invention, in the third aspect, the analog control clamp circuit clamps the pedestal level of the analog input video signal to the analog clamp control voltage during the clamp control period specified by the clamp pulse. Since the error detector compares the pedestal level of the output signal of the A / D converter with a preset clamp setting level in a detection period designated by the clamp level detection signal, and detects the difference, The clamp level of the input video signal can be a pedestal level serving as a black reference.

According to a fifth aspect of the present invention, in the first, second, third, or fourth aspect, an average value calculation circuit is inserted between the error detector and the coring processing circuit, and the average value calculation circuit uses the average value calculation circuit for a predetermined period. In this configuration, the average value of the detection signal of the error detector is calculated, so that the circuit operation can be stabilized.

According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the average value calculation circuit is configured to calculate the average value of the detection signal of the error detector during one horizontal scanning period. The configuration of the average value calculation circuit can be simplified as one horizontal scanning period.

According to a seventh aspect of the present invention, in the fifth aspect, the average value arithmetic circuit is configured to calculate the average value of the detection signal of the error detector during one vertical scanning period. At the same time, the configuration of the average value calculation circuit can be simplified by setting a certain period as one vertical scanning period that is easy to form.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a clamp control circuit according to the present invention.

FIG. 2 is a characteristic diagram showing input / output characteristics of a coring processing circuit in FIG.

FIG. 3 is a characteristic diagram showing a change over time of a clamp control level fed back from the integrator 18 to the digital control clamp circuit when the output level of the coring processing circuit 36 is 0 in FIG.

FIG. 4 is a block diagram showing a second embodiment of the clamp control circuit according to the present invention.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a waveform diagram showing a timing relationship among an input video signal, a clamp pulse, and a clamp level detection signal in FIG.

FIG. 7 is a block diagram of a circuit obtained by digitizing the clamp control circuit of FIG. 5;

8 is a characteristic diagram showing a change with time of a clamp control level fed back from the output side of the integrator 18 to the digital control clamp circuit 32 in FIG. 7;

9 is a diagram conceptually showing how the level of the output signal of the A / D converter 12 fluctuates at a rate of two quantization levels with respect to a fluctuation of one control level of the clamp control level in FIG. 7; (A) shows a state where the clamp control level fluctuates by one control level, and (b) shows a state where the clamp level of the output signal of the corresponding A / D converter 12 fluctuates by two quantization levels. It is.

[Explanation of symbols]

1, 1a, 100, 102 ... clamp control circuit, 10
... Analog control clamp circuit 12 A / D converter
14 ... clamp control signal generation circuit 16 ... error detector 18 ... integrator 20 ... D / A converter 22 ...
LPF, 24: video processing block, 32: digital control clamp circuit, 34: average value calculation circuit, 36
... Coring processing circuit, w ... 1 control level width.

Continued on the front page (72) Inventor Junichi Onodera 1116 Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture Inside Fujitsu General Co., Ltd. (72) Inventor Makoto Ikeda 1116, Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Co., Ltd. Person Eizo Nishimura 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa F-term in Fujitsu General Limited (reference) 5C021 PA13 PA17 PA34 PA53 PA58 PA76 PA85 PA86 RC03 SA02 SA11 XA42 XA48 XA52 XA58 XA59 YA01 YC00

Claims (7)

[Claims] 1. A digital control clamp circuit for clamping a clamp level of an analog input video signal to a digital clamp control level during a clamp control period specified by a clamp pulse, and converting an output signal of the digital control clamp circuit into a digital signal. A / D to convert
Generating a clamp pulse and a clamp level detection signal based on an (analog / digital) converter and a synchronization signal,
A clamp control signal generation circuit for outputting the generated clamp pulse to the digital control clamp circuit; and an output signal of the A / D converter during a detection period specified by the clamp level detection signal generated by the clamp control signal generation circuit. An error detector for detecting a difference by comparing the clamp level with a preset clamp setting level, and a control level of not less than 1 control level and less than 2 control levels of the clamp control level with respect to a detection signal of the error detector. A coring processing circuit that performs a coring process using a threshold value set for the width as a coring amount, and integrates the signal that has been subjected to the coring process in the coring processing circuit, and sets the integrated value as a clamp control level to the digital control clamp circuit. A clamp control circuit comprising: an output integrator. 2. The digital control clamp circuit clamps a pedestal level of an analog input video signal to a digital clamp control level during a clamp control period designated by a clamp pulse, and an error detector includes a clamp level detection signal. In the detection period specified in,
2. The clamp control circuit according to claim 1, wherein a difference is detected by comparing a pedestal level of an output signal of the A / D converter with a preset clamp set level. 3. An analog control clamp circuit for clamping a clamp level of an analog input video signal to an analog clamp control voltage during a clamp control period designated by a clamp pulse, and converting an output signal of the analog control clamp circuit into a digital signal. An A / D (analog / digital) converter for conversion, a clamp control signal generation circuit for generating a clamp pulse and a clamp level detection signal based on a synchronization signal, and outputting the generated clamp pulse to the analog control clamp circuit; In the detection period specified by the clamp level detection signal generated by the clamp control signal generation circuit, an error in which the difference is detected by comparing the clamp level of the output signal of the A / D converter with a preset clamp setting level. Detector and the detection signal of this error detector Coring processing circuit that performs coring processing using the set threshold value as the amount of coring, an integrator that integrates the signal that has been subjected to coring processing by this coring processing circuit, and an analog signal that is integrated by the integrator. And a LPF (low-pass filter) for limiting the frequency band of the output signal of the D / A converter and outputting the same as a clamp control voltage to the analog control clamp circuit. A clamp control circuit, comprising: 4. An analog control clamp circuit clamps a pedestal level of an analog input video signal to an analog clamp control voltage during a clamp control period specified by a clamp pulse, and an error detector includes a clamp level detection signal. A / D in the detection period specified by
4. The clamp control circuit according to claim 3, wherein a difference is detected by comparing a pedestal level of an output signal of the converter with a preset clamp set level. 5. An average value calculation circuit is inserted between an error detector and a coring processing circuit, and the average value calculation circuit calculates an average value of a detection signal of the error detector during a predetermined period to perform the coring. 3. An output to a processing circuit.
5. The clamp control circuit according to 3 or 4. 6. The average value calculation circuit calculates an average value of detection signals of an error detector during one horizontal scanning period.
The described clamp control circuit. 7. The average value calculation circuit calculates an average value of detection signals of an error detector during one vertical scanning period.
The described clamp control circuit.