JP2522395B2 - Video signal clamp circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal clamp circuit for constantly maintaining a clamp voltage of a video signal at a constant level.

[Prior Art] FIG. 7 is a block diagram showing a conventional video signal clamp circuit. In the figure, (1) is a buffer amplifier for buffer-amplifying an input video signal, and (2) is a DC component from the input video signal. The DC blocking capacitors to be removed, (3) and (4), are resistors that determine the clamp voltage.

Further, (5) is a clamp voltage generation circuit, (6) is a sample hold circuit, (7) is a clamp pulse generation circuit which supplies a pulse for clamping to the sample hold circuit (6), and (8) is clamped. An A / D converter that converts a video signal into a digital value.

 Next, the operation will be described.

Analog input video signal (a) is buffer amplifier (1)
Buffer amplified by DC blocking capacitor (2)
DC component is removed by.

On the other hand, the clamp voltage is determined by the resistors (3) and (4) and guided to the sample hold circuit (6) through the clamp voltage generating circuit (5).

Further, the analog input video signal (a) is guided to a clamp pulse generating circuit (7) which separates a horizontal synchronizing portion and generates a pulse having a predetermined width and timing.

The clamp pulse generated by the clamp pulse generation circuit (7) is supplied to the sample hold circuit (6), and the video signal output from the DC blocking capacitor (2) is clamped at the timing based on this clamp pulse. Further, it is converted into a digital value by the A / D converter (8).

[Problems to be Solved by the Invention] Since the conventional video signal clamp circuit is configured as described above, the clamp voltage changes from the reference value due to changes in the characteristics of circuit elements due to heat or the like, fluctuations in the power supply voltage, and the like. There was a case where it was displaced, and it had to be adjusted each time, which was troublesome.

The present invention has been made to solve the above problem, and an object of the present invention is to obtain a video signal clamp circuit that can always control the clamp voltage to a constant value and supply a stable clamp voltage.

[Means for Solving the Problem] A video signal clamp circuit according to the present invention samples an A / D converter that receives a video signal and a pedestal portion of the video signal from the output of the A / D converter at a constant cycle. Sampling circuit, a comparison output circuit that outputs a value obtained by increasing or decreasing a previous output value by a constant value in accordance with the magnitude relationship between the output of the sampling circuit and the set reference value, and D that receives the output of the comparison output circuit as an input. A / A converter, a clamp voltage setting circuit that sets the pedestal level according to the output of the D / A converter, and a convergence condition that the output of the sampling circuit is in a specific range centered on the setting reference value. It is characterized by comprising a judging means for judging and a control operation adjusting circuit for suppressing the change of the clamp voltage when the convergence condition is satisfied.

[Operation] The video signal clamp circuit according to the present invention performs A / D conversion of the video signal by the A / D converter, and the convergence determination means determines the digital value and the reference set value of the predetermined portion of the A / D converted video signal. In comparison, a convergence determination signal having different polarities is output depending on whether the digital value is within a predetermined range centered on the reference set value, and the convergence determination signal output from the convergence determination means by the control operation adjusting means. Based on this, the clamp voltage adjustment control is started or stopped to stabilize the clamp voltage even when the S / N ratio of the video signal is poor.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, (1) is a buffer amplifier that buffer-amplifies an input video signal, and (2) is a DC blocking capacitor that removes a DC component from the input video signal.

Further, (5) is a clamp voltage generation circuit, (6) is a sample hold circuit, (7) is a clamp pulse generation circuit which supplies a pulse for clamping to the sample hold circuit (6), and (8) is clamped. An A / D converter that converts a video signal into a digital value.

Further, (9) is a first latch circuit that samples a predetermined position of the A / D converted video signal, and (10) compares the output of the first latch circuit (9) with a reference set value. It is a ROM that outputs a value based on the size and also operates as a convergence determination circuit to output a convergence determination signal (g).

And (11) is the second that latches the output of ROM (10).
Is a D / A converter for converting the output of the second latch circuit (11) into an analog value.

Further, (13) supplies the output of the D / A converter (12) to the first latch circuit (9), and (14) supplies the first latch circuit (9) with the level compression shift circuit composed of resistance elements in this embodiment. The latch pulse generation circuit outputs a latch pulse (c) having a predetermined timing to be output and a pulse (d) having an offset of a fixed period with respect to the latch pulse (c).

Further, (15) is a flip-flop circuit that latches the convergence determination signal (g) output from the ROM (10), (16) is a shift register circuit that receives the convergence determination signal and outputs a mask signal (h), (17) ) Is an AND gate for supplying a signal (i) obtained by gate-grating the pulse (d) with the mask signal (h) to the second latch circuit (11), which constitutes a control operation adjusting circuit (21). ing.

 Next, the operation of this embodiment will be described.

Analog input video signal (a) is buffer amplifier (1)
Buffer amplified by DC blocking capacitor (2)
The DC component is removed by and is clamped to a predetermined value through the sample hold circuit (6).

After that, it is converted into a digital value by the A / D converter (8) and becomes an output signal (b).

On the other hand, the input video signal (a) is also input to the latch pulse generation circuit (14) to separate the vertical synchronizing portion, and the pedestal portion of the output video signal (b) can be sampled 1
Appropriate latch pulse (c) of field (1/60 second) period
Then, a pulse (d) having an offset for a certain period with respect to the latch pulse (c) is output.

The pedestal portion of the output video signal (b) is the first latch circuit (9) at the timing of the latch pulse (c).
It is latched by and becomes the address of ROM (10).

Then, the output of the ROM (10) is the first latch circuit (1
1) and latched by signal (i) (second
See figure).

Further, the output (f) of the second latch circuit (11) is input to the D / A converter (12) and returned to the address of the ROM (10).

Then, in the ROM (10), the output (e) (current value) of the first latch circuit (9) is compared with the reference pedestal value,
When the output (e) of the first latch circuit (9) is smaller than the reference pedestal value, the second latch circuit (11)
The value (1) larger than the output (f) (value one field before) is output.

Similarly, if the output (e) of the first latch circuit (9) is larger than the reference pedestal value, a value 1 LSB smaller than the output (f) of the second latch circuit (11) is output. To do.

Separately from this, when the output (e) of the first latch circuit (9) becomes a value within the range of the reference pedestal value ± 1, the signal (g) which is “H” is output otherwise. To do.

For example, as shown in FIG. 3, the output (e) of the first latch circuit (9) is x, the output (f) of the second latch circuit (11) is y, and the reference clamp value is x ₀ , x. Y when ＝ x ₀
Let y _{0 be} the value of y and the output value of the ROM (10) be z, if z is at the position a, it is larger than x ₀ , so in the next field, one less than the current value z = y -1 (position a) is output.

Then, in the u position, this is greater than x ₀ , so in the next field the value z is one less than the current value.
= Y−1 (position of d) is output.

In this way, when you reach the position (x = x ₀ )
Output signal of (10) (hereinafter referred to as convergence determination signal) (g)
Becomes "L", the shift register circuit (16) is cleared, the mask signal (h) becomes "L", the pulse (d) is masked, and the signal (i) supplied to the second latch circuit (11) is supplied. ) Becomes “L”.

That is, ROM (1 when x converges to the range of x ₀ ± 1
The output of 0) is fixed. FIG. 4 is a timing chart showing the operation of the control operation adjusting circuit,
When the convergence determination signal (g) becomes "L", the latch pulse of the second latch circuit (11), that is, the signal (i) is stopped.

If the convergence determination signal (g) becomes “H”, the convergence operation is performed only when this state, that is, the state where x is out of the range of x ₀ ± 1 continues for a predetermined cycle (4 cycles in FIG. 4). It also shows how it will resume.

As described above, the digital data output from the second latch circuit (11) is converted into an analog value by the D / A converter (12) and converted per bit by the level compression shift circuit (13). Width is A / D converter (8)
Level is compressed so as to be smaller than the resolution per 1 bit of, and is level-shifted so as to swing around the convergent value, and is supplied as a clamp voltage through the clamp voltage generation circuit (5) and the sample hold circuit (6). .

Next, another embodiment of the present invention will be described with reference to FIG. The same parts as those described above are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 5, (18) is a shift register circuit and (1
9) is an inverter and (20) is an OR gate.

When the convergence determination signal (g) becomes "L",
That is, the value of the output (e) of the first latch circuit (9) is x
= X ₀ ± 1, the output () of the flip-flop circuit (15) becomes “H”.

When this "H" state continues for a predetermined cycle (4 cycles in this example), the output of the shift register circuit (18) becomes "H", and the shift register circuit (18) passes through the inverter (19) and the OR gate (20). 16) is cleared, the output of the shift register circuit (16) is set to “L”, the pulse (d) supplied to the second latch circuit (11) is masked, and the digital output of the second latch circuit (11). Fix the data (see Figure 6).

The output () of the flip-flop circuit (15) becomes "L", and the operation when the convergence operation is started again is as described above.

The clamp circuit may be any clamp circuit that controls the clamp voltage by using the digital value after A / D conversion.For example, the value of the difference between the digital value of the predetermined part of the video signal and the reference set value is fed back. It may be a clamp circuit that does.

Further, in the above-described embodiment, the convergence determination circuit is configured by using the shift register circuit or the like, but is not limited to this, and may be configured by using a circuit element such as a counter.

Further, the range of changing the polarity of the convergence determination may be set arbitrarily, and the same effect can be obtained even if the cycle value for starting and stopping the control operation adjusting circuit is set arbitrarily.

[Effects of the Invention] As described above, according to the present invention, different polarities are determined depending on whether the digital value of a predetermined portion of an A / D converted video signal is within a predetermined range centered on a reference set value. Since it is configured to start or stop the clamp voltage adjustment control based on the output convergence determination signal, the S /
Even if the N ratio is bad, the clamp voltage can be automatically stabilized, which can reduce coding errors and prevent image deterioration, and can be performed every time the clamp voltage deviates from the reference value. It is possible to save the trouble of adjusting.

[Brief description of drawings]

FIG. 1 is a block diagram showing the structure of a video signal clamp circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the timing of a latch pulse, FIG. 3 is a diagram showing the operation of the embodiment, and FIG. FIG. 5 is a timing chart showing the operation timing of the control operation adjusting circuit, FIG. 5 is a diagram showing the configuration of another embodiment of the present invention, and FIG. 6 is a timing chart of the operation of another embodiment of the present invention. Timing chart diagram,
FIG. 7 is a block diagram showing a configuration of a conventional clamp circuit. In the figure, (8) is an A / D converter, (10) is a convergence determining means, and (21) is a control operation adjusting means. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A video signal clamp circuit for controlling a pedestal level of a video signal so as to keep the pedestal level at a set reference value, and an A / D converter which inputs the video signal, and a pedestal of a video signal from the output of the A / D converter. Circuit for sampling a section at a constant cycle, a comparison output circuit for outputting a value obtained by increasing or decreasing a previous output value by a constant value in accordance with the magnitude relationship between the output of the sampling circuit and a set reference value, and the comparison output circuit D / A converter whose input is the output, a clamp voltage setting circuit that sets the pedestal level according to the output of the D / A converter, and an output of the sampling circuit that is centered around the setting reference value Determination means for determining a convergence condition of being in a range, and a control operation adjusting circuit for performing an operation of suppressing a change of the clamp voltage when the convergence condition is satisfied And a video signal clamp circuit comprising: