JPH05153429A - Clamping circuit - Google Patents

Abstract

PURPOSE:To shorten the time till clamping is made stable after, e.g. the application of power and to improve the convergence accuracy by supplying a current to a capacitor by turning on a switch when the level of a sampled signal is larger than the level of a reference signal. CONSTITUTION:This clamping circuit is provided with an amplifier circuit 2 amplifying a video signal from an image pickup element, an A/D converter 3 converting its output signal into a digital signal, a subtractor circuit 20 subtracting the output signal and a reference level, a D/A converter 8 converting the output signal into an analog signal and a sample-and-hold and integration circuit 9 integrating the output signal and a speed-up circuit 10 supplying a charge to the capacitor 9b of the sample-and-hold and integration circuit 9 when the output signal of the A/D converter 3 is larger than the reference level based on the comparison result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp circuit suitable for application to, for example, a video camera.

[0002]

2. Description of the Related Art Conventionally, a clamp circuit has been used in, for example, a color video camera.

A video camera, for example, amplifies signals from three CCDs (charge coupled devices) which are respectively responsible for red, green and blue components of light from an optical system by a preamplifier, and further, these red, green and blue components are amplified. The video signal of is amplified by a video amplifier, an image enhancer, and a process amplifier, respectively, and then subjected to various processes such as gamma correction and supplied to an encoder to be converted into, for example, an NTSC color video signal and output. ing.

The above-mentioned clamp circuit is arranged in a video amplifier together with a video amplifier, a gamma correction circuit and the like which can perform white balance adjustment and gain adjustment.

When white balance adjustment or gain adjustment is performed, the reference black level of the video signal fluctuates, which may cause a problem such that the black portion on the screen is out of balance and the image quality is deteriorated.

In order to prevent such an adverse effect, the clamp circuit plays a role of fixing one point of the waveform of the video signal to a constant potential.

FIG. 7 shows an example of this clamp circuit, and this clamp circuit will be described below.

In FIG. 7, reference numeral 1 denotes an input terminal to which a red, green or blue image signal is supplied from the above-described red, green or blue image pickup device, and the image signal of the amplifier circuit 2 is supplied via this input terminal 1. It is supplied to the non-inverting input terminal (+).

The output signal from the amplifier circuit 2, that is, the amplified video signal is converted into a digital video signal by the AD converter 3 and then supplied to the error detection circuit 4.

The error detection circuit 4 supplies the digital video signal from the A / D converter 3 to the digital process circuit (not shown) via the output terminal 5.

At the same time, the error detection circuit 4 determines whether or not the clamp phase digital code is larger than the reference code, and supplies the result (1 bit) to the integration circuit 6 as an error signal.

The integration circuit 6 integrates the error signal from the error detection circuit 4 and supplies the integration result to the inverting input terminal (-) of the amplification circuit 2.

In the clamp circuit of FIG. 7, the error signal p1 output from the error detection circuit 4 is as shown in FIG. 5C when the clamp phase for the video signal as shown in FIG. 5A is as shown in FIG. 5B. When this signal is supplied to the integrating circuit 6, the integrating circuit 6 changes it by a certain amount of change.

As shown in FIG. 5D, this change amount is the time Δ
The amount of change ΔFBL at t.

This change amount ΔFBL is the time constant of the integrating circuit 6, the output level of the error signal from the error detecting circuit 4,
It is determined by the gain of the amplifier circuit 2.

When the error signal p1 is supplied to the integrating circuit 6, the output from the integrating circuit 6 becomes a signal as shown in FIG. 5D.

As can be seen from FIGS. 5C and 5D, when the change amount ΔFBL is set to a large value, the level change from immediately after the clamp process to the next clamp process becomes large, and immediately after the clamp process and immediately before the clamp process. The difference in DC level between the two becomes large.

Therefore, in the prior art, the time constant of the integrating circuit 6 is increased or the output level of the error signal p1 from the error detecting circuit 4 is decreased.

That is, as shown in FIG. 4A, the level of the error signal from the error detection circuit 4 is reduced or the time constant of the integration circuit 6 is changed to immediately perform the clamp process as shown in FIG. 4B. The level change from one clamp to the next clamp is made small so that the difference between the DC levels immediately after the clamp and immediately before the clamp is not large.

[0020]

By the way, in the above clamp circuit, the output of the integrating circuit 6 is stable during operation.
For example, the signal is as shown in FIG. 6A.

In FIG. 6, Δt is the changing time,
ΔFBL is the change amount.

As shown in FIG. 6A, it can be seen that there is a degree of change, that is, a gradient of ΔFBL / Δt.

However, when the power is turned on or the like, the level of the control signal is substantially the ground level as shown in FIG. 6B.
The level rises with the same slope as in the case of the stable level.

Therefore, when the power is turned on, it takes a long time for the control signal to reach a stable level.

The present invention has been made in view of the above points, and it is an object of the present invention to propose a clamp circuit which can shorten the time from the power-on to the stabilization of the clamp operation and can improve the convergence accuracy. It is a thing.

[0026]

The clamp circuit of the present invention, as shown in, for example, FIGS. 1 to 6, includes a variable amplification means 2 for amplifying an output signal of an image pickup device, and an output signal of the variable amplification means 2 into a digital signal. A-D converter 3 for converting and this A
The subtracting means 20 for subtracting the output signal of the -D converter 3 and the digital code signal indicating the reference level, the DA converter 8 for converting the output signal of the subtracting means 20 into an analog signal, and the DA Integrating means 9 for integrating the output signal of the converter 8 and comparing means 12 for comparing the output signal of the AD converter 3 and the digital code signal indicating the second reference level.
And when the output signal of the AD converter 3 is larger than the second reference level based on the comparison result of the comparison means 12,
The charge storage means 9b of the integration means 9 is provided with a speed-up means 10 for supplying charges, and the output signal of the integration means 9 is supplied to the variable amplification means 2 as a gain control signal.

[0027]

According to the present invention described above, when the output signal of the AD converter 3 is larger than the second reference level based on the comparison result of the comparing means 12, the charge accumulating means 9 of the integrating means 9 is obtained.
Since the electric charge is supplied to b and the gain of the variable amplifying means 2 is changed by the output signal of the integrating means 9, for example, the time from the power-on to the stabilization of the clamp operation can be shortened, and the convergence accuracy can be improved. Can be improved.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the clamp circuit of the present invention will be described in detail below with reference to FIG.

In FIG. 1, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

The clamp circuit shown in FIG. 1 samples four reference black levels (see FIGS. 2A and 2B) of a video signal obtained by picking up an image with an image pickup device in a horizontal cycle, and codes the code as "020H" or This is a circuit that clamps to "040H".

In FIG. 1, reference numeral 1 denotes an input terminal to which a video signal from a red, green or blue image pickup device (not shown) is supplied, and a video signal imaged through the input terminal 1 (see FIG. 2A). ) Is the non-inverting input terminal (+) of the amplifier circuit 2.
Is supplied to.

The output video signal from the amplifier circuit 2 is A
It is supplied to the -D converter 3.

The input video signal supplied to the A / D converter 3 is sampled by the A / D converter 3 at the sampling clock shown in FIG. 2C to be a digital video signal (see FIG. 2D), and then output terminal. 5
Is supplied to the digital process circuit of the video camera to which the clamp circuit of this example is applied.

The digital video signal passed through this digital process circuit (not shown) is, for example, NT.
An SC encoder (not shown) converts it into an NTSC color video signal and outputs it to the outside.

On the other hand, the digital video signal from the A / D converter 3 is also supplied to the synchronous addition circuit 16.

The synchronous adder circuit 16 is composed of an adder circuit 17 and a D-type flip-flop circuit 18.

The digital video signal in the form of a 10-bit data string from the A / D converter 3 is supplied to the adder circuit 17 of the synchronous adder circuit 16. In the adder circuit 17, the 10-bit data string is successively output. For example, it is added four times to form a 12-bit data string and supplied to the D-type flip-flop circuit 18.

The D-type flip-flop circuit 18 latches a 12-bit data string based on a clock signal (see FIG. 2E) from the control unit of the video camera (not shown).

The output signal from the D-type flip-flop circuit 18 is supplied to the subtracting circuit 20, the comparator 12 and the adding circuit 17, respectively.

In the D-type flip-flop circuit 18, for example, if only one code is brought, noise will be added. Therefore, several codes are taken and the average thereof is obtained.

The 12-bit digital signal supplied to the subtraction circuit 20 is a digital control signal from the control unit of the video camera (not shown) from the input terminal 19,
For example, the subtraction process is performed with a hexadecimal data signal of “020H × 4” or “040H × 4”.

The 12-bit digital signal obtained as a result of this subtraction processing is supplied to the clipping circuit 21.

The clipping circuit 21 is a digital clipping circuit, and clips the 12-bit digital signal from the subtraction circuit 20 into a 3-bit digital signal, that is, a signal that indicates a 12-bit value with 3 bits. ..

The 3-bit output signal from the clip circuit 21 is supplied to the code conversion circuit 22.

The code conversion circuit 22 converts the 3-bit digital signal from the clip circuit 21 into a signal for the DA converter 8.

That is, when the 3-bit digital signal from the clipping circuit 21 is "100 (corresponding to +4)", it is converted into "111", and the 3-bit digital signal from the clipping circuit 21 is changed to "011 (+3)". Corresponding) ”
When it is, it is converted to "110", and when the 3-bit digital signal from the clip circuit 21 is "010" (corresponding to +2), it is converted to "101", and the 3-bit digital signal from the clip circuit 21 is converted. "001 (+1
(Corresponding to)), it is converted into "100", and the 3-bit digital signal from the clipping circuit 21 is converted into "000".
When it is "corresponding to 0", it is converted into "011", and the 3-bit digital signal from the clipping circuit 21 becomes "1".
11 (corresponding to -1) "is converted to" 010 ", and when the 3-bit digital signal from the clipping circuit 21 is" 110 (corresponding to -2) "," 001 ".
When the 3-bit digital signal from the clipping circuit 21 is "101 (corresponding to -3)", it is converted to "0".
00 ".

The 3-bit conversion output (see FIGS. 2F and 2G) from the code conversion circuit 22 is converted into an analog signal (see FIG. 2H) by the DA converter 8.
This is supplied to the gate circuit 23.

This gate circuit 23 turns on / off the switch 25 by a switching pulse (see FIG. 2J) supplied from an input terminal 24 from a control unit of a video camera (not shown), and is shown in FIG. 2H. The output signal of the DA converter 8 is gated.

This switching pulse corresponds to the clamp portion. In other words, the signal indicating the position where the correction amount can be captured can be used to correct the video signal only in the reference black level period shown in FIG. 2B.

That is, in the case where the gate circuit 23 is not provided, as shown in FIG. 2I, a signal which has been converted into an analog signal by the DA converter 8 is supplied to the sample hold and integration circuit 9 during the video period of the video signal. In this case, unless the integration time constant is made considerably longer than the clamp period, the DC level difference immediately before and immediately after the clamp becomes large.

However, if the time constant is set to a large value, it will take some time for the clamp to come off once and to reach the original stable operation level again.

Therefore, in this example, the gate circuit 23 reduces the fluctuation of the DC level of the video portion of the video signal.

The signal gated by the gate circuit 23 is supplied to the sample hold and integration circuit 9.

This sample hold and integration circuit 9
As shown in this figure, it is composed of a resistor 9a and a capacitor 9b.

The output from the sample hold and integration circuit 9 is supplied to the inverting input terminal (-) of the amplification circuit 2 as a control signal (see FIG. 2K).

That is, as shown in FIG. 2K, the gate circuit 2
DC of the video part of the video signal by the gate processing by 3
A control signal with little level fluctuation is output from the sample hold and integration circuit 9.

The control operation of the amplifier circuit 2 by this control signal is determined by the time constants of the resistor 9a and the capacitor 9b of the sample hold and integration circuit 9.

When this control signal is supplied to the amplifier circuit 2, the level of the video signal supplied from the input terminal 1 is changed according to the level of this control signal.

That is, the video code output from the AD converter 3 is added four times with the clock shown in FIG. 2C. An average value can be obtained by dividing this by 4, but since the number of samplings is known, it is sufficient to compare with a code multiplied by 4.

Therefore, the code to be clamped from the added code, that is, "020H" or "040"
4 times of H ″ is subtracted, the high-frequency part is clipped in order to convert this into 3-bit data, and code conversion is further performed for the DA converter 8.

After this is converted into an analog signal by the D / A converter 8, gate processing is performed and integration is performed to DC clamp.

On the other hand, when a 12-bit digital signal is supplied to the comparator 12 which constitutes the speed increasing circuit 10, it is compared with a reference code or the like from the controller of the video camera (not shown) via the input terminal 11. And outputs the comparison result as a switching pulse of the switch 14.

This reference signal is variable, for example 1
With the hexadecimal code “0A0H × 4”, the comparator obtains the level difference between this code and the 12-bit digital signal, and when this level difference is large, the switching pulse supplied to the switch 14 is set to, for example, a high level “1”, Close the switch.

Now, one fixed contact of the switch 14 is connected to, for example, the terminal 13 to which a positive power is supplied, and the other fixed contact is connected via the resistor 15 to the capacitor 9b which constitutes the sample hold and integration circuit 9. Are connected in series.

When the switch 14 is on, a current from the power supply terminal 13 flows into the capacitor 9b via the switch 14 and the resistor 15, and this current is charged in the capacitor 9b.

Therefore, when the switch 14 is on,
Since the capacitor 9b is charged with the current from the power supply terminal 13 and the input signal current, the control signal from the gate circuit 23 is supplied to the amplifier circuit 2 regardless of the time constants of the resistor 9a and the capacitor 9b.

That is, in the amplifier circuit 2, the level control processing can be quickly performed on the input video signal.

Here, as shown in FIG.
Is on, the current flowing through the resistor 15 is
I is the current flowing through the capacitor, and the current flowing into the capacitor 9b is i.
In the stable state, the current i is off and the current i is
c = current i, the slope of ΔFBL / Δt becomes a normal slope, and the level of the control signal rises with this slope.

On the other hand, when the clamp of the switch 14 is largely disengaged (when the power is turned on, etc.), the switch 14 is turned on, and the current ic = the current is + the current i, so ΔFBL /
The slope of Δt becomes large, and the convergence becomes faster.

As described above, in this example, when the level difference in the comparator 12 is large, the switch 14 is turned on, and the current from the power supply terminal 13 flows into the capacitor 9b, thereby increasing the inclination and stabilizing the level. I try to increase the speed to reach.

Here, in order to correspond to FIG. 7 which is a conventional example, a block diagram in which the clamp circuit of this example shown in FIG. 1 is simplified (the gate circuit 23 shown in FIG. 1 is excluded. ) Is shown in FIG. 3, and also with reference to FIG. 5, the reason why the above-described clip circuit 21 sets, for example, 3 bits and a plurality of bits will be described.

As shown in FIG. 3, in this example, the video signal supplied to the input terminal 1 is converted into digital data by the A / D converter 3, and the digital data is omitted from the output terminal 5. The error detection circuit 7 is supplied to the digital process circuit of the video camera (that is, from the synchronous addition circuit 16 to the code conversion circuit in FIG. 1).
Thus, the digital video signal is converted into a 3-bit digital signal, the D-A converter 8 converts it into an analog signal, and the integration circuit 9 integrates the analog signal.

In the prior art, since there was only a 1-bit data string at the time of digital data before the analog control signal, as shown in FIG. 5, the output from the error detection circuit 4 (see FIG. 7). The level of the signal p1 is "1"
Or “0”, and as shown in FIGS. 7 and 5D,
The slope of the control signal p2 output from the integrating circuit 6, that is,
The amount of change ΔFBL / time Δt becomes relatively large.

However, if the slope is increased, the difference between the DC levels immediately after the clamp and immediately before the next clamp becomes large. Therefore, the slope is reduced by changing the time constant of the integrating circuit 6 and the like.

However, for example, when the power is turned on,
When the clamp is largely disengaged, it takes time to converge due to the small inclination.

Therefore, in this example, as shown in FIGS. 1 and 3, the 3-bit digital control signal is converted into an analog signal, integrated, and output as a signal for controlling the amplifier circuit 2.

As shown in FIG. 5E, in FIG.
Since the signal p3 supplied to the DA converter 8 is a signal having a plurality of potentials, the output p4 obtained by integrating this is as shown in FIG. 5F.

For example, Δ when the lower 1 bit changes
If FBL is set in the same manner as in 1 bit, a gain of ± 4 times that in 1 bit can be obtained when the clamp is most off.

That is, as shown in FIG. 4, for example, when there is an output from the DA converter 8 as shown in FIG. 4C, the conventional clamp circuit attains a stable operation level with a slope as shown by py in FIG. 4D. The clamp circuit of the present example converges to a stable operation level with a slope as shown by px in FIG. 4D (four slopes can be selected above and below the signal py).

As is apparent from FIG. 4D, only by changing the error signal from the error detection circuit 7 from 1 bit to 3 bits, a gain of ± 4 times that in the case of 1 bit can be obtained, It is less susceptible to noise, is effective even when signals are switched, and converges significantly faster.

That is, as the number of bits is increased, ΔFBL / Δt corresponding to the error is obtained, so that oscillation can be prevented and the convergence time can be shortened to perform accurate feedback clamp.

As described above, in this example, when the sampled signal level is higher than the reference signal, the switch 14 is turned on to flow the current into the capacitor 9b. Therefore, for example, the clamp operation is performed after the power is turned on. It is possible to shorten the time until stabilization and improve the convergence accuracy.

In the above example, since the relationship between the level at power-on and the level at stable operation is defined in advance, only the rising side is dealt with, but if it is also added to the falling side, something will happen. Even if the clamp is largely disengaged due to the influence of, the convergence time can be shortened by the operation of the speed increasing circuit 10.

Further, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0085]

According to the present invention described above, when the output signal of the AD converter is larger than the second reference level based on the comparison result of the comparison means, the charge is stored in the charge storage means of the integration means. Since the gain of the variable amplifying means is supplied and the gain of the variable amplifying means is varied according to the output signal of the integrating means, it is possible to shorten the time from the power-on to the stabilization of the clamp operation and to improve the convergence accuracy. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clamp circuit according to the present invention.

FIG. 2 is a timing chart for explaining an embodiment of the clamp circuit of the present invention.

FIG. 3 is a block diagram for explaining an embodiment of the clamp circuit of the present invention.

FIG. 4 is a timing chart provided for explaining an embodiment of the clamp circuit of the present invention and an example of a conventional clamp circuit, respectively.

5A and 5B are explanatory diagrams respectively provided for explaining one embodiment of the clamp circuit of the present invention and an example of a conventional clamp circuit.

FIG. 6 is an explanatory diagram for explaining an example of a conventional clamp circuit.

FIG. 7 is a block diagram showing an example of a conventional clamp circuit.

[Explanation of symbols]

 2 amplification circuit 3 A-D converter 8 D-A converter 9 sample hold and integration circuit 10 speed increase circuit 12 comparator 16 synchronous addition circuit 20 subtraction circuit 21 clip circuit 22 code conversion circuit 24 gate circuit

Claims (1)

[Claims] 1. A variable amplification means for amplifying an output signal of an image pickup device, an AD converter for converting an output signal of the variable amplification means into a digital signal, an output signal of the AD converter and a reference level. Subtracting means for subtracting a digital code signal indicating the above, and DA for converting an output signal of the subtracting means into an analog signal
A converter; an integrating means for integrating the output signal of the DA converter; a comparing means for comparing the output signal of the AD converter with a digital code signal indicating a second reference level; Speed-up means for supplying charges to the charge storage means of the integration means when the output signal of the AD converter is higher than the second reference level based on the comparison result of the means. A clamp circuit, wherein the output signal of the means is supplied to the variable amplification means as a gain control signal.