JPH0360579A - Video signal clamp circuit - Google Patents

Abstract

PURPOSE:To obtain a highly accurate clamp voltage even when the S/N of a video signal is deteriorated by stopping the convergence when a digital data at a clamp point is equal to a reference value and restarting the convergence when the data is at the outside of the prescribed range around the reference value consecutively for a prescribed cycles or over. CONSTITUTION:A ROM 10 compares an output (e) of a latch circuit 9, that is, a current output with a reference pedestal and outputs an output (f) of a latch circuit 11 when the output (e) is smaller than the reference and outputs a value smaller than the output (f) by 1LSB when the output (e) is larger. Moreover, the output goes to L when the reference value is equal to the output (e), and a latch pulse of the latch circuit 11 is stopped. An operation selection switch 18 outputs a convergence signal when a mask signal (h) is at H and outputs a convergence discrimination signal (g) when the mask signal (h) is at L. Thus, the convergence is restarted when a state of (x) deviated from a range of xo + or -1 is consecutive for a prescribed cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal clamp circuit that always maintains a clamp voltage of a video signal at a constant level.

[Conventional technology]

FIG. 5 is a diagram showing a conventional clamp circuit. In the figure, 1 is a buffer amplifier, 2 is a DC blocking capacitor, and 3 is a DC blocking capacitor.
．． 4 is a resistor that determines the clamp voltage, 5 is a clamp voltage generation circuit, 6 is a sample and hold circuit, 7 is a clamp pulse generation circuit that supplies clamping pulses to the sample and hold circuit 6, and 8 is a circuit that generates a clamped video signal. This is an A/D converter that converts into digital values.

Next, the operation will be explained.

An analog input video signal a is buffer-amplified by a buffer l, and a DC component is removed by a DC blocking capacitor 2. The clamp voltage is determined by a resistor 3.4 and is led to a sample and hold circuit 6 through a clamp voltage generation circuit 5. On the other hand, the analog input video signal a separates the horizontal synchronization portion and is guided to a clamp pulse generation circuit 7 which generates pulses of appropriate width and timing. A clamp pulse generated by the clamp pulse generating circuit 7 is supplied to the sample hold circuit 6, and at this timing, the video signal output from the DC blocking capacitor 2 is clamped and converted into a digital value by the A/D converter 8. be done.

[Problem to be solved by the invention]

Conventional video signal clamp circuits are configured as described above, but the problem is that the clamp voltage may deviate from the reference value due to variations in circuit elements or fluctuations in power supply voltage, and adjustment is required each time. was there.

This invention was made to solve the above-mentioned problems, and aims to provide a video signal clamp circuit that can always control the clamp voltage to a constant value and supply a stable lamp voltage. There is.

[Means to solve the problem]

The video signal clamp circuit according to the present invention has an A
A convergence judgment circuit and an operation selection switch are attached to the clamp circuit to control the clamp voltage using the digital value after /D conversion, and the convergence operation is started.

It is configured to control stopping.

[Effect]

In this invention, the convergence judgment circuit and the operation selection switch stop the convergence operation when the digital data of the clamp point is equal to the reference value, and when the digital data of the clamp point deviates from the predetermined range centered on the reference value continuously for more than a predetermined cycle. Since the device is configured to operate so as to restart the convergence operation, it is possible to automatically supply a stable and highly accurate lamp voltage even when the S/N ratio of the video signal is poor.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a video signal clamp circuit according to an embodiment of the present invention. In the figure, the same symbols as in FIG. 5 are the same or corresponding parts, and 9 is a video signal after A/D conversion. latch circuit sampling a fixed position of 10
1 is a ROM that compares the output e of the latch circuit 9 with a reference value and outputs a value according to the magnitude thereof; 11 is a latch circuit that latches the output of ROM10; 12 is a latch circuit that converts the output of the latch circuit 11 into an analog value. It is a D/A converter.

13 level compresses the output of the D/A converter 12.

This is a level compression shift circuit that shifts, and in this embodiment, it is realized by a resistor element. 14 is a latch pulse generation circuit that outputs latch pulses c and d at appropriate timings to the latch circuit 9 and 11; 15 is a flip-flop circuit that latches the convergence signal or convergence judgment signal g output from the ROM 10; and 16 is a convergence signal. or a shift register circuit which receives the convergence determination signal g and outputs a mask signal; 17 is an AND gate that gates the latch pulse supplied to the latch circuit 11 with the mask signal; 18 is an AND gate that gates the latch pulse supplied to the latch circuit 11;
This is an operation selection switch that switches between a convergence signal and a convergence determination signal g.

Next, the operation will be explained.

The input video signal passes through a buffer 1, has its DC component cut off by a capacitor 2, and passes through a sample hold circuit 6 where it is clamped to a certain value. Thereafter, it is converted into a digital value by the A/D converter 8 and becomes an output video signal. In addition, the input video signal a is the latch pulse generation circuit 14
The vertical synchronization part is separated here, and an appropriate latch pulse C with a period of 1 field (1/60 seconds) that can sample the pedestal part of the output video signal, and a certain period of time with respect to the latch pulse C are Outputs a latch pulse d with an offset. The pedestal portion of the output video signal is latched by the latch circuit 9 at the timing of the latch pulse C, and becomes the address of the ROM10. ROMl
The output of 0 is input to the latch circuit 11, and the latch pulse d
is latched. This situation is shown in FIG.

The output f of the latch circuit 11 is input to the D/A converter 12 and is returned to the address of the ROM10. R
In OMl0, the output e of the latch circuit 9, that is, the current value, is compared with the reference pedestal value, and if the output e is smaller than the reference value, the output f of the latch circuit 11, that is, the value before the l field, is compared by ILSB. Output a large value. Similarly, if the output e is larger than the reference value, the output f
A value smaller by ILSB than that is output. In addition, ROM10 also has a convergence signal that becomes "L" if the output e is equal to the reference value and "H" if it is not equal, and a convergence signal that becomes "u" if the output e becomes a value within the reference value ±1.
L II, and outputs a convergence determination signal g that is "H" for other values. Also, the operation selection switch 18
outputs a convergence signal when the mask signal is “H”,
When the mask signal is "L", a convergence determination signal g is output.

Figure 3 is a diagram showing this situation, where the value of the output e is
The output f value is y, and the reference clamp value is X (11X!
Let the value of y be )r, and the output value of ROM10 be Z
For example, if X is at position A, this is larger than xo, so in the next field, a value z-y-1, which is one smaller than this time, is output (position A). Next, if X reaches the value shown at position 1, this is still larger than X6, so the value z-y-1 (position position), which is one smaller than the previous value (one field before), is output. be done. In this way, X will eventually reach the O position (X *
.

, the convergence signal becomes L due to the output of ROMLO.
'', the shift register circuit I6 is cleared, the mask signal becomes °L'', the latch pulse d supplied to the latch circuit 11 is masked, and the output of the operation selection switch 18 is switched. That is, the output y0 of the ROM 10 when X converges to Xo is fixed.

FIG. 4 is a timing chart showing the operation of the convergence determination circuit, and shows how the latch pulse of the latch circuit 11 stops as described above when the convergence signal, which is the output of ROM10, becomes "L". .

Furthermore, if the convergence determination signal g, which is the output of ROM10, becomes H'', then in this state, that is, X is X.

) A state that deviates from the range of ±1 is a predetermined cycle (°4th
The diagram also shows how the convergence operation is restarted only when the convergence operation continues (4 cycles in the figure). The level is compressed by the compression shift circuit I3 so that the conversion width per bit is smaller than the resolution per bit of the A/D converter 8, and the level is shifted so that the convergence value is centered, and the clamp voltage generation circuit 5. It is supplied as a clamp voltage through the sample and hold circuit 6.

Note that the clamp circuit excluding the convergence judgment circuit is not limited to the one shown in the above embodiment, but can be any other type of lamp circuit that controls the clamp voltage using a digital value after A/D conversion. For example, it goes without saying that it may be a lamp circuit or the like that feeds back the value of the difference between the digital value of a predetermined portion of the video signal and a reference setting value.

Further, in the above embodiment, the convergence determination circuit is configured using a shift register circuit or the like, but it may also be configured using other circuit elements such as a counter. Further, the predetermined range for making the polarity of the convergence determination signal different may be set arbitrarily, and the same effect can be obtained even if the predetermined cycle value for starting the operation of the convergence determination circuit is arbitrarily set.

〔Effect of the invention〕

As described above, according to the present invention, when the digital data at the clamp point is equal to the reference value, the convergence operation is stopped using the convergence determination circuit and the operation selection switch. Since the convergence operation is restarted when the video signal goes out of a predetermined range, the S/
Even when the N ratio is poor, it is possible to automatically obtain a stable and highly accurate lamp voltage.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a video signal clamp circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing latch pulse timing, FIG. 3 is a diagram showing the operation of the above embodiment, and FIG. 4 is a diagram showing the above embodiment. FIG. 5 is a diagram showing the operation timing of the convergence determination circuit according to an example, and FIG. 5 is a diagram showing a conventional video signal clamp circuit. 8 is an A/D converter, 9.11 is a latch circuit, 10 is a ROM, 12 is a D/A converter, 13 is a level compression shift circuit, 14 is a latch pulse generation circuit, 15 is a field circuit, 16 is a shift register circuit, 17 is an AND gate, and 18 is an operation selection switch. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A video signal clamping circuit that A/D converts a video signal and uses the digital value of a predetermined portion of the obtained video signal to control and clamp the predetermined digital value so that it matches a reference setting value, as described above. means for comparing a predetermined digital value with the reference setting value and outputting a convergence signal having a different polarity depending on whether the predetermined digital value is equal to or not equal to the reference setting value; means for outputting a convergence determination signal having a different polarity depending on whether the value is within a predetermined range or outside the range; and a convergence operation when the convergence signal and the convergence determination signal are converged. A video signal clamp characterized by comprising: a signal switching means for switching between the two cases, and a means for starting and stopping a control operation using the convergence signal or the convergence determination signal output from the signal switching means. circuit.