JP2006229544A - Image signal dc voltage stabilization circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit which analog-processes an image signal for a digital conversion, wherein the black level of the image signal is stably fixed without exceeding a predetermined level. <P>SOLUTION: When a signal of a black reference period is extracted during a horizontal blanking period of an output digital signal of an A/D converter 3, an addition average circuit 4 is controlled by a counter 5, thereby sequentially adding and averaging within the black reference period in the output digital signal of the A/D converter 3 for outputting. Also, a value obtained by D/A-converting a difference between the output value and a clamp level set value is compared with a reference value in a subtraction circuit 9 during the clamp pulse active period, the result is output to a control terminal 2a of a DC control circuit 2, and a DC voltage is controlled during the black reference period in a signal to input to the A/D converter 3 according to a magnitude of a terminal voltage of the control terminal 2a. Such a loop is constituted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a video signal DC voltage stabilization circuit provided in a CCD camera, a copying machine, an image scanner device, a television device, a video tape recorder device, and other video equipment, and more particularly, a CCD (Charge Coupled Devices). ) Video that stabilizes DC voltage when A / D converting video signal such as area sensor output signal, CCD linear sensor output signal, CMOS sensor output signal, television signal, video signal, RGB signal, etc. The present invention relates to a signal DC voltage stabilizing circuit.

  Conventionally, as this type of technique, there is a technique disclosed in Patent Document 1, which includes a black reference period in a signal obtained by clipping the upper bits of an output digital signal of an A / D converter by a clipping circuit. A binary average data of at least two of the above is obtained by an averaging circuit, a difference between the average value and the clamp level setting value is D / A converted by the D / A converter, and the D / A converter The capacitor is charged / discharged according to the magnitude of the comparison result with the intermediate voltage of the reference voltage, and a loop for controlling the DC voltage of the black reference period in the signal input to the A / D converter according to the voltage of the capacitor is formed. Thus, the signal that the fluctuation of the DC voltage during the black reference period in the output digital signal of the A / D converter is reduced and stabilized. It has been described for flow voltage stabilizer.

  FIG. 4 is a block diagram of a conventional video signal DC voltage stabilization circuit, and FIG. 5 is a timing diagram showing the operation of the video signal DC voltage stabilization circuit of FIG.

  As shown in FIG. 5, an input analog video signal has an effective period in which a video signal exists and a horizontal blanking period in which no video signal exists in one horizontal period. There is a black reference period, which is the black reference. As shown in FIG. 5, the clamp pulse described later has an active period in the black reference period of the input analog video signal.

  As shown in FIG. 4, the input analog video signal is amplified by a fixed gain or variable gain amplifier 1 to optimize the amplitude, and further, a control terminal in a DC control circuit 2 defining the DC voltage of the output analog video signal. The DC voltage of the amplifier 1 is optimized according to the control terminal voltage applied to 2a, and further converted to a digital signal at the conversion speed according to the input clock in the A / D converter 3. In this way, the input analog video signal is output as a digital signal synchronized with the clock. The relationship between this clock and the input analog video signal is as shown in FIG.

  The digital signal output from the A / D converter 3 is added and averaged by the clamp pulse rate addition averaging circuit 6 for the conversion period within the active period starting from the front edge of the clamp pulse (FIG. 5), and the data is determined. , And output as a digital signal having a period of the clamp pulse. This digital signal is input to the digital subtraction circuit 7, and is subtracted from the clamp level setting value data obtained by adding a predetermined digital value to the arbitrarily set clamp level setting code and output. The digital signal output from the digital subtraction circuit 7 is converted into analog data 8 a by the D / A converter 8.

  The analog data 8a output from the D / A converter 8 is compared with a reference voltage 10 corresponding to a predetermined digital value by a subtraction circuit 9. When the comparison result is larger than the reference voltage 10, the capacitor 11 is charged, the control terminal voltage applied to the control terminal 2a of the DC control circuit 2 is increased, and the DC voltage of the analog video signal input to the A / D converter 3 is increased. To raise. Conversely, when the comparison result is smaller than the reference voltage 10, the analog video signal input to the A / D converter 3 by discharging the capacitor 11 and lowering the control terminal voltage applied to the control terminal 2 a of the DC control circuit 2. Decrease the DC voltage.

With the above operation, the black level of the output digital video signal of the A / D converter 3 is maintained at a predetermined level set arbitrarily.
JP 2003-23549 A JP-A-8-98057

  According to the conventional video signal DC voltage stabilizing circuit, as shown in the timing chart of FIG. 5, the analog data 8a output from the D / A converter 8 during the operation of the subtraction circuit 9 is clamped one cycle before. A digital signal obtained by averaging within the active period of the pulse is subtracted from the clamp level set value data and is converted to an analog value by the D / A converter 8. Therefore, when there is a relatively large difference between this value and the reference voltage 10, the change of the control terminal 2a continues according to the difference, and the DC voltage of the analog video signal input to the A / D converter 3 is optimum. The black level of the digital video signal output from the A / D converter 3 cannot be maintained at a predetermined level that is arbitrarily set and becomes unstable, and the video is disturbed while the black color is shifted during that time. May occur.

  In order to solve such problems, circuits as shown in FIGS. 6 and 7 have been proposed. 6 and 7 are disclosed in Patent Document 2. FIG.

  According to the circuit shown in FIG. 6, after the input analog signal is amplified by the amplifier 51, an analog video signal having no DC component is extracted by the sample and hold circuit 52. One end of a capacitor 53 is connected to the output end of the sample hold circuit 52 from which the analog video signal is output, and a switch 54 and an A / D converter 55 are connected to the other end (point A) of the capacitor 53. Has been.

  The clamp pulse generation circuit 56 generates a clamp pulse having an active period in the horizontal blanking period, the switch 54 is closed and turned on, the capacitor 53 is charged, and the DC voltage of the analog video signal is the optimum value at point A. Fixed to. The analog video signal is converted into a digital signal by the A / D converter 55 and output. This digital signal is input to the error detection circuit 57, and a correction potential value for correcting the black level to a value that should be fixed is extracted. After the high frequency noise is removed by the loop filter 59, the analog signal is obtained by the D / A converter 58. The correction potential value is fed back to the point A while the switch 54 is closed and turned on, so that the black level of the digital video signal reaches a value that is originally fixed.

  However, the loop filter 59 in the digital processing constituting the circuit shown in FIG. 6 has a relatively large circuit scale even if it is a horizontal filter, and if it becomes a vertical filter or a time filter, a line memory or a frame memory is required. Therefore, there is a problem that the circuit becomes extremely large and the area when mounted on a semiconductor integrated circuit becomes large.

  On the other hand, in the circuit shown in FIG. 7, the loop filter 59 is arranged after the D / A converter 58 so as to perform analog processing by a simple RC circuit, and the same effect as the circuit shown in FIG. 6 is achieved.

  However, in the circuit configuration shown in FIG. 7, since the frequency band of the digital correction potential value input to the D / A converter 58 is high, the D / A converter 58 must have high frequency characteristics and power consumption. Has the problem of increasing.

  The present invention solves such problems, and can stably fix the black level of a video signal to a predetermined level to suppress image disturbance and can realize a relatively small circuit scale. An object is to provide a DC voltage stabilizing circuit.

  In order to achieve the above object, the present invention provides an A / D converter by controlling an averaging circuit with a counter circuit when extracting a signal of a black reference period in a horizontal blanking period of an output digital signal of an A / D converter. Of the output digital signal is sequentially added and averaged within the black reference period, and the result obtained by comparing the value obtained by D / A conversion of the difference from the clamp level setting value data with the reference voltage in the clamp pulse active period in the subtraction circuit A loop for controlling the DC voltage in the black reference period in the signal input to the A / D converter according to the size of the A / D converter is formed.

  According to such a configuration, a negative feedback loop is formed in real time during the subtraction circuit operation of the same clamp pulse period, and the DC voltage (black level) of the black reference period in the output digital signal of the A / D converter is set. Acts to always match the given value.

  Hereinafter, each claim will be described.

  According to a first aspect of the present invention, there is provided a video signal direct current stabilization circuit that amplifies an input analog video signal and direct current control that defines a direct current voltage of the output analog video signal of the amplifier according to a control terminal voltage applied to a control terminal. A circuit, an A / D converter that converts an analog video signal output from the DC control circuit into a digital signal at a predetermined conversion frequency, and outputs a black signal during a horizontal blanking period of the input analog video signal. Starting from the leading edge of the clamp pulse existing in the reference period, within a range of the black reference period in the horizontal blanking period, a predetermined number of the A / D converters that are at most ½ or less of the black reference period A counter circuit that repeats counting for a conversion period, and from the A / D converter under the control of the counter circuit A digital signal output from the addition averaging circuit from a digital data obtained by adding a predetermined digital value to an arbitrarily set clamp level setting code. A subtracting circuit, a D / A converter for converting digital data output from the digital subtracting circuit into analog data, and an analog data output from the D / A converter during an active period of the clamp pulse. A subtracting circuit that has a capacitor that is charged and discharged according to a subtraction result obtained by subtracting a reference voltage corresponding to a predetermined digital value, and that generates a control terminal voltage of the DC control circuit in proportion to the voltage of the capacitor. Yes.

  According to this configuration, the black level of the video signal can be stably converged to a predetermined level without using a D / A converter with high frequency characteristics or a loop filter with a large circuit scale.

  The video signal direct current stabilization circuit according to claim 2 of the present invention is the signal direct current stabilization circuit according to claim 1, wherein the addition averaging circuit counts a predetermined number of times while the counter circuit is counting. Digital signals output from the A / D converter for the conversion period are sequentially averaged and output.

According to this configuration, when there is a difference between the D / A converter output and the reference voltage value during the subtraction circuit operation, and the control terminal changes according to the difference, the D / A converter output is Since the data obtained by sequentially adding and averaging the black reference period signals in the output digital signal of the A / D converter that changes according to the change is reflected when the data of the subsequent averaging circuit is determined, the black level of the video signal exceeds the convergence point. Without being fixed at a predetermined level.

  The video signal direct current stabilization circuit according to claim 3 of the present invention is the signal direct current stabilization circuit according to claim 2, wherein the predetermined number of conversion cycles sequentially added and averaged by the averaging circuit is made binary.

  According to this configuration, the division process after the addition can be realized by shifting the bits, and the circuit scale can be reduced.

  The video signal direct current stabilization circuit according to claim 4 of the present invention is the signal direct current stabilization circuit according to claim 1, wherein the addition averaging circuit counts a predetermined number of times while the counter circuit is counting. The digital signals output from the A / D converter are sequentially added and averaged for the conversion period, and at least one of the added average value and the added average value for the predetermined number of conversion periods immediately before and the total predetermined number The average is sequentially added and output.

  According to this configuration, the number of addition averages increases without changing the output cycle of the addition average circuit, so that the influence of fluctuation factors such as noise can be further alleviated.

  The video signal direct current stabilization circuit according to claim 5 of the present invention is the signal direct current stabilization circuit according to claim 4, wherein a predetermined number of conversion periods sequentially added and averaged by the addition average circuit and an addition average for further averaging. A predetermined number of values is converted into a binary number.

  According to this configuration, the division process after the addition can be realized by shifting the bits, and the circuit scale can be reduced.

  According to the video signal DC voltage stabilization circuit of the present invention, since the black level of the video signal is stably converged without exceeding a predetermined level, there is an effect that a high-quality video without image disturbance can be obtained.

  Furthermore, since it is not necessary to use a D / A converter with high frequency characteristics, it has the effect of realizing a video signal DC voltage stabilizing circuit with relatively low power consumption.

  Further, as the averaging circuit, while the counter circuit is counting, the digital signals output from the A / D converter are sequentially added and averaged for a predetermined number of conversion cycles to be counted, and the average value and the immediately preceding average value are further calculated. At least one addition average value for a predetermined number of conversion periods and a total of a predetermined number are sequentially added and averaged to further reduce the influence of fluctuation factors such as noise, thereby reducing the black level of the video signal to a predetermined level. Therefore, it is possible to obtain a high-quality video image with a stable black level.

  Furthermore, since it is not necessary to use a loop filter, the circuit configuration is relatively small. In addition, a predetermined number of conversion periods sequentially added and averaged in the averaging circuit and a total number of addition average values to be added and averaged are binary numbers. In this way, the division processing after the addition can be realized by shifting the bits in the averaging circuit, and the circuit scale is further reduced, resulting in power saving. Therefore, the video signal direct current can be easily mounted on a semiconductor integrated circuit and is suitable for industrial mass production. This has the effect of realizing a voltage stabilization circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing a circuit configuration of a video signal DC voltage stabilizing circuit according to a first embodiment of the present invention, wherein 1 is a fixed gain or variable gain amplifier, 2 is a DC control circuit, and 2a is a DC control circuit. 2 is a control terminal, 3 is an A / D converter, 4 is an averaging circuit, 5 is a counter, 7 is a digital subtraction circuit, 8 is a D / A converter, 9 is a subtraction circuit, 10 is a reference voltage source, and 11 is a capacitor is there.

  FIG. 2 is a timing chart showing the operation of the video signal DC voltage stabilizing circuit of FIG.

  As shown in FIG. 2, the input analog video signal has an effective period in which the video signal exists in one horizontal period and a horizontal blanking period in which no video signal exists. There is a black reference period, which is the black reference. In the clamp pulse described later, as shown in FIG. 2, an active period exists in the black reference period of the input analog video signal.

  As shown in FIG. 1, the input analog video signal is amplified by an amplifier 1 having a fixed gain or a variable gain, the amplitude is optimized, and the output analog video signal of the amplifier 1 is further applied according to the control terminal voltage applied to the control terminal 2a. The DC voltage is optimized by the DC control circuit 2 that regulates (clamps) the DC voltage. The input analog video signal is converted into a digital signal by the A / D converter 3 at a conversion speed according to the input clock, and is output in synchronization with the clock. This clock and the input analog video signal have a relationship as shown in FIG.

  The counter 5 starts at the front edge of the clamp pulse, and at least two or more that are at most 1/2 or less of the black reference period within the range of the black reference period in the horizontal blanking period of the input analog video signal. The count of the clock for converting the A / D converter 3 of a predetermined binary number (a power of 2 (2 to the power of n)) such as 2, 4, 8,... Is repeated.

  Under the control of the counter 5, the averaging circuit 4 sequentially adds and averages the digital signals output from the A / D converter 3 for the conversion period of a predetermined binary number to be counted while the counter 5 is counting. The digital signal output from the A / D converter 3 is output as a digital signal having a frequency that is one-fifth of the average of the addition averages, and this digital signal is input to the digital subtraction circuit 7.

  When the output signal of the averaging circuit 4 matches the clamp level setting code with respect to the arbitrarily set clamp level setting code, the digital subtraction circuit 7 outputs analog data 8a of the D / A converter 8 described later. An output signal from the averaging circuit 4 is subtracted from clamp level setting value data obtained by adding a predetermined digital value that matches the voltage of the reference voltage source 10 and the subtraction result is given to the D / A converter 8. is there.

  The D / A converter 8 converts the subtraction result of the digital subtraction circuit 7 into an analog signal having a frequency that is one-fifth of the addition average number in the addition average circuit 4 with respect to the frequency of the digital signal output from the A / D converter 3. The data is converted into data 8 a and input to the subtraction circuit 9.

  The subtraction circuit 9 is configured to subtract the voltage of the reference voltage source 10 from the output analog data 8a of the D / A converter 8 during the active period of the clamp pulse, and charge / discharge the capacitor 11 according to the subtraction result. Here, the voltage of the reference voltage source 10 corresponds to a value obtained by converting a predetermined digital value added to a clamp level setting code arbitrarily set in the digital subtraction circuit 7 into analog by the D / A converter 8. Further, the subtraction circuit 9 generates a control terminal voltage applied to the control terminal 2a of the DC control circuit 2 in proportion to the voltage of the capacitor 11, and determines the DC voltage of the black reference period of the output analog video signal of the DC control circuit 2. It is supposed to be.

  FIG. 2 is a timing chart showing an example when the count number in the counter 5 of FIG. 1 is “4”. When the count number in the counter 5 is “4”, the addition averaging circuit 4 controlled by the counter 5 is an A / D converter every four clock cycles within the black reference period starting from the leading edge of the clamp pulse. The operation of sequentially adding and averaging the digital signals output from 3 and outputting the data is repeated. Accordingly, the output analog data 8a of the D / A converter 8 input to the subtraction circuit 9 is also updated every four clock cycles as shown in FIG.

  Therefore, in the case of the example shown in FIG. 2, the last four clocks in the timing of the clamp pulse one cycle before are only the period corresponding to the first four clock cycles from the start of the subtraction circuit 9 starting from the front edge of the clamp pulse. The data based on the signal determined by the addition averaging circuit 4 in the period and the data determined is subtracted from the voltage of the reference voltage source 10, and from the period corresponding to the next four clock periods, The data based on the signal determined by the addition and averaging in the averaging circuit 4 immediately before the four clocks and the voltage of the reference voltage source 10 are subtracted.

  Therefore, the output analog data 8a of the D / A converter 8 is larger than the voltage of the reference voltage source 10 during the period corresponding to the first four clock cycles from the start of the front edge of the clamp pulse, and the DC control is performed. When the DC voltage during the black reference period of the output analog video signal of the circuit 2 rises and tends to exceed the convergence point that is originally fixed, the DC of the black reference period in the output digital signal of the A / D converter 3 The voltage (black level) also coincides with an arbitrarily set value, and as a result, the output signal of the addition averaging circuit 4 is determined as data that coincides with an arbitrarily set clamp level setting code, and the output data of the digital subtraction circuit 7 A digital value such that the output analog data 8a of the D / A converter 8 matches the voltage of the reference voltage source 10 is output.

  Therefore, in the period corresponding to the next four clock cycles, in the subtraction circuit 9, the output analog data 8a of the D / A converter 8 as the input coincides with the voltage of the reference voltage source 10, and the capacitor 11 is charged / discharged. Since the voltage is stopped and the voltage is fixed, the voltage to the control terminal 2a of the DC control circuit 2 is fixed. Therefore, the DC voltage of the black reference period of the output analog video signal of the DC control circuit 2 is also fixed at a voltage that matches the originally fixed convergence point, and the DC voltage of the black reference period in the output digital signal of the A / D converter 3 is fixed. (Black level) is stably fixed to the set value.

  On the other hand, in a period corresponding to the first four clock cycles from the start of the clamp pulse leading edge, the output analog data 8a of the D / A converter 8 is smaller than the voltage of the reference voltage source 10, Even when the DC voltage of the black reference period of the output analog video signal of the DC control circuit 2 falls and tends to exceed the convergence point that is originally fixed, the output analog data 8a is also the voltage of the reference voltage source 10. In the period corresponding to the next four clock cycles, the output analog data 8a of the D / A converter 8 that is the input in the subtraction circuit 9 matches the voltage of the reference voltage source 10, Since charging / discharging to the capacitor 11 is stopped and the voltage is fixed, the voltage of the control terminal 2a of the DC control circuit 2 is fixed. Therefore, the DC voltage of the black reference period of the output analog video signal of the DC control circuit 2 is also fixed at a voltage that matches the originally fixed convergence point, and the DC voltage of the black reference period in the output digital signal of the A / D converter 3 is fixed. (Black level) is stably fixed to the set value.

  Further, as the averaging circuit 4, an addition average value obtained by averaging the digital signals output from the A / D converter 3 for the conversion period of a predetermined binary number to be counted while the counter 5 is counting, A configuration in which a predetermined number of binary numbers are sequentially added and averaged by a total number of at least one of the addition average values can also be applied.

  FIG. 3 is a timing chart showing an example in which the count number in the counter 5 is “4” and the further average number of a certain average value and the previous average value is “4”.

  Since the count number is “4”, the output analog data 8a of the D / A converter 8 input to the subtraction circuit 9 is updated every period corresponding to 4 clock cycles as in the example of FIG. Therefore, the DC voltage (black level) in the black reference period in the output digital signal of the A / D converter 3 is stably fixed to the set value by the same operation as in the example of FIG. Since the number is 16 clock cycles, the influence when noise is applied during the black reference period of the video signal is reduced to ¼ that in the example of FIG.

  As described above, according to the embodiment of the present invention described above, there is a difference between the output analog data 8a of the D / A converter 8 and the voltage of the reference voltage source 10 during the operation of the subtraction circuit 9 having the same clamp pulse period. When the terminal voltage of the control terminal 2a of the DC control circuit 2 changes according to the difference, the output analog data 8a of the D / A converter 8 is the output digital of the A / D converter 3 that changes according to the change of the control terminal 2a. Since the data obtained by sequentially adding and averaging the black reference period signals in the signal is reflected and reflected in real time, the change in the terminal voltage of the control terminal 2a does not continue and does not exceed the convergence point. Therefore, the DC voltage of the analog video signal input to the A / D converter 3 does not exceed the optimum value.

  As described above, the present invention is useful for realizing a high-performance video signal DC voltage stabilizing circuit, high-quality video equipment, and the like.

The circuit diagram which shows the circuit structure in 1st Embodiment of the video signal DC voltage stabilization circuit of this invention. Timing chart showing the operation of the first embodiment Timing diagram showing operation of another embodiment Circuit diagram showing a conventional example of a video signal DC voltage stabilization circuit FIG. 4 is a timing chart showing the operation of the conventional example of FIG. Circuit diagram showing another conventional example of a video signal DC voltage stabilizing circuit Circuit diagram showing another conventional example of a video signal DC voltage stabilizing circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Variable gain amplifier 2 DC control circuit 3 A / D converter 4 Addition averaging circuit 5 Counter 6 Clamp pulse rate addition averaging circuit 7 Digital subtraction circuit 8 D / A converter 9 Subtraction circuit 10 Reference voltage source 11 for generating a reference voltage Capacitor

Claims (5)

An amplifier for amplifying the input analog video signal;
A DC control circuit that regulates the DC voltage of the output analog video signal of the amplifier according to the control terminal voltage applied to the control terminal;
An A / D converter that converts an analog video signal output from the DC control circuit into a digital signal at a predetermined conversion frequency and outputs the digital signal;
Starting from the leading edge of the clamp pulse existing in the black reference period in the horizontal blanking period of the input analog video signal, the active period is at most within the black reference period in the horizontal blanking period. A counter circuit that repeats counting for a conversion period of a predetermined number of A / D converters that is 1/2 or less;
An averaging circuit for averaging the digital signals output from the A / D converter under the control of the counter circuit;
A digital subtraction circuit that subtracts a digital signal output from the addition averaging circuit from digital data obtained by adding a predetermined digital value to an arbitrarily set clamp level setting code;
A D / A converter for converting digital data output from the digital subtraction circuit into analog data;
A capacitor that is charged and discharged according to a subtraction result obtained by subtracting a reference voltage corresponding to the predetermined digital value from analog data output from the D / A converter during an active period of the clamp pulse; A subtracting circuit that proportionally generates a control terminal voltage of the DC control circuit;
A video signal DC voltage stabilizing circuit comprising:   The addition averaging circuit sequentially averages and outputs digital signals output from the A / D converter for a predetermined number of conversion periods to be counted while the counter circuit is counting. The video signal DC voltage stabilizing circuit according to claim 1.   3. The video signal DC voltage stabilization circuit according to claim 2, wherein the predetermined number of conversion cycles sequentially added and averaged by the addition averaging circuit is a binary number.   While the counter circuit is counting, the averaging circuit sequentially adds and averages digital signals output from the A / D converter for a predetermined number of conversion cycles to be counted, and further adds the average value and 2. The video signal DC voltage stabilizing circuit according to claim 1, wherein at least one addition average value corresponding to the immediately preceding predetermined number of conversion cycles and a total of a predetermined number are sequentially averaged and output.   5. The video signal DC voltage stabilization according to claim 4, wherein the predetermined number of conversion periods sequentially added and averaged by the averaging circuit and the total predetermined number of addition average values to be added and averaged are binary numbers. circuit.

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