JP2000156796A - Dc component recovery device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC component recovery device that provides an always proper DC component to a black level of a video signal by avoiding the effects of a high-frequency noise mixed in a video signal onto a black level due to the effects of external disturbance. SOLUTION: This DC component recovery device, employing a feedback clamp circuit or the like, provides a DC component to the black level of an analog video signal whose level is deviated from a pedestal level due to loss of the DC component, so as to restore the black level to the pedestal level. The feedback clamp circuit is provided with a differential amplifier 11 that amplifies the difference between a correction level for a given black level and a received analog video signal and provides the output of a difference signal and averaging circuits 13-17 that average the difference signal for a prescribed period to provide the output of a correction level, in response to a timing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC component reproducing device such as a feedback clamp circuit, and more particularly to a DC component reproducing device for avoiding the influence of disturbance such as a high frequency component in black level correction of a video signal.

[0002]

2. Description of the Related Art In recent years, in video equipment, an opportunity to convert an analog video signal into a digital video signal and handle the digital video signal has been increasing. An analog video signal loses its DC component by being amplified by, for example, a video amplifying circuit by CR coupling in a process before being input to a video device, so that a pedestal level (dark level) and a bright level are displayed on a dark screen (black level). Signals with different blanking levels (reference potentials) are different. This causes inconveniences such as that a portion that should be displayed as white on the screen becomes gray, or that the screen has a changed contrast.

Therefore, when an analog video signal is converted into a digital signal and recorded and transmitted, an accurate DC component having a small error is reproduced from the input analog video signal, and the reproduced DC component is superimposed on the input analog video signal. Therefore, it is necessary to force the pedestal level between the dark screen and the bright screen. A conventional feedback clamp circuit for performing such a reproducing process is described in, for example, Japanese Patent Application Laid-Open No. 6-46287.

FIG. 8 is a block diagram showing an example of the feedback clamp circuit described in the above publication. This feedback clamp circuit has a differential amplifier 81, an A / D converter 82, a first register 83, a subtraction circuit 84, an addition circuit 85, a second register 86, a D / A converter 87, and a timing generation circuit 88. ing.

[0005] The differential amplifier 81 clamps an input analog video signal to a correction potential. A / D converter 82
Converts the analog video signal clamped by the differential amplifier 81 into a digital signal. The first register 83 holds the pedestal level at the timing given for each horizontal line from the timing generation circuit 88 for the clamped digital video signal.

The subtraction circuit 84 detects an error between the held pedestal level and a predetermined pedestal level. The addition circuit 85 updates the correction potential by adding the error detected by the subtraction circuit 84 and the previously calculated correction potential. The second register 86 holds the updated correction potential at the timing from the timing generation circuit 88. The D / A converter 87 converts the updated new correction potential into an analog signal, and feeds it back to the differential amplifier 81 as a clamp potential of the input analog video signal.

Next, the operation of the above-mentioned conventional feedback clamp circuit will be described with reference to FIGS. FIG.
FIG. 3 is a timing chart showing signal waveforms indicating the operation of a conventional feedback clamp circuit. In the figure, the horizontal direction indicates the time axis, and the vertical direction indicates the signal line axis, respectively.
Shows a video signal (signal A) which has lost a DC component and is located at a pedestal level, (b) shows a clamp timing signal (signal B), and (c) shows a set signal (signal C).

First, when an analog video signal having no DC component is input to the differential amplifier 81, the differential amplifier 81 converts the analog video signal into a black level correction potential signal sent from the D / A converter 87. Is clamped at and output. The clamped analog video signal is converted into a digital signal by the A / D converter 82 and output to the outside of the apparatus and to the first register 83, respectively.

When the clamped digital video signal is input to the first register 83, the pedestal level of the input digital video signal is determined by the clamp timing signal corresponding to the pedestal (return blanking) timing of the digital video signal. Is extracted, held and output. The clamp timing signal is a signal (FIG. 9B) generated by the timing generation circuit 88 and sent to the first register 83 and the second register 86, respectively.

Then, when the pedestal level output from the first register 83 is input to the subtraction circuit 84, the subtraction circuit 84 subtracts a predetermined pedestal level from the pedestal level. Subtraction circuit 8
The result of the subtraction in 4 is error data between the pedestal level of the input digital video signal and a prescribed pedestal level (set value shown in FIG. 8).

Further, when the error data is input to the adder circuit 85, the adder circuit 85 adds the error data to the correction potential from the second register 86 which was given to the differential amplifier 81 last time, and generates a new signal. Output as a correction potential. At this time, when the correction potential output value from the adding circuit 85 overflows, its maximum value is output, and when it is negative, a zero value is output.

The new correction potential output from the adder circuit 85 is input to the second register 86, and is delayed from the clamp timing signal (signal B in FIG. 9B) and has horizontal blanking (return blanking). 9) is updated by a set signal (signal C in FIG. 9C) generated at one timing during the period, and is maintained during one horizontal period. This set signal is input from the timing generation circuit 88 to the second register 86, and the correction potential output from the second register 86 is updated each time the clamp timing signal is generated. The new correction potential output from the second register 86 is converted to an analog signal by the D / A converter 87 and
1 is input. As a result, the input analog video signal having no DC component is clamped to a new correction potential,
A DC component will be provided.

[0013]

However, the conventional feedback clamp circuit is susceptible to high frequency noise mixed into the black level due to disturbance or the like.
When affected by high-frequency noise, an accurate black level correction potential cannot be obtained, and the black level of a video signal sometimes becomes uneven. When the detected error data amount is large, the error data is directly added to the previous correction potential, and the correction potential amount that changes every one horizontal line period becomes large. Occurs every horizontal line.

In view of the above, the present invention avoids the influence of high frequency noise mixed into a video signal on the black level due to the influence of disturbance or the like, and always gives an appropriate DC component to the black level of the video signal. It is an object of the present invention to provide a DC component regenerating apparatus capable of performing the above.

[0015]

In order to achieve the above object, a DC component reproducing apparatus according to the present invention provides a DC component to a black level of an analog video signal deviating from a pedestal level by losing a DC component. In a DC component reproducing apparatus for returning a black level to the pedestal level, a differential amplifier circuit for amplifying a difference between a given black level correction potential and an input analog video signal and outputting the amplified signal as a difference signal; An averaging circuit for averaging for a predetermined period and outputting the corrected potential in response to a timing signal.

In the DC component reproducing apparatus of the present invention, the black level of the video signal is averaged and then supplied to the differential amplifier circuit as the black level correction potential, so that high frequency noise is mixed during the black level output period. However, the noise is averaged together with the black level, and the direct influence of high frequency noise is avoided to enable high-precision black level reproduction.

The averaging circuit converts the difference signal output from the differential amplifier circuit into a digital image signal and sends the digital signal as a digital video signal to the averaging process. A D / A converter for converting the subsequent digital video signal into an analog potential to obtain the correction potential, a clock signal for latching a black level in the digital video signal, and a black level period signal indicating a black level output period And a timing generation circuit for respectively generating Thus, only the black level can be extracted from the digital video signal, subjected to averaging processing, and then converted to analog, and the value can be supplied to the differential amplifier circuit as the correction potential.

Also, the averaging circuit performs a logical operation on the clock signal and the black level period signal and outputs the result as another clock signal. A first latch circuit that outputs to the dynamic amplification circuit and feeds back to the input side; an addition circuit that adds the digital video signal from the A / D converter to a feedback output of the first latch circuit; It is preferable that a second latch circuit that outputs the first latch circuit while holding the output from the point in time when the level period signal is applied is provided. This makes it possible to obtain a suitable circuit configuration for averaging the black level of the video signal and then outputting the averaged black level as a correction potential to the differential amplifier circuit.

[0019] It is preferable that the averaging circuit includes a comparison circuit for comparing the integration result of the addition circuit with a preset black level setting value. In this case, for example, it is possible to absorb a characteristic variation caused by a temperature drift or the like of the differential amplifier circuit or the A / D conversion circuit, and to always provide an appropriate DC component to the input analog video signal.

Preferably, the averaging circuit increases or decreases or fixes the count value once in one horizontal line period according to the comparison result of the comparison circuit, and increases or decreases or fixes the black-level correction potential for the differential amplifier circuit. And an up-down counter.

In this case, for example, if the result of the comparison by the comparing circuit is smaller than the preset value of the black level, the up / down counter is incremented by one so as to increase the correction potential of the black level. I do.
If the integration result is larger than the set value of the black level, the up / down counter is decremented by one so as to decrease the black level correction potential. On the other hand, when the integration result is equal to the set value of the black level, the counter value of the up / down counter is not increased or decreased. By these processes, even when the error between the preset black level setting value and the black level of the video signal is large, a video signal without black level unevenness can be generated for each horizontal line period.

More preferably, when the averaging circuit receives the black level period signal as the timing signal, the D / A converter converts the output of the up / down counter into an analog signal and outputs it. This makes it possible to supply the analog-converted correction potential to the differential amplifier circuit at an appropriate timing.

Alternatively, instead of the above, the averaging circuit increases or decreases or fixes the count value once in one field period according to the comparison result of the comparison circuit, and adjusts the black-level correction potential to the differential amplifier circuit. It is also a preferable embodiment to provide an up / down counter for increasing / decreasing or fixing. In this case, even when the error between the preset black level setting value and the black level of the video signal is large, a video signal without black level unevenness can be generated for each field period.

Further, at the time when the averaging circuit receives, as the timing signal, a vertical drive signal for the image based on the digital video signal, the D / A converter outputs the output of the up / down counter. Preferably, the signal is converted into an analog signal and output. This makes it possible to supply the analog-converted correction potential to the differential amplifier circuit at an appropriate timing.

[0025]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a feedback clamp circuit (DC component reproducing device) according to the first embodiment of the present invention. The feedback clamp circuit includes a differential amplifier 11, an A / D converter 12, a timing generation circuit 13, a digital integration circuit 14, a digital comparison circuit 15, an UP / DOWN (up / down) counter 16, and a D / A converter 17. Have.

The differential amplifier 11 receives an analog video signal having no DC component, amplifies a difference between the video signal and a correction potential supplied from the D / A converter 17, and outputs the amplified signal. The A / D converter 12 converts the analog video signal amplified by the differential amplifier 11 and provided with a DC component into a digital signal based on an A / D conversion clock signal ADCLK supplied from the timing generation circuit 13. Then, the digital video signal is output to the outside of the device and to the digital integration circuit 14, respectively.

The digital integrator 14 converts the video signal from the converted clock signal ADCLK supplied from the timing generator 13 and a black level period signal OBCP (Optical Black Clamp Pulse) indicating a black level output period in the digital video signal. Black levels are integrated and averaged (integrated),
The integration result is output to the digital comparison circuit 15. The black level period signal OBCP is a signal generated by the timing generation circuit 13 at a predetermined timing and indicating a black level output period. Further, the digital comparison circuit 15 compares the integration result from the digital integration circuit 14 with a preset black level setting value OB (Optical Black) of the video signal from outside the device, and compares the integration result with the black level setting. The signals UD and EN indicating the magnitude relationship with the value are output to the UP / DOWN counter 16.

The UP / DOWN counter 16 counts the count value, that is, the black level correction potential, in accordance with the black level period signal OBCP from the timing generation circuit 13 based on the signals UD and EN output from the digital comparison circuit 15. Increase or decrease. D /
The A-converter 17 converts the count value of the UP / DOWN counter, that is, the correction potential into analog data by the black level period signal OBCP from the timing generation circuit 13, and
Feedback to 1 As a result, the input analog video signal is clamped by the black level correction potential signal output from the D / A converter 17 and has a DC component.

Next, the structure of the digital integration circuit 14 in this embodiment will be described in detail. FIG. 2 is a block diagram showing a configuration of the digital integration circuit 14. The digital integration circuit 14 includes an adder 21, latch circuits 22 and 23 each including a flip-flop, and a gate circuit 24.
The gate circuit 24 has a conversion clock signal input to one input terminal.
The inverted value of ADCLK is applied to the black level period signal O
Each of the BCPs is input, and the resulting clock signal is output to the latch circuit 22.

The adder 21 adds the digital video signal digitally converted by the A / D converter 12 and the output of the latch circuit 22 fed back. Latch circuit 22
Receives the data added by the adder 21, holds the added data by a clock signal from the gate circuit 24, and stores the held data in the latch circuit 23 and the adder 2.
Send to one. The addition (integration) result is sent to the digital comparison circuit 15 as an integration result of the black level period of the video signal while being held once in one horizontal line period by the latch circuit 23 by the black level period signal OBCP.

Next, the operation of the feedback clamp circuit in this embodiment will be described. The differential amplifier 11
The difference between the input analog video signal and the applied black level correction potential is amplified and output to the A / D converter 12 as an analog video signal having a DC component. The A / D converter 12 converts an analog video signal into a digital signal at the timing of the conversion clock signal ADCLK from the timing generation circuit 13, and outputs the digital video signal to the outside of the device and to the digital integration circuit 14, respectively. Thereby, the digital integration circuit 14 integrates the black level in the digital video signal based on the conversion clock signal ADCLK and the black level period signal OBCP.

Next, the operation of the digital integration circuit 14 will be described with reference to FIGS. FIG. 3 is a timing chart showing the operation of the digital integration circuit 14 in the present embodiment. In the figure, the horizontal direction indicates the time axis, and the vertical direction indicates the signal axis. The video signal for one horizontal line period is shown at the top, and the black level period signal OBCP is shown at (a). (B) in the figure is the black level period signal of (a).
This is an enlarged view of one pulse in the OBCP, and the following (c), (d), and (e) correspond to the time axis of (b), respectively. (c) is the conversion clock signal ADCLK, (d) is the output of the A / D converter 12, and (e) is the gate circuit 24 to the latch circuit 22.
Are shown, respectively.

The black level period signal OBCP is generated once in one horizontal line period and in the horizontal blanking period of the video signal (FIG. 3 (a)). The gate circuit 24 is configured as shown in FIG.
A logical operation is performed on the black level period signal OBCP and the converted clock signal ADCLK shown in (c) to generate a clock signal (e) to the latch circuit 22. The clock signal (e) is generated by the number obtained by dividing one period of the conversion clock signal ADCLK during the period when the black level period signal OBCP in (b) is at the high level “H”.

In FIG. 3, the number of pulses of the conversion clock signal ADCLK is N. The latch circuit 22 holds the data when the conversion clock signal ADCLK is input, and
To the latch circuit 22 and the adder 2
By combining with 1, the black level of the digital video signal is integrated N times. The black level integrated N times is held by the latch circuit 23 by the black level period signal OBCP. This holding process is performed once in one horizontal line period.

FIG. 4 is a timing chart showing the timing of the video signal containing high frequency noise and the black level period signal OBCP. As shown in the figure, even if high-frequency noise (whisker-like pulses in the horizontal blanking period in the figure) is mixed during the black level output period, the black level is integrated N times by the digital integration circuit 14 and Since the noise is averaged together with the black level, errors in the operation result are reduced. In this case, as the number of integrations N increases, the integration result approaches the original black level value.

The digital comparison circuit 15 compares the integration result of the digital integration circuit 14 with the black level set value OB.
Tables 1 and 2 are truth tables respectively showing the operations of the digital comparison circuit 15 and the UP / DOWN counter circuit 16 in this embodiment.

[0037]

[Table 1]

[0038]

[Table 2]

The result of comparison between the two values is handled according to the truth table shown in Table 1. When the integration result is smaller than the predetermined black level set value OB, "1" is output to the increase / decrease signal UD (UP / DOWN) and the enable signal EN (ENABLE) for the UP / DOWN counter 16, respectively. When the integration result is larger than the black level set value OB, “0” is output to the increase / decrease signal UD and “1” is output to the enable signal EN.
When the integration result is equal to the black level set value OB, the increase / decrease signal UD may be either “1” or “0”, and outputs “0” as the enable signal EN.

The UP / DOWN counter circuit 16 increases or decreases the count value at the timing of the black level period signal OBCP supplied from the timing generation circuit 13 according to the comparison result (UD, EN signal) given from the digital comparison circuit 15. UP
The operation mode of the / DOWN counter circuit 16 is determined by the input signals (UD, EN) as shown in Table 2.

For example, an increase / decrease signal UD and an enable signal EN
Are both "1", that is, the integration result is the black level set value OB
If it is smaller, the UP / DOWN counter circuit 16 enters the increment mode, and the count value is incremented by 1 LSB at the timing of the black level period signal OBCP from the timing generation circuit 13, that is, the count value is incremented by one.

When the increase / decrease signal UD is "0" and the enable signal EN is "1", that is, when the integration result is larger than the black level set value OB, the UP / DOWN counter circuit 16 enters the decrease mode, The count value is set to 1LS at the timing of the black level period signal OBCP supplied from the generation circuit 13.
Only B, that is, the count value is decremented by one. When the enable signal EN is “0”, the increase / decrease signal UD
Irrespective of the value, the UP / DOWN counter circuit 16 is in the holding mode, and holds the count value without increasing or decreasing even if the black level period signal OBCP is supplied from the timing generation circuit 13.

As described above, when the integration result of the digital integration circuit 14 is larger than the black level set value OB, UP / D
The OWN counter 16 works in a decreasing direction,
When the integration result of the digital integration circuit 14 is smaller than the black level set value OB, the count value of the UP / DOWN counter 16 works in a direction to increase. The count value of the UP / DOWN counter 16 is output to the D / A converter 17 as a black level correction value of the analog video signal input to the differential amplifier 11. The D / A converter 17 converts the count value into analog data once in one horizontal line period based on the black level period signal OBCP from the timing generation circuit 13, and supplies the analog data to the differential amplifier 11. As a result, the analog video signal input to the differential amplifier 11 is clamped to the output voltage (black level correction potential) of the D / A converter 17.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram illustrating a configuration of a feedback clamp circuit according to the present embodiment.
FIG. 6 is a block diagram showing a detailed configuration of the digital integration circuit 14 in the present embodiment. 5 and 6, the same reference numerals are given to the same circuit elements as those in FIGS.

In the first embodiment, the digital integration circuit 1
4. The digital comparison circuit 15, the UP / DOWN counter 16, and the D / A converter 17 are respectively operated by the black level period signal OBCP, but in the present embodiment, the digital integration circuit 1
4, a black level period signal OBCP is supplied to the gate circuit 24, while the latch circuit 23, the UP / DOWN counter 16 and the D / A converter 17 are supplied with the vertical drive signal VD for the video based on the digital video signal. You.

That is, the differential amplifier 11 receives an analog video signal having no DC component, amplifies the difference between this video signal and the correction potential provided from the D / A converter 17, and outputs the amplified signal. The A / D converter 12 is a differential amplifier 1
The analog video signal amplified in 1 is converted into a digital signal based on the conversion clock signal ADCLK supplied from the timing generation circuit 13, and the digital video signal is output to the outside of the device and to the digital integration circuit 14, respectively.

The digital integration circuit 14 integrates and averages (integrates) the black level of the video signal from the conversion clock signal ADCLK and the black level period signal OBCP, and integrates the integration result at the timing of the video vertical drive signal VD. Output to the digital comparison circuit 15. The digital comparison circuit 15 calculates the integration result from the digital integration circuit 14 and the black level setting value from outside the device.
It compares with the OB and outputs signals UD and EN indicating the magnitude relationship between the integration result and the black level set value to the UP / DOWN counter 16.

The UP / DOWN counter 16 counts (black level correction potential) according to the vertical drive signal VD of the image from the timing generation circuit 13 based on the signals UD and EN output from the digital comparison circuit 15. Is increased or decreased. D / A
The converter 17 converts the count value of the UP / DOWN counter into analog data based on the video vertical drive signal VD from the timing generation circuit 13 and feeds it back to the differential amplifier 11. As a result, the input analog video signal becomes D /
It is clamped by the black level correction potential signal output from the A converter 17 and has a DC component.

Next, the structure of the digital integration circuit 14 in this embodiment will be described in detail. FIG. 6 is a block diagram showing the configuration of the digital integration circuit 14. The digital integration circuit 14 includes an adder 21, latch circuits 22 and 23 each including a flip-flop, and a gate circuit 24.
The gate circuit 24 has a conversion clock signal input to one input terminal.
The inverted value of ADCLK is applied to the black level period signal O
Each of the BCPs is input, and the resulting clock signal is output to the latch circuit 22.

The adder 21 adds the digital video signal digitally converted by the A / D converter 12 and the output of the latch circuit 22 fed back. Latch circuit 22
Inputs the data added by the adder 21, holds the added data with a clock signal from the gate circuit 24, and sends the held data to the latch circuit 23 and the adder 21. As a result, the output signal of the latch circuit 22 becomes
The result is the integration of the black level period of the video signal. The result of the integration is once held in one field period by the video vertical drive signal VD, sent to the latch circuit 23, and input to the digital comparison circuit 15.

Next, the operation of the digital integration circuit 14 will be described with reference to FIGS. FIG. 7 is a timing chart illustrating the operation of the digital integration circuit 14 in the present embodiment. In the figure, the horizontal direction indicates the time axis, and the vertical direction indicates the signal axis. The video signal for one field period is at the top, and the vertical drive signal VD of the video is shown at (a), (b)
Shows the black level period signal OBCP. (C) in FIG.
(B) is an enlarged view of the interval between pulses mainly indicating one horizontal line period in the black level period signal OBCP in (b), and (e) following this corresponds to the time axis in (c). (e) shows a clock signal supplied from the gate circuit 24 to the latch circuit 22.

The video vertical drive signal VD is generated once in one field period (1/2 screen) and in the vertical blanking period of the video signal (FIG. 7 (a)). Gate circuit 24
Is a black level period signal OBCP shown in (b) and (e) of FIG.
And a converted clock signal ADCLK to generate a clock signal (e) to the latch circuit 22. Clock signal (e)
Occurs during the period in which the black level period signal OBCP shown in (c) is at the high level “H”, by the number obtained by dividing by one cycle period of the conversion clock signal ADCLK.

In FIG. 7, the number of pulses of the conversion clock signal ADCLK is N. The latch circuit 22 holds the data when the conversion clock signal ADCLK is input, and
To the latch circuit 22 and the adder 2
By combining with 1, the black level of the video signal of one horizontal line of the digital video signal is integrated N times. The black level integrated N times is held and output by the latch circuit 23 by the video vertical drive signal VD. Since this holding process is performed once for each field period, the digital integration circuit 14 of the present embodiment integrates the black level of the video signal of one horizontal line in the vertical direction for a half image frame period further. Is output.

The integration result from the digital integration circuit 14 is
It is input to the digital comparison circuit 15 and compared with the black level setting value OB. The UP / DOWN counter 16 holds the count value by 1 LSB, or without changing it, based on the comparison result of the digital comparison circuit 15.

The input / output relationship between the digital comparison circuit 15 and the UP / DOWN counter 16 is shown in Table 1 in the first embodiment.
Is the same as That is, when the integration result of the digital integration circuit 14 is larger than the black level setting value OB, the UP / DOWN counter 16 acts in a direction to decrease the count value, and the integration result of the digital integration circuit 14 determines the black level setting value OB. If it is smaller than the value, it works in the direction of increasing the count value.
The UP / DOWN counter 16 is provided with a digital integration circuit 14.
Is equal to the black level set value OB, the count value is held without increasing or decreasing.

The count value of the UP / DOWN counter 16 increases and decreases at the timing of the vertical drive signal VD from the timing generation circuit 13 and is supplied to the D / A converter 17 as a black level correction potential of the digital video signal. D / A converter 17
Receives the count value of the UP / DOWN counter 16, converts the count value (black level correction potential) into analog data once in one field period at the timing of the vertical drive signal VD from the timing generation circuit 13, It is supplied to the amplifier 11. As a result, the analog video signal input to the differential amplifier 11 is clamped at the output potential of the D / A converter 17, and the DC component is reproduced.

In the feedback clamp circuit of this embodiment, one field period (1/2 image frame period)
Since the black level in the video signal is averaged, the DC reproduction process can be performed with higher accuracy than in the first embodiment. In the embodiment, the error of the black level of the video signal is 1
Since feedback is based on the field period,
Variation in the black level corrected by the correction potential can be further reduced.

As described above, in the feedback clamp circuits according to the first and second embodiments, the black level is averaged during the period in which the black level is output. It is possible to perform the reproduction process of the DC component with respect to the black level with high accuracy without being directly affected. Also, the black level setting value
Without detecting the error amount between the OB and the black level integrated value of the video signal, only the magnitude relationship between the two values is detected, and the count value of the UP / DOWN counter 16 can be increased or decreased by only 1 LSB from the detection result. . Thus, for example, when the black level setting value OB is greatly different from the black level integration value and the error is large, it is possible to suppress unevenness of the black level caused by an increase in the amount of feedback to the differential amplifier 11. it can.

Although the present invention has been described based on the preferred embodiment, the DC component reproducing apparatus such as the feedback clamp circuit of the present invention is not limited to the configuration of the above embodiment. A DC component reproducing apparatus obtained by making various modifications and changes from the configuration of the above embodiment is also included in the scope of the present invention.

[0060]

As described above, according to the DC component reproducing apparatus of the present invention, it is possible to avoid the influence of the high frequency noise mixed into the video signal on the black level due to the influence of disturbance or the like, and to reduce the black level of the video signal. Therefore, an appropriate DC component can always be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a feedback clamp circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a digital integration circuit according to the first embodiment.

FIG. 3 is a timing chart illustrating an operation of the digital integration circuit according to the first embodiment.

FIG. 4 is a timing chart showing timings of a video signal and a black level period signal when high frequency noise is included.

FIG. 5 is a block diagram illustrating a configuration of a feedback clamp circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a digital integration circuit according to a second embodiment.

FIG. 7 is a timing chart illustrating an operation of the digital integration circuit according to the second embodiment.

FIG. 8 is a block diagram showing an example of a conventional feedback clamp circuit.

FIG. 9 is a timing chart illustrating an operation of the feedback clamp circuit of FIG. 8;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Differential amplifier 12 A / D converter 13 Timing generation circuit 14 Digital integration circuit 15 Digital comparison circuit 16 UP / DOWN counter 17 D / A converter 21 Adder 22, 23 Latch circuit 24 Gate circuit 81 Differential amplifier 82 A / D converter 83 First register 84 Subtraction circuit 85 Addition circuit 86 Second register 87 D / A converter 88 Timing generation circuit

Claims (8)

[Claims] 1. A DC component reproducing apparatus for applying a DC component to a black level of an analog video signal deviated from a pedestal level by losing a DC component and returning the black level to the pedestal level. And a differential amplifier circuit that amplifies the difference between the input analog video signal and outputs the difference signal as a difference signal; and an averaging circuit that averages the difference signal for a predetermined period and outputs the corrected potential in response to a timing signal. A direct current component reproducing device comprising: 2. An A / D conversion circuit, wherein the averaging circuit digitally converts the difference signal output from the differential amplifier circuit and sends the digital signal as a digital video signal to the averaging process. A D / A converter for converting the digital video signal into an analog potential by converting the digital video signal into a correction potential, a clock signal for latching a black level in the digital video signal, and a black level period signal indicating a black level output period. 2. The DC component reproducing apparatus according to claim 1, further comprising a timing generation circuit that generates each of them. 3. A logical operation circuit, wherein the averaging circuit performs a logical operation on the clock signal and the black level period signal and outputs the result as another clock signal; A first latch circuit that outputs the signal to the dynamic amplifier circuit and feeds back the signal to the input side; and the digital video signal from the A / D converter and the first latch circuit.
And an adder circuit for adding a feedback output of the latch circuit, and a second latch circuit that outputs while holding the output of the first latch circuit from the time when the black level period signal is given. Item 3. A direct current component reproducing apparatus according to item 2. 4. The direct current (DC) according to claim 2, wherein the averaging circuit includes a comparison circuit that compares the integration result of the addition circuit with a preset black level setting value. Component regeneration device. 5. The averaging circuit increases or decreases or fixes the count value once in one horizontal line period according to the comparison result of the comparison circuit, and increases or decreases or fixes the black-level correction potential for the differential amplifier circuit. The DC component reproducing apparatus according to claim 4, further comprising an up / down counter for performing the operation. 6. When the averaging circuit receives the black level period signal as the timing signal,
6. The DC component reproducing apparatus according to claim 5, wherein the / A converter converts the output of the up / down counter into an analog signal and outputs the analog signal. 7. The averaging circuit increases or decreases or fixes the count value once in one field period according to the comparison result of the comparison circuit, and increases or decreases or fixes the black-level correction potential for the differential amplifier circuit. The direct current component reproducing apparatus according to claim 4, further comprising an up / down counter. 8. The D / A converter converts the output of the up / down counter into an analog signal when the averaging circuit receives a vertical drive signal for the image based on the digital image signal as the timing signal. The direct-current component reproducing device according to claim 7, wherein the direct-current component is output.