JPH06177761A - Video signal a/d conversion circuit - Google Patents

Abstract

PURPOSE:To obtain a video signal A/D conversion circuit generating a digital video signal with high quality by always making a maximum value of a video signal fed to the A/D converter coincident with an upper limit level of sampling in the A/D converter. CONSTITUTION:A clamp circuit 2 clamps a black level of a video signal 101 to a lower reference potential VB at the sampling of an A/D converter 10. A comparator 3 compares an upper limit potential VT at the sampling of an A/D converter 10 with a video signal 102 and generates a logic signal 103 at 'H' when the video signal 102 exceeds the level VT. D flip-flop circuits 5, 6 latch the state of the signal 103 only for a period of vertical synchronizing signal VD. An up-down counter 7 counts down when a signal 106 is at H and counts up when L. A D/A converter 8 converts a digital count signal 107 into an analog signal 108. An amplifier offset adjustment circuit 9 amplifies the signal 108 and adjusts the center potential of fluctuation (offset potential) and generates a gain control signal 109 in matching with the standard of the amplitude and the offset potential of the video amplifier 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for converting an analog video signal output from a video camera or the like into a digital signal. More specifically, the level of the analog video signal supplied to an A / D converter is controlled. The present invention relates to a video signal A / D conversion circuit that generates a high-quality digital video signal by adjusting the input dynamic range of the A / D converter to the full.

[0002]

2. Description of the Related Art A conventional video signal A / D conversion circuit for converting an analog video signal into a digital video signal is shown in a block circuit diagram of FIG. This A / D conversion circuit is a video amplifier 1
A clamp circuit 2, an A / D converter 10, a video signal level detector 11, and an amplification / offset adjustment circuit 9. The video amplifier 1 amplifies the analog input video signal 100 with a gain according to the gain control signal 109,
The amplified video signal 101 is generated. Clamp circuit 2
Generates a level-adjusted video signal 102 in which the black level of the video signal 101 is adjusted to the lower limit (Bottom) reference potential V _B of the A / D converter 10 without changing the amplitude and waveform of the video signal 101.

The A / D converter 10 receives an analog video signal 102, subjects the signal 102 to sampling (sampling), quantization and coding, and then a digital video signal 1
Generate 10. Sampling is performed on the video signal 102 between the reference potential V _T of the upper limit (Top) and the reference potential V _B of the lower limit (Bottom), and is not performed on the video signal 102 of V _T or more or V _B or less. .

The video signal level detector 11 detects the video signal 10
The second level is detected, and the signal level is converted into a DC level signal 111. The amplification / offset adjustment circuit 9
The gain control signal 109 is generated by amplifying the level signal 111 and adjusting the fluctuation center potential (offset potential, that is, DC level). The offset potential is set to the center potential of the dynamic range of the gain control signal that is defined in advance for the video amplifier 1.

[0005]

The video signal A / D shown in FIG.
In the conversion circuit, the video amplifier 1, the clamp circuit 2, the video signal level detector 11, and the amplification / offset adjustment circuit 9 form an automatic gain control circuit (AGC circuit), and the level fluctuation of the input video signal 100 is generated. Nevertheless, the video signal 102 of a constant level is supplied to the A / D converter 10. However, since the video signal level detection circuit 11 and the amplification / offset adjustment circuit 9 are analog circuits, it is unavoidable to change the characteristics depending on the environmental temperature. If the maximum value of the video signal 102 is A /
Upper limit potential (T
op) When V _T is exceeded, the part exceeding V _T is uniformly V _T
The information in the video signal 102 in the portion exceeding V _T is lost. On the other hand, when the white level of the video signal 102 is lower than the upper limit potential V _T , the A / D converter 10
Dynamic range (V _T −
Since the video signal 102 is converted into a digital signal in a range smaller than V _B ), the performance of the A / D converter 10 is not fully used, and the resolution of the digital video signal 110 is reduced. As a result, the quality of the digital video signal 110 deteriorates.

As described above, the conventional video signal A / D conversion circuit has a problem to be solved regarding the level adjustment of the video signal supplied to the A / D converter. Therefore, an object of the present invention is to set the maximum value of the video signal supplied to the A / D converter to the A / D converter.
Upper limit potential (Top) V of sampling in D converter
It is to provide a video signal A / D conversion circuit that always matches _T to generate a high-quality digital video signal.

[0007]

Means for Solving the Problems In order to solve the above-mentioned problems, the means provided by the present invention is to amplify an input video signal by a video amplifier whose amplification gain is controlled by a gain control signal. A clamp circuit receives the output amplified video signal to generate a level-adjusted video signal in which the black level of the amplified video signal is set to a predetermined potential, and the level-adjusted video signal is applied to an A / D converter to obtain a predetermined level. A video signal A / D conversion circuit for converting the level adjustment video signal between the lower limit potential V _B and the upper limit potential V _T into a digital video signal, wherein the level adjustment video signal and the upper limit potential V _T are compared. A first D flip-flop for receiving a vertical synchronizing signal related to the input video signal at a clear terminal and receiving an output of the comparator at a clock terminal, and the first D flip-flop. A second D flip-flop that receives the output of the drop at the data terminal and that receives the vertical synchronization signal at the clock terminal, and a clock, and increases the count value for each clock according to the output of the second D flip-flop. Up / down counter for increasing or decreasing, a D / A converter for converting the output of the up / down counter into an analog signal, an output of the D / A converter is amplified, and its DC level is adjusted to the video amplifier. An amplification / offset adjustment circuit supplied as the gain control signal is provided, and a signal processing circuit from the comparator to the amplification / offset adjustment circuit has a maximum value of the level adjustment video signal and the upper limit potential V _T. The polarity of the gain control signal is adjusted so that

[0008]

In the present invention, the analog signal supplied to the A / D converter is a level-adjusted video signal in which the black level is set to a predetermined potential, and in this respect it is the same as the conventional circuit of FIG. The level-adjusted video signal and the upper limit potential V _{T at} the input of the A / D converter are compared by a comparator, and the output of this comparator is converted by a digital circuit (first and second D flip-flops and an up / down counter). After processing, the output of this digital circuit is converted into an analog signal by a D / A converter, and the amplification / offset adjustment circuit adjusts the analog signal to an amplitude and a DC level suitable for the gain control signal in the video amplifier. .

As described above, according to the present invention, the level fluctuation of the level-adjusted video signal is detected by comparing with the upper limit potential V _T of the input in the A / D converter, and the signal of the level fluctuation is digitally processed. Since it determines whether to increase or decrease the amplification gain of the video amplifier,
That is, since the direction of gain control is determined by the output of the up / down counter, even if the D / A converter and the amplification / offset adjustment circuit are affected by the temperature change to some extent, the maximum value of the level adjustment video signal is A / D. It can be stably made to match the upper limit reference potential (Top) V _T of the converter.

[0010]

The present invention will be described in more detail with reference to the following examples. FIG. 1 is a block circuit diagram showing an embodiment of the present invention, and FIGS. 2, 3 and 4 are waveform diagrams of signals in respective portions of the embodiment of FIG. In this embodiment, a video amplifier 1, a clamp circuit 2, a comparator 3, an inverter 4, D flip-flops 5 and 6, an up / down counter 7, a D / A converter 8, an amplification / offset adjustment circuit 9 and an A / D conversion. Bowl 1
It is 0. The operations of the video amplifier 1, the clamp circuit 2, the amplification / offset adjustment circuit 9 and the A / D converter 10 are the same as those in the conventional circuit of FIG.

The video amplifier 1 amplifies the analog input video signal 100 with a gain according to the gain control signal 109 and generates an amplified video signal 101. Clamp circuit 2
Generates a level-adjusted video signal 102 in which the black level of the video signal 101 is adjusted to the lower limit (Bottom) reference potential V _B of the A / D converter 10 without changing the amplitude and waveform of the video signal 101. FIG. 2 is a waveform diagram of the video signal 102.

The A / D converter 10 receives an analog video signal 102, performs sampling (sampling), quantization and coding on the signal 102, and digital video signal 1
Generate 10. Sampling is performed on the video signal 102 between the reference potential V _T of the upper limit (Top) and the reference potential V _B of the lower limit (Bottom), and is not performed on the video signal 102 of V _T or more or V _B or less. .

The comparator 3 compares the level adjusted video signal 102 with the upper limit reference potential V _T. As shown in FIG. 3, the output signal 103 of the comparator 3 is a rectangular wave signal which is “H” only when the video signal 102 exceeds the upper reference potential V _T and is “L” at other times.

The D flip-flop 5 has a clock terminal C.
K receives the output signal 103 of the comparator 3, and the clear terminal CL
The vertical sync signal VD (Verti) for each field.
Cal Drive) is received by a negative pulse, and the data terminal D receives + 5V (logic level “H”). Figure 1
Also, in FIG. 4, VD + and VD- indicate the vertical synchronizing signal VD of positive pulse and negative pulse, respectively. As is clear from FIG. 4, the output signal 105 of the D flip-flop 5 is
Is "H" when the comparator output signal 103 rises to "H", and is VD- (a signal obtained by inverting the polarity of VD +).
Cleared to become "L". Therefore, the signal 105
Unless the comparator output signal 103 becomes “H”,
Maintain "L".

The D flip-flop 6 receives the output signal 105 of the D flip-flop 5 at the data terminal D and the vertical synchronizing signal VD + at the clock terminal CK. As shown in FIG. 4, the output signal 106 of the D flip-flop 6 changes the state of the output signal 105 of the D flip-flop 5 when the vertical synchronizing signal VD + rises to the next vertical synchronizing signal VD.
Hold until + is input.

When the signal 106 is "H", the up-down counter 7 decrements the measured value by 1 each time the clock terminal CK receives VD-, and when the signal 106 is "L", the clock terminal CK receives VD-. -Count value is 1 each time
It increases gradually. The signal 107 is a digital signal representing the count value. The D / A converter 8 converts the digital signal 107 representing the count value into the analog signal 108.

The amplifying / offset adjusting circuit 9 uses the signal 10
8 is amplified and the fluctuation center level of the signal 108 (offset potential = potential of the direct current component of the signal 108) is adjusted to generate the gain control signal 109. Gain control signal 10
Reference numeral 9 controls the amplification gain of the video amplifier 1. The amplification / offset adjustment circuit 9 amplifies the signal 108 and adjusts the offset potential of the signal 108 so that the amplitude and offset potential of the gain control signal 109 have predetermined values for the video amplifier 1.

In the embodiment of FIG. 1, the A / D converter 1
It is checked in each field whether the maximum value of the video signal 102 input to 0 exceeds the upper limit reference potential V _T in the sampling of the A / D converter 10, and the maximum value of the video signal 102 exceeds V _T. When the maximum value of the video signal 102 is V _T or less, the gain of the video amplifier 1 is increased. Therefore, the video amplifier 1, the clamp circuit 2, the comparator 3, the D flip-flops 5 and 6, the up / down counter 7, the D / A converter 8 and the amplification / offset adjustment circuit 9 are controlled by the automatic gain control (AG).
C) It is a circuit. By the action of this AGC circuit,
The maximum value of the video signal 102 is always attracted to the upper limit reference potential V _T. The black level of the video signal 102 is adjusted to the lower limit reference potential V _B by the clamp circuit 2. Therefore, according to the present embodiment, the A / D converter 10 always receives the input video signal 102 having the amplitude of the full dynamic range,
The A / D converter 10 generates the digital video signal 110 having the highest possible resolution.

In the embodiment of FIG. 1, when the signal 102 at the input of the comparator 3 exceeds the reference potential V _T , the output signal 103 becomes "H" level.
Conversely, the logic level of 3 may be "L", and the count value may be increased when the signal 106 is "H" in the up / down counter 7 and may be decreased when the signal 106 is "L". Absent. Similarly, the present invention can be realized even if the logical values and polarities of the circuits indicated by reference numerals 3 to 9 are different from those in the embodiment. Further, the clock terminal C of the up / down counter 7
Although VD- is added to K, other clock signals may be introduced to the clock terminal CK.

[0020]

As described above with reference to the embodiments,
According to the present invention, the maximum value of the video signal supplied to the A / D converter is always matched with the upper limit potential V _T of the sampling in the A / D converter to generate a high quality digital video signal. A / D conversion circuit can be provided.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an output waveform of a clamp circuit 2 in the embodiment of FIG.

FIG. 3 is a diagram showing input / output waveforms of a comparator 3 in the embodiment of FIG.

4 is a diagram showing input / output waveforms of D flips 5 and 6 in the embodiment of FIG.

FIG. 5 is a circuit block diagram showing a conventional video signal A / D conversion circuit.

[Explanation of symbols]

 1 Video Amplifier 2 Clamp Circuit 3 Comparator 4 Inverter 5, 6 D Flip-Flop 7 Up-Down Counter 8 D / A Converter 9 Amplification / Offset Adjustment Circuit 10 A / D Converter

Claims (2)

[Claims] 1. A video amplifier, the amplification gain of which is controlled by a gain control signal, amplifies an input video signal, the clamped circuit receives the amplified video signal output from the video amplifier, and a predetermined black level in the amplified video signal. By generating the level-adjusted video signal set to the potential and applying the level-adjusted video signal to the A / D converter, a predetermined lower limit potential V _B
And the video signal A / D conversion circuit for converting the digital video signal to the level adjustment video signal between the upper limit electric potential V _T, a comparator for comparing said level adjustment video signal and the upper limit electric potential V _T, the A first D flip-flop for receiving a vertical synchronizing signal relating to an input video signal at a clear terminal and receiving an output of the comparator at a clock terminal, and an output of the first D flip-flop for a data terminal and clocking the vertical synchronizing signal. A second D flip-flop received at the terminal,
An up / down counter that counts clocks and increases or decreases a count value for each clock according to the output of the second D flip-flop, and D / A conversion that converts the output of the up / down counter into an analog signal A vessel,
An amplification / offset adjustment circuit for amplifying the output of the D / A converter and adjusting the direct current level thereof and supplying it to the video amplifier as the gain control signal. The video signal A / D conversion circuit according to claim 1, wherein the signal processing circuit adjusts the polarity of the gain control signal in a direction in which the maximum value of the level-adjusted video signal and the upper limit potential V _T coincide with each other. 2. The video signal A / D conversion circuit according to claim 1, wherein the clock is the vertical synchronization signal.