KR950010063B1 - Auto gain control & clamping circuit of image signal - Google Patents

Abstract

The circuit provides an accurate and stable automatic gain control by preventing the circuit from entering the saturation mode. The circuit comprises a video amplifier(OP11) for clamping the composite video signal(CV); a lowpass filter(11) for filtering the output of video amplifier(OP11); an amplifier(OP12) for amplifying the filter output signal; an A/D converter(12) for converting the amplifier output signal; and a peak detector(13), a black level detector(14), a synchronization level detector(15).

Description

Automatic Gain Control and Clamping Circuit of Image Signal

1 is a clamping circuit diagram of a general image signal processor.

2 is a general automatic gain adjustment circuit.

3 is a diagram illustrating level conversion of a composite video signal.

4 is an automatic gain control and clamping block diagram of a video signal of the present invention.

5 is a detailed block diagram of FIG.

Fig. 6 is a-c diagram of Fig. 6 and a-b of Fig. 7 is a waveform diagram of each part of Fig. 5;

A a in FIG. 8 is a charge / discharge table of the capacitor for etching according to the level comparison result,

b is a charge / discharge table of the clamping capacitor according to the level comparison result.

* Explanation of symbols for main parts of the drawings

11: low pass filter 12: A / D converter

13 peak level comparator 14 black level comparator

15: Sync level comparator 16: Sync and black level sync detector

16A: Horizontal Sync Signal Separator 16B: Delay

17: automatic gain control and clamp logic section 17A, 17D: latch

17B, 17D: Integrator OR11: Oagate

I11: Inverter C _agc : Capacitor for automatic gain adjustment

C _clamp : clamping capacitor

The present invention relates to a preprocessing technique of an analog / digital converter of a video signal, and in particular, to automatically improve the accuracy and stability of the automatic gain and clamping of a video signal inputted to an analog / digital converter by outputting an analog / digital converter. It relates to an automatic gain control and clamping circuit of an image signal.

FIG. 1 is a clamping circuit diagram of a general image signal processor. As shown in FIG. 1, an image amplifier 1 for inverting and amplifying a composite image signal CV and an output signal of the image amplifier 1 are supplied to synchronize the same. It consists of the synchronization signal detection part 2 which detects a signal.

2 is a diagram of a general automatic gain control circuit, in which a black level of a video signal is set to V _RT and a back level is set to V _RB , as shown in FIG. 3. FIG. It demonstrates with reference to.

Analog (A) / Digital (D) conversion of complex video signal (CV) requires preprocessing to process the signal suitable for A / D conversion, including clamp circuit as shown in FIG. A gain control circuit is included.

First, in FIG. 1, the input composite image signal CV is inverted and amplified by the image amplifier OP1 of the image signal amplifier 1 and outputs a signal in the negative direction at the ground level. In the inverted and amplified signal, in the detected asynchronous signal located above the ground, and then rectified and smoothed back to the non-inverting input of the front end, the bottom of the output synchronization signal is always maintained at the ground level.

On the other hand, in the automatic gain control circuit of FIG. 2, the variable resistor VR1 is used to set the black level (-0.3V) of the video signal to V _RT and the back level (level-1.0V) to V _RB for output. do. When the video signal set as described above is input to the A / D converter, the signals except for the synchronous part of the video signal are converted into digital values (0 to 255), where V _RB and V _RT are in accordance with the input range of the A / D converter. I can adjust it.

However, in such a conventional circuit, the circuit composed of four amplifiers and their peripheral circuits is complicated, which leads to a complicated production process and an increase in cost, and the use of a variable resistor to adjust V _RB and V _RT . Therefore, there is a limit to reduce the error, and when the voltage range (V _PP ) of the input signal is greater than 1V, saturation occurs around the back level, and it contains defects such as being sensitive to noise.

The present invention eliminates the error generating element in the process of adjusting the clamping level and the automatic gain level in order to solve such a conventional defect, and devised not to reach the saturation state even if the input signal is out of the standard range. It demonstrates in detail by drawing.

4 is an automatic gain control and clamping block diagram of a video signal according to the present invention. As shown therein, an associative amplifier for adjusting the gain of the composite video signal CV and clamping the composite video signal CV is shown in FIG. OP11), a low pass filter 11 for low pass filtering the output signal of the associative amplifier OP11, an associating amplifier OP12 for amplifying an image signal output from the low pass filter 11 to an appropriate level, and the associative Supply the output signal of the A / D converter 12 and the A / D converter 12 for converting the analog video signal output from the amplifier OP12 into a digital signal and outputting it to the TTI output terminal O _TTL side. A peak level comparator 13, a black level comparator 14, a sync level comparator 15, and a combination of the peak level comparator and the black level comparator Synchronization Pearl of Synchronization Level And the peak level comparator 13 and the black level comparator 14, which are synchronized with the synchronous and black level synchronous detector 16 for detecting the black level synchronous pulse, and the outputs of the synchronous and black level synchronous detector 16, respectively. ), A clamping capacitor C _clamp for controlling the clamping of the image amplifier OP11 by latching an output signal of the sync level comparator 15, and an automatic gain adjustment capacitor C _agc for automatically adjusting gain. The automatic gain control and clamping logic unit 17 for controlling the discharge, and will be described in detail with reference to FIGS. 5 to 8 attached to the operation and effect of the present invention configured as described above.

The digital video signal output from the A / D converter 12 is supplied to the input terminals Q ₀ -Q ₇ of the peak level comparator 13, the black level comparator 14, and the synchronous level comparator 15, and the input terminal ( P ₀ -P ₇ ) are compared with the reference level values supplied through them, and the corresponding values are outputted from them. In this case, each reference level value is expressed in a CCIR601 format indicating a digital standard of an analog video signal. The specified value.

Peak Level Threshold = 240

Black Level Reference Value = 64

Sync Level Reference Value = 0

On the other hand, the composite image signal CV as shown in FIG. 6A is supplied to the sync and black level sync detector 16 so that a blanking section thereof is detected, thereby detecting a sync level sync signal as shown in FIG. 6B. This is supplied via the inverter I11 and then directly supplied to the clock signal CLK of the latch 17C, and on the other hand, is delayed by a predetermined time (4.5 μSec) through the delay unit 16B, as shown in FIG. The black level comparator 14 is supplied to the clock signal CLK of the latch 17A. At this time, the outputs of the black level comparator 14, the sync level comparator 15, and the peak level comparator 13 are synchronized and the black level. The latches 17A and 17C are latched in synchronization with the clock signal CLK output from the sync detector 16, respectively.

A square wave as shown in a of FIG. 7 is output from the latch 17A, which is shaped as shown in FIG. 7B through an integrator 17B, and then to a non-inverting input terminal of the associative amplifier OP11. The charged clamping capacitor C _clamp is charged and charged, and the pulse output from the latch 17C is also shaped at the integrator 17D through the OR gate OR11, and then the automatic gain adjusting capacitor C _{agc is} connected. charge is thereby discharged, so that the automatic gain adjustment capacitor charging and discharging is made, as shown in FIG degrees claim 8 a, capacitors for clamping (C _clamp) charging and discharging of a (C _agc) according to the in FIG degrees claim 8 b It is done together.

When the A / D converted value is D, the black level comparator 14, the sync level comparator 15, and the peak level comparator 13 have D <64, D <0, and D <240, respectively. A square wave such as a is output, and the square wave signals are stored in the latches 17A and 17B, respectively.

At this time, the synchronization and black level synchronization signals are detected by the synchronization and black level synchronization detectors 16, and the values stored in the latches 17A and 17B in synchronization with the respective detected synchronization signals are integrators 17B and ( 17D). The output of the integrator 17B controls the clamping capacitor C _clamp to charge in a section in which a square wave exists and to discharge in a section in which it does not exist.

That is, a larger A / D converted value (D) the clamping capacitor when is input (C _agc) to discharge to the level of the voltage drop to be supplied to the inverting input terminal of the operational amplifier (OP11) than the black level reference value (64) Be sure to In addition, the integrator 17D operates in the same manner as the integrator 17B to control charging and discharging of the automatic gain adjusting capacitor _{Ca acc} for automatic gain adjustment.

As a result, the inverting input and the automatic gain control input of the image amplifier OP11 are controlled to achieve automatic gain adjustment.

As described in detail above, the present invention ensures accuracy by fixing the previous level to a digital value in adjusting the clamping level and the automatic gain adjustment level, and when the input signal is outside the standard voltage range, By adjusting the lower level of the synchronization signal, the saturation state can be prevented, and the digital circuit has the effect of miniaturizing the product and expecting stability against noise.

Claims (3)

An image amplifier OP11 for adjusting the gain of the composite image signal CV and clamping the composite image signal CV, and a low pass filter 11 for low-pass filtering the output signal of the image amplifier OP11; An amplifier OP12 for amplifying the video signal output from the low pass filter 11 to an appropriate level, an A / D converter 12 for converting an analog video signal output from the amplifier OP12 into a digital signal; A peak level comparator 13 and a black level comparator for receiving the output signal of the A / D converter 12 and comparing the output signal with a preset reference level value to detect difference values for peak level, black level, and synchronization level, respectively. (14), a sync level comparator 15, a sync and black level sync detector 16 for detecting a sync pulse and a black level sync pulse of the sync level from the composite video signal CV; The peak level synchronized with the output of the level synchronization detector 16 A clamping capacitor C _clamp for controlling the clamping of the image amplifier OP11 by latching the output signals of the comparator 13, the black level comparator 14, and the sync level comparator 15, and for automatically adjusting the gain. An automatic gain adjustment and clamping circuit comprising an automatic gain adjustment and clamping logic unit (17) for controlling charging and discharging of an automatic gain control capacitor (C _agc ). The latch of claim 1, wherein the automatic gain adjusting and clamping logic unit 17 latches the difference signal output from the black level comparator 14 in synchronization with the signal of the synchronization and black level synchronization detectors 15. 17A), an integrator 17B for shaping the output signal of the latch 17A and outputting it to the clamping capacitor C _clamp , and the peak level in synchronization with the output signal of the synchronous and black level synchronization detector 16; The latch 17C for latching the difference signal output from the comparator 13 and the sync level comparator 15 and the signal supplied from the latch 17C are _shaped and outputted to the automatic gain control capacitor C _agc . An automatic gain adjustment clamping circuit comprising an integrator 17D. The automatic gain control and clamping logic unit 17 discharges the voltage charged in the clamping capacitor C _clamp when the A / D converted value is greater than the black level reference value. The automatic gain control and clamping circuit of a video signal, characterized in that configured to discharge the voltage charged in the automatic gain control capacitor (C _agc ) when the value is larger than the synchronization level reference value or larger than the peak level reference value.