JP2000137048A - Noise level determining circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably provide a noise level-deteremined result to precisely determine a noise level even when a dynamic range of a circuit is not secured. SOLUTION: This circuit has a comparator 3 to which a noise signal NS and a reference voltage Vref are input to output a comparison signal of a logic level in response to a level difference relation between a level of the noise signal NS and the reference voltage Vref, an up-down counter circuit 5 upcount-operated or downcount-operated in response to the logic level to output a count value in order, and a determining circuit 6 for outputting to the counter circuit 5 a reset signal to reset the count value to a reference count value between a first count value and a second count value when the count value reaches to the first count value or the second count value, and for determining concurrently the level of the noise signal NS with respect to a level of a reference voltage signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise level discriminating circuit for discriminating the level of noise contained in a signal such as a video signal of a television device.

[0002]

2. Description of the Related Art Conventionally, a noise level detecting circuit for detecting the level of noise contained in a video signal of a television apparatus or the like, for example, extracts a noise component of the video signal and peak-holds the noise component signal to obtain a direct current. There is known a device which converts a noise component into a component and compares the component with a reference voltage to detect a noise level. For example, the noise level detection circuit shown in FIG. 5 is a noise detection timing pulse generation circuit 10 that generates a timing pulse for cutting out a signal for detecting noise from a video signal.
1, a noise detection circuit 102 that extracts a noise component from a video signal and converts it into a DC component by a peak hold circuit, for example, and compares a DC voltage of an output signal from the noise detection circuit 102 with a reference voltage to obtain a noise level. 103, a reference voltage power supply 104 for generating a reference voltage for the comparator 103, and a comparator 1
03, a noise determination logic circuit 105 that outputs a determination signal STS based on the output signal of the hysteresis circuit 10
6.

[0003] Noise detection timing pulse generation circuit 1
In the video signal input to 01, a noise component is extracted in synchronization with the timing pulse. The extracted noise component is converted into a DC component by the peak hold circuit of the noise detection circuit 102. The signal converted into the DC voltage is compared with the reference voltage by the comparator 103. If the noise level is higher than the reference voltage, a logical value “1” is detected. If the noise level is lower than the reference voltage, Detects a logical value “0”. The detection result of the comparator 103 is input to the noise determination logic circuit 105, the noise level is determined based on the detection result, and a determination signal STS is output.

When the DC voltage output from the noise detection circuit 102 is close to the reference voltage of the comparator 103, the hysteresis circuit 106 inverts the detection result of the comparator 103 frequently and cannot obtain a stable result. Is provided to stabilize the detection result. If the detection result of the comparator 103 is not stable, for example, it is difficult to perform image quality adjustment based on the detection result of the comparator 103. Hysteresis circuit 106
Is a circuit for switching the reference voltage input to the comparator 103 according to the output voltage of the comparator 103. FIG. 6 is a diagram for explaining the function of the hysteresis circuit. As shown in FIG. 6A, when the hysteresis circuit is not provided, the reference voltage is constant even when the output voltage (comparison voltage) of the noise detection circuit 102 exceeds the reference voltage. The voltage changes frequently and is not stable. On the other hand, as shown in FIG. 6B, when a hysteresis circuit is provided,
At the moment when the comparison voltage of No. 2 exceeds the reference voltage, the reference voltage is switched to a lower voltage, and the output voltage of the comparator 103 does not change until the noise level becomes lower than the switched reference voltage. A stable detection result of the comparator 103 is obtained.

[0005]

However, in the above method, when the noise level is detected, the reference voltage input to the comparator 103 is switched by the hysteresis circuit. Therefore, the stability of the detection result of the comparator 103 is reduced. In order to perform the adjustment, it is necessary to adjust and change the hysteresis voltage of the hysteresis circuit, and a circuit including the comparator 103 needs at least a dynamic range corresponding to the hysteresis voltage. Therefore, if the required dynamic range cannot be secured, the detection result of the comparator 103 cannot be sufficiently stabilized. When a plurality of comparators 103 to which a plurality of different reference voltages are input are provided and it is desired to accurately determine the level of the noise signal, a circuit including the comparator 103 corresponds to a hysteresis voltage for each reference voltage. A dynamic range is required. Therefore, when a necessary dynamic range cannot be secured in the circuit including the comparator 103, the detection result of the comparator 103 cannot be stabilized, and it is difficult to accurately determine the level of the noise signal. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and it is possible to stably obtain a noise level determination result, and to accurately determine a noise level even when a dynamic range of a circuit cannot be secured. An object of the present invention is to provide a noise level determination circuit.

[0007]

According to the present invention, a noise signal and a reference voltage signal are inputted, and a comparison signal of a logical level corresponding to a magnitude relation between the level of the noise signal and the level of the reference voltage signal is output. A comparison circuit that performs an up-count operation or a down-count operation according to the logical level in synchronization with a predetermined clock signal, and an up-down counter circuit that sequentially outputs a count value; When the count value or the second count value is reached, the count value is compared with the first count value and the second count value.
And a discrimination circuit for outputting a return signal for returning to a reference count value between the count value and the reference value signal to the up / down counter circuit, and simultaneously outputting a determination signal for determining the level of the noise signal with respect to the level of the reference voltage signal. .

The up / down counter circuit does not perform a counting operation until the logical level of the comparison signal changes after the input of the return signal.

The reference count value is an intermediate count value between the first count value and the second count value.

The comparison circuit includes a plurality of comparison circuits to which a noise signal and a reference voltage signal of a different level are input, respectively, and the up / down counter circuit outputs a comparison signal output from the plurality of comparison circuits. The circuit includes a plurality of up / down counter circuits for performing a count operation, and the determination circuit determines the level of the noise signal based on a plurality of count values output from the plurality of up / down counter circuits.

In the present invention, the result of comparison between the level of the noise signal and the reference voltage is output as a logical value from the comparison circuit,
The up-down counter circuit performs an up-count operation or a down-count operation according to a logical value, and the count value increases or decreases. When the count value of the up / down counter circuit reaches the first or second count value, the determination circuit returns the count value of the up / down counter circuit to the reference count value and determines the level of the noise signal with respect to the reference voltage. Output a signal. Therefore, the discrimination signal output from the discrimination circuit maintains a constant state until the count value of the up / down counter circuit reaches the first or second count value, and the level of the noise signal rises and falls near the reference voltage. Even when the output of the comparison circuit is not stable, the discrimination signal output from the discrimination circuit is stable. Further, if the range between the first count value and the second count value is adjusted, the stability of the determination signal can be arbitrarily adjusted without being limited by the dynamic range of the circuit.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a noise level determination circuit according to one embodiment of the present invention. The noise level determination circuit shown in FIG. 1 includes a noise detection timing pulse generation circuit 1, a noise detection circuit 2, a comparator 3, a reference voltage power supply 104, an up / down counter circuit 5, and a determination circuit 6.

Noise detection timing pulse generation circuit 2
Is a circuit for generating a timing pulse signal TP for extracting a noise component included in the video signal SG, for example. FIG. 2 is a diagram illustrating a configuration example of the noise detection timing pulse generation circuit 1. As shown in FIG. 2, the timing pulse generation circuit 1 for noise detection includes a vertical synchronization signal separation circuit 21 and a counter circuit 22. The vertical synchronization signal separation circuit 21 is a circuit that selectively extracts a video signal SG that is a composite synchronization signal including a horizontal synchronization signal, a vertical synchronization signal, and the like. The counter circuit 22 outputs the vertical synchronization signal 21 extracted by the vertical synchronization signal separation circuit 21.
s and a clock signal CLK of a predetermined frequency, for example, 500 KHz, are inputted, a rising edge of the vertical synchronizing signal 21s is detected, counting is performed based on the clock signal CLK, and a timing pulse signal TP synchronized with the vertical synchronizing signal 21s is output. Circuit.

The noise detection circuit 2 is a circuit that extracts a noise component from a video signal, converts the noise component into a DC component, and outputs the DC component. FIG. 3 is a diagram illustrating a configuration example of the noise detection circuit 2. As shown in FIG. 3, the noise detection circuit 2 includes an amplification circuit 31, a switch circuit 32, a conversion circuit 33, and a peak hold circuit 34.

The amplification circuit 31 amplifies the video signal SG by, for example, about 10 dB and outputs the amplified signal. The amplification circuit 31 is provided to amplify a noise component included in the video signal SG to a detectable level. The switch circuit 32
This is a circuit that turns on and off according to the timing pulse signal TP output from the noise detection timing pulse generation circuit 1. Since the timing pulse signal TP is synchronized with the rising edge of the vertical synchronization signal 21s, the switch circuit 32 is turned on and off in synchronization with the vertical synchronization signal 21s.

The conversion circuit 33 is a circuit for converting the level of a logarithmically changing noise component of the video signal SG passed through the amplifier circuit 31 and the switch circuit 32 so as to linearly change. The peak hold circuit 34 includes a conversion circuit 33
Hold the peak level of the linearly converted signal output from the
Is a circuit that outputs.

The comparator 3 compares the level of the noise signal NS output from the noise detection circuit 2 with the reference voltage Vref output from the reference voltage power supply 4, and outputs a comparison signal 3s of a logical level corresponding to the magnitude relationship between the two. Is a circuit that outputs. For example, when the level of the noise signal NS is the reference voltage V
If it is larger than ref, the high-level comparison signal 3s
And outputs a low-level comparison signal 3s when the level of the noise signal NS is lower than the reference voltage Vref.

The up / down counter circuit 5 receives the comparison signal 3s from the comparator 3, the timing pulse signal TP output from the noise detection timing pulse generation circuit 1, and the timing pulse signal TP. As a clock, an up-count operation or a down-count operation is performed according to the level state of the comparison signal 3s, and a count value is sequentially output. That is, when the comparison signal 3s is at a high level, an up-count operation is performed, and when the comparison signal 3s is at a low level, a down-count operation is performed.

The up / down counter circuit 5 includes:
When the reset signal RST is input from the determination circuit 6 and the reset signal RST is input, the up / down counter circuit 5 returns the count value to a predetermined reference count value and changes the level state of the comparison signal 3s. Stop the count operation until. For the up-down counter circuit 5, for example, a 4-bit up-down counter capable of counting values from 0 to 15 can be used. The above-mentioned reference count value is set to a maximum count value of 15 and a minimum count value of 0. Is set to 8, which is halfway between

The determination circuit 6 receives the count value from the up / down counter circuit 5 and outputs a determination signal STS for determining the level of the noise signal NS with respect to the reference voltage Vref based on the count value. Specifically, the count value from the up / down counter circuit 5 is:
For example, when it reaches 15, it is determined that the level of the noise signal NS is higher than the reference voltage Vref, and the determination signal ST
S is set to the high level, and the reset signal RTS
Is output to the up / down counter circuit 5. When the count value from the up / down counter circuit 5 reaches, for example, 0, it is determined that the level of the noise signal NS is lower than the reference voltage Vref, the state of the determination signal STS is set to low level, and reset. The signal RTS is output to the up / down counter circuit 5.

Next, an example of the operation of the noise level determination circuit having the above configuration will be described with reference to FIG. 4A shows the relationship between the noise signal NS input to the comparator 3 and the reference voltage Vref, and FIG.
Shows the comparison signal 3s output from the comparator 3, (c) shows the count value output from the up / down counter circuit 5, and (d) shows the output state of the discrimination signal STS of the discrimination circuit 6. Is shown.

First, when the video signal SG is input to the noise detection timing pulse generation circuit 1 and the noise detection circuit 2, the noise detection timing pulse generation circuit 1 generates a timing pulse signal TP, and the noise detection circuit 2
Extracts the noise signal NS from the video signal SG in synchronization with the timing pulse signal TP, and outputs it to the comparator 3. In the comparator 3, as shown in FIG. 4A, when the level of the noise signal NS exceeds the reference voltage Vref from a state lower than the reference voltage Vref, the state of the comparison signal 3s is changed as shown in FIG. Is output from low level to high level. As can be seen from FIGS. 4A and 4B, when the level of the noise signal NS rises and falls near the reference voltage Vref, the state of the comparison signal 3s frequently changes.

In the up / down counter circuit 5, FIG.
As shown in (c), when the state of the comparison signal 3s changes from low level to high level, an up-count operation is performed in synchronization with the timing pulse signal TP, and when the state changes from high level to low level, a down-count operation is performed. The count value changes from the reference count value 8.

When the state of the comparison signal 3s continues at a high level, the count value of the up / down counter circuit 5 increases, and the count value reaches 15. When the count value reaches 15, the determination circuit 6 determines that the level of the noise signal NS has exceeded the reference voltage Vref, and outputs the determination signal STS to a high level. At the same time, it outputs a reset signal RST to the up / down counter circuit 5.

When the reset signal RST is input, the up-down counter circuit 5 receives the reset signal RST as shown in FIG.
The count value is returned to 8. The up-down counter circuit 5 stops the counting operation when the level of the comparison signal 3s from the comparator 3 does not change, and stops counting.
The count value remains at 8 as shown in FIG.

From this state, when the level of the noise signal NS falls and rises and falls near the reference voltage Vref, the comparison signal 3s
Changes frequently, and the count value of the up / down counter circuit 5 changes. When the level of the noise signal NS continues to be lower than the reference voltage Vref, the count value of the up / down counter circuit 5 decreases and reaches the count value 0. When the count value reaches 0, the determination circuit 6 determines that the level of the noise signal NS is lower than the reference voltage Vref, and outputs the determination signal STS from a high level state to a low level state. At the same time, it outputs a reset signal RST to the up / down counter circuit 5. When the reset signal RST is input, the up / down counter circuit 5 returns the count value to 8, as shown in FIG.

In the noise level discriminating circuit according to the present embodiment, as can be seen by comparing FIGS. 4B and 4D, even if the state of the comparison signal 3s changes frequently, the state of the discrimination signal STS changes. Can be stabilized. Therefore, the noise level determination circuit according to the present embodiment can stabilize the determination signal STS for determining the level of the noise signal NS with respect to the reference voltage Vref without including a hysteresis circuit for changing the reference voltage Vref. . Further, unlike the case where the hysteresis circuit is used, it is not necessary to secure a dynamic range of the circuit for the hysteresis voltage. In the noise level determination circuit according to the present embodiment, the stability of the determination signal STS can be arbitrarily adjusted by changing the bit length of the up / down counter circuit 5, that is, by changing the maximum and minimum count values. When the length is shorter than the above case, the stability decreases, but the followability of the discrimination signal STS to a change in the level of the noise signal can be improved.
When the bit length is longer than the above case, the stability of the determination signal STS can be further increased.

In the above embodiment, the case where the level of the noise signal NS is compared with the single reference voltage Vref has been described, but the present invention is not limited to this. That is, a plurality of comparators 3 are provided, the level of the noise signal NS is compared with a plurality of different reference voltages Vref, and an up-down counter circuit 5 is provided for each comparison signal 3s. Since it is not necessary to secure the dynamic range of the circuit for the hysteresis voltage, a plurality of reference voltages Vref can be set arbitrarily, and the level of the noise signal NS can be detected accurately from the counter value of each up-down counter circuit 5. It is possible.

[0029]

According to the present invention, a discrimination signal for discriminating the magnitude relation between the noise level and the reference voltage can be stably obtained even if the level of the noise signal rises and falls near the reference voltage to be compared. Further, according to the present invention, if the count length between the first count value and the second count value of the up / down counter is adjusted, the stability of the discrimination signal is not limited by the dynamic range of the circuit. Can be adjusted. Further, according to the present invention, the stability of the discrimination signal can be adjusted without being limited by the dynamic range of the circuit. Therefore, by comparing a plurality of different reference voltages with the level of the noise signal, the noise can be adjusted. The signal level can be detected with high accuracy. Further, according to the present invention, since the discrimination signal can be stably obtained without being limited by the dynamic range of the circuit, the level of the noise signal can be detected with high accuracy even when a low-voltage power supply is used. it can.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a noise level determination circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a noise detection timing pulse generation circuit 1;

FIG. 3 is a diagram illustrating a configuration example of a noise detection circuit;

FIG. 4 is a diagram illustrating an example of an operation of the noise level determination circuit of the noise level determination circuit according to one embodiment of the present invention.

FIG. 5 shows a configuration example of a conventional noise level detection circuit.

FIG. 6 is a diagram for explaining a function of a hysteresis circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Noise detection timing pulse generation circuit, 2 ... Noise detection circuit, 3 ... Comparator, 4 ... Reference power supply, 5 ... Up / down counter circuit, 6 ... Discrimination circuit.

Claims (4)

[Claims] 1. A noise signal and a reference voltage signal are inputted,
A comparison circuit that outputs a comparison signal of a logic level according to a magnitude relationship between the level of the noise signal and the level of the reference voltage signal; and an up-count operation or a synchronization operation in accordance with the logic level in synchronization with a predetermined clock signal. An up-down counter circuit that performs a down-count operation and sequentially outputs a count value; and when the count value reaches a first count value or a second count value, the count value is compared with the first count value. And a determination circuit that outputs a return signal for returning to a reference count value between the count value and the reference value signal to the up / down counter circuit, and simultaneously outputs a determination signal for determining the level of the noise signal with respect to the level of the reference voltage signal. A noise level determining circuit. 2. The noise level discrimination circuit according to claim 1, wherein the up / down counter circuit does not perform a counting operation until the logical level of the comparison signal changes after the input of the return signal. 3. The noise level discrimination circuit according to claim 1, wherein the reference count value is a count value intermediate between the first count value and the second count value. 4. The comparison circuit includes a plurality of comparison circuits to which a noise signal and a reference voltage signal having different levels are respectively input, and the up / down counter circuit includes a comparison circuit that outputs a comparison signal output from each of the plurality of comparison circuits. A plurality of up / down counter circuits for performing a count operation on a signal, wherein the determination circuit determines a level of the noise signal based on a plurality of count values respectively output from the plurality of up / down counter circuits. 2. The noise level determination circuit according to 1.