JP3412456B2 - Automatic gain control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control device used for adjusting a gain of a video signal in a television, a video tape recorder, or the like. 2. Description of the Related Art Conventionally, an automatic gain control device is disclosed in
One described in Japanese Patent No. 5895 is known. FIG. 3 shows a block diagram of a conventional automatic gain control device. In FIG. 3, reference numeral 11 denotes gain adjustment means, 12 denotes AD conversion means, 13 denotes error level detection means, and 18 denotes DA
Conversion means, 19 is an analog video signal input terminal, 110 is a digital video signal output terminal, and 31 is a conversion means.
Hereinafter, a conventional automatic gain control device will be described with reference to FIG. [0004] The analog video signal input from the terminal 19 is adjusted to an optimum gain by the gain adjusting means 11, converted from analog to digital by the AD conversion means 12, becomes a digital video signal, and is output from the terminal 110. Thereafter, the digital video signal is subjected to digital signal processing such as YC separation. On the other hand, the difference between the signal level of the digital video signal and the reference level is detected by the error level detecting means 13. FIG. 4 shows a configuration example of the error level detecting means 13. In FIG. 4, 41 is a sync separation circuit, 42 is a sync tip level detection circuit, 43 is a pedestal level detection circuit,
Reference numerals 4 and 45 denote subtracters, and reference numeral 46 denotes a digital video signal input terminal. The sync separation circuit 41 separates a horizontal sync signal from a digital video signal input from a terminal 46.
FIG. 5A shows an example of a digital video signal, and FIG. 5B shows an example of a separated horizontal synchronizing signal. In the sync chip level detection circuit 42, the horizontal synchronization signal is used as a reference.
A pulse as shown in (c) is generated, and the pulse integrates the digital video signal for one period to output a sync tip level S. Similarly, the pedestal level detection circuit 43
Then, a pulse as shown in FIG. 5D is generated based on the horizontal synchronizing signal, and the pulse integrates the digital video signal for one period to output a pedestal level P. The subtractor 44 calculates PS, and obtains the length of the synchronization signal, that is, the level L = PS of the digital video signal. The difference between this and the reference level L0 is obtained by the subtractor 45, and an error signal L-L0 is output. [0007] The conversion means 31 converts the error signal L-L0 into a digital gain control signal and outputs it. FIG. 6 shows a configuration example of the conversion means 31. FIG.
, 210 is a code determination circuit, 211 is a selection circuit,
213 is an adder, 214 is a flip-flop, 215 is an error signal input terminal, and 216 is a digital gain control signal output terminal. The error signal LL inputted from the terminal 215
The sign judgment circuit 210 judges whether the sign of 0 is positive or negative or 0. When L−L0> 0, the selection circuit 211 selects −1. Therefore, the adder 213 and the flip-flop 21
The value of the counter composed of 4 is decreased by 1. That is, the value of the digital gain control signal output from the terminal 216 decreases by one. This is digital-to-analog converted by the DA converter 18 and the gain of the gain adjuster 11 is varied. Since the analog gain control signal is smaller than before, the level of the analog video signal input to the AD converter 12 is reduced. Therefore, the level of the digital video signal output from the AD conversion means 12 decreases,
The error level L-L0 approaches zero. Conversely, when L-L0 <0, 1 is selected by the selection circuit 211, so that the analog gain control signal becomes larger than before, and the level of the digital video signal output from the AD converter 12 becomes larger. Therefore, L-L0 approaches 0 from a negative direction. Through the above operation, the error level L-L0 gradually approaches 0. When the error level finally matches 0, the sign discrimination circuit 210 detects this and the selection circuit 211 selects 0, so that the adder 213 , The counter constituted by the flip-flop 214 stops its operation. That is, the digital gain control signal is at a constant level, and converges in a state where the level of the synchronizing signal of the digital video signal is equal to L. Actually, the error signal does not completely converge to 0 due to the influence of noise. Therefore, the digital gain control signal always increases or decreases near the point where the error signal becomes 0. By the above operation, the level of the digital video signal is automatically adjusted to a state equal to the reference level. [0010] However, in the above-mentioned conventional configuration, when the level of the digital video signal is made to converge to the reference level at a high speed when the analog video signal is switched by switching the channel or the like, the digital video signal cannot be obtained. There has been a problem that the noise does not converge stably due to the noise superimposed on the video signal, and this appears as fluctuation (flicker) in brightness. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and to provide an automatic gain control device which does not cause flicker even when the level of a digital video signal is converged to a reference level at high speed. [0012] In order to solve this problem, an automatic gain control device according to the present invention varies the gain of an analog video signal according to an analog gain control signal and adjusts the gain of the analog video signal. Gain adjusting means for outputting a signal, AD converting means for converting the analog video signal whose gain has been adjusted into a digital video signal, comparing the magnitude of the digital video signal with a reference level, and using the difference as an error signal. An error level detection means for outputting, a coincidence detection means for detecting that a period in which the error signal is equal to 0 has exceeded a predetermined period, and outputting a detection result as a coincidence detection signal; Large period is longer than specified period
And a comparing means for detecting a time when the error has occurred and outputting a detection result as a mismatch detection signal; shifting to a match state with the match detection signal; shifting to a mismatch state with the mismatch detection signal; State holding means for outputting a state signal indicating that the error signal has been converted to a digital gain control signal and output when the state signal is in the mismatched state, and the state signal has changed from the mismatched state to the matched state. And a DA converter for converting the digital gain control signal into the analog gain control signal. According to the present invention, the gain adjusting means changes the gain of an analog video signal according to an analog gain control signal, and outputs an analog video signal whose gain has been adjusted. The analog video signal whose gain has been adjusted is converted into a digital video signal by AD conversion means. The error level detecting means compares the magnitude of the digital video signal with the reference level, and outputs the difference as an error signal. The coincidence detecting means detects that the period during which the error signal is equal to 0 exceeds a predetermined period ,
The detection result is output as a coincidence detection signal. In the comparing means, the period during which the error signal is larger than the predetermined error is longer than the predetermined period
Detects when a, and outputs the detection result as a mismatch detection signal. The state holding means shifts to the mismatch state by the mismatch detection signal, holds the mismatch state until the match detection signal is output, and shifts to the match state when the match detection signal is output. The level conversion means converts the error signal into a digital gain control signal in the case of a non-match state and outputs the digital gain control signal. The DA converter converts the digital gain control signal into an analog gain control signal, and adjusts the gain of the analog video signal according to the analog gain control signal. Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing an automatic gain control device according to an embodiment of the present invention. In FIG. 1, reference numeral 11 denotes gain adjustment means, 12 denotes AD conversion means, 13 denotes error level detection means, 14 denotes coincidence detection means, 15 denotes comparison means, 16 denotes state holding means, 17 denotes level conversion means,
8 is DA conversion means, 19 is an analog video signal input terminal,
110 is a digital video signal output terminal. Components that perform the same operations as in FIG. 3 described in the section of the prior art are denoted by the same reference numerals. Hereinafter, the automatic gain control device according to the present embodiment will be described with reference to FIG. 1, particularly, the coincidence detecting means 14, the comparing means 15, the state holding means 16, and the level converting means 17 which are characteristic parts of the present invention. . FIG. 2 shows a specific configuration example of the coincidence detecting means 14, the comparing means 15, the state holding means 16, and the level converting means 17. In FIG. 2, reference numeral 21 denotes a coincidence detection circuit;
27 is an up / down counter, 23, 24, 25, 28
Is a comparator, 26 is an OR gate, 29 is a set / reset flip-flop, 210 is a code discriminating circuit, 211 and 21
2 is a selection circuit, 213 is an adder, 214 is a flip-flop, 215 is an error signal input terminal, and 216 is a digital gain control signal output terminal. In the operation as described in the section of the prior art,
An error signal L-L0 is input from a terminal 215. The coincidence detecting means 14 outputs a coincidence detection signal when the period when L−L0 = 0 exceeds a predetermined period. Hereinafter, the operation of the coincidence detecting means 14 will be described. The coincidence detecting circuit 21 outputs 1 when L-L0 = 0.
And outputs 0 when L−L0 ≠ 0. The up-down counter 22 increases the output by one when the output of the coincidence detection circuit 21 is 1, and decreases the output by 1 when the output is 0. However, the minimum value is 0. Therefore, if L-L0 ≠ 0 continues continuously, the output becomes 0, and if L-L0 = 0 continues, the output increases by one. The comparator 23 compares the output of the up / down counter 22 with a constant M. When the output of the up / down counter 22 exceeds M, that is, when the error signal L−L0 becomes 0 continuously for M times or more, the error signal is output. Is determined to be zero, and 1 is output to the coincidence detection signal. The constant M is a constant that determines the accuracy of coincidence detection, and is usually selected to be about several H (1H is one horizontal cycle). The comparing means 15 outputs a non-coincidence detection signal when the error signal L-L0 exceeds a predetermined level and the period becomes longer than a predetermined period. Hereinafter, the operation of the comparing means 15 will be described. The comparator 24 determines that the error signal L-L0 is a constant L1.
When it is larger, 1 is output. The comparator 25 outputs the error signal L−
When L0 is smaller than the constant L2, 1 is output. Where L
2 <0 <L1. The constants L1 and L2 are set for the purpose of preventing the operation of the comparing means 15 with the noise component of the error signal, and are selected to be sufficiently larger than the noise level of the error signal. Since the noise component is usually symmetric,
= -L1. Next, the logical sum of the outputs of the comparators 24 and 25 is
Take at R gate 26. As a result, the output of the OR gate 26 becomes 1 when the error signal goes out of 0 beyond the range of the noise level. The output of the OR gate 26 is counted by an up / down counter 27 like the up / down counter 22 and the comparator 23, and compared with a constant N by a comparator 28. That is, when the error signal L-L0 exceeds the range defined by the constants L1 and L2 continuously N times or more, it is determined that the error signal is not zero, and 1 is output as the mismatch detection signal. The constant N is a constant that determines the accuracy of mismatch detection, and is usually selected to be several hundreds of hours. Selecting the constant M for coincidence detection to several H and the constant N for non-coincidence detection to several hundred H is because the digital video signal is quickly pulled to a predetermined level.
This is to perform stable gain adjustment that is not affected by noise once the pull-in is performed. The state holding means 16 comprises a set / reset flip-flop 29. The output is set to 1 when the coincidence detection signal becomes 1, and 0 when the inconsistency detection signal is 1.
Is reset to That is, when the match detection signal is input, the state holding means 16 holds the match state (output = 1) until the mismatch detection signal is input, and conversely, when the mismatch detection signal is input, the match detection signal is input. Until then, the mismatch state (output = 0) is held. In the level conversion means 17, the error signal LL
0 is converted to a digital gain control signal and output from terminal 216. When the output of the state holding means 16 is 0 (in a mismatch state), the selection circuit 212 selects the output of the selection circuit 211. The sign discriminating circuit 210 discriminates whether the sign of the error signal L−L0 is positive, 0 or negative, and selects the selecting circuit 2 according to the result.
11 outputs -4, 0 or 1, respectively. When the error voltage is large in the positive direction, it is when the level of the analog video signal is large, and may exceed the dynamic range of the AD converter 12. Therefore, the selection circuit 21
The output of 1 is -4, and the response is four times faster than when the error signal is negative. The counter composed of the adder 213 and the flip-flop 214 increases or decreases according to the output of the selection circuit 211, that is, the digital gain control signal increases or decreases. Eventually, as described in the section of the related art, the error signal converges to zero. Then, a coincidence detection signal is output from the coincidence detection means 14, and the output of the state holding means 16 changes to 1 (coincidence state).
Since 2 outputs 0, the digital gain control signal becomes constant. At this time, the error signal is a constant L including noise.
1, since it is within the range determined by L2, the digital gain control signal keeps a constant value without being affected by noise. Therefore, in this state, a constant gain adjustment is performed by the gain adjustment means 11, and a stable operation without flicker can be performed. When the analog video signal is switched by channel switching or the like, the error voltage exceeds the range determined by the constants L1 and L2 for a predetermined period.
Changes to 0 (unmatched state). Then, by the same operation as described above, the state finally changes to the coincidence state again, and thereafter the operation is stabilized. As described above, according to the present invention, a high-speed response is performed in a non-coincidence state, and a response is stopped in a coincidence state, so that a high-speed response and stable gain adjustment without flicker can be performed. In the above description, the error level detecting means 13 detects the difference between the magnitude of the synchronization signal of the video signal and the reference level. However, the difference between the burst level of the color signal and the reference level is determined. According to the configuration for detecting the color signal, the gain can be adjusted at high speed without flicker similarly. As described above, according to the present invention, gain adjustment means for varying the gain of an analog video signal, and AD conversion means for converting the analog video signal whose gain has been adjusted into a digital video signal. , this in which the error level detecting means for outputting a comparison error signal the magnitude of the digital video signal with a reference level, a period error signal is equal to 0 exceeds a predetermined time period
And coincidence detection means for detecting the door state holding error signal to output a state signal indicating a comparison means is greater than the period predetermined error is detected outputs when equal to or more than a predetermined period of time, the matching state inconsistent state Means, a level converting means for converting an error signal into a digital gain control signal in accordance with the state signal and outputting the digital gain control signal, and a DA converting means for converting the digital gain control signal into an analog gain control signal. Stable gain adjustment without flicker is possible,
Its practical effect is great.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a configuration of an automatic gain adjustment device according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating a specific configuration example according to the first embodiment. 3 is a block diagram showing a configuration of a conventional automatic gain adjustment device. FIG. 4 is a block diagram showing a specific configuration example of an error level detection unit. FIG. 5 is a signal waveform diagram for explaining the operation of the error level detection unit. 6 Block diagram showing a specific configuration of the conversion means [Explanation of reference numerals] 11 Gain adjustment means 12 AD conversion means 13 Error level detection means 14 Match detection means 15 Comparison means 16 State holding means 17 Level conversion means 18 DA conversion means

Claims (1)

(57) Claims: (1) gain adjusting means for varying the gain of an analog video signal in accordance with an analog gain control signal and outputting an analog video signal whose gain has been adjusted; A / D conversion means for converting the analog video signal into a digital video signal, an error level detection means for comparing the magnitude of the digital video signal with a reference level, and outputting the difference as an error signal, That the equal period has exceeded the predetermined period
And a coincidence detecting means for detecting the result as a coincidence detection signal, and a period in which the error signal is larger than a predetermined error is a predetermined period
Comparing means for detecting the time when the above has occurred , and outputting a detection result as a mismatch detection signal; shifting to a match state by the match detection signal; shifting to a mismatch state by the mismatch detection signal; State holding means for outputting a state signal indicating a state; and when the state signal is in the mismatched state, the error signal is converted into a digital gain control signal and output, and the state signal changes from the mismatched state to the matched state. Level conversion means for holding the digital gain control signal at the time of the conversion and outputting the digital gain control signal in the coincidence state, and DA conversion means for converting the digital gain control signal to the analog gain control signal. Gain control device.