JPH05244631A - Frequency separation circuit - Google Patents

Abstract

PURPOSE:To reduce a separation error by selecting a filter where the level fluctuation of a frequency signal is less based on the fluctuation value of the frequency signal to be separated. CONSTITUTION:A left filter 2 processing a signal more previous than prescribed time on the time base of the frequency signal which is to be separated and a right filter 1 processing a future signal are provided. When fluctuation quantity detectors 10 and 11 detect the frequency signal to be separated, the right filter 1 or the left filter 2 where the level fluctuation of the frequency signal detected based on fluctuation quantity is less is selected. Change quantity data is compared in a magnitude comparator 12, and prescribed delay time is given to the output by a delay equalizer 13, and it becomes output S. The output S is transmitted to gates 3a and 3b as a filter switch signal, and the filter is selected by a high or low signal. Thus, a frequency division circuit where there is few separation errors can be obtained without affecting others even if there is inappropriate data in the past or future on the time base.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency separation circuit used for YC separation of video signals.

[0002]

2. Description of the Related Art For example, Y in a television receiver
In the C separation circuit, a circuit as shown in FIG. 4 is used.

In the figure, a luminance signal Y and a chroma signal C are shown.
In the video signal Y + C including the signal C, only the C signal is separated by the bandpass filter (BPF) 41 of 3.58 MHz. Also, the Y + C signal is a delay equalizer (DL ・ E
Q) 42, and BPF4 by DL EQ42
A delay equal to the delay time of 1 is given.

A part of the output of the DL EQ 42 and a part of the output of the BPF 41 are sent to the subtractor 43, and the subtractor 4
In 3 the BPF4 from the Y + C signal that passed DL EQ42
The component of the C signal separated by 1 is subtracted to separate the Y signal.

[0005]

[Problems to be Solved by the Invention] However, the BPF
No. 41 does not have an ideal characteristic. Therefore, as shown in FIG. 5 (a), the CPF-like component is output to the portion where the C signal originally does not exist, and it also corresponds to the edge of the Y signal. In the portion, the C signal is output as if it were apparently attenuated.

Since the Y + C signal is subtracted by the output of the BPF 41, the obtained Y signal is affected by an erroneous C signal component sent from the BPF 41 and is disturbed as shown in FIG. 5 (b). It is not possible to reproduce the regular luminance signal Y as shown in FIG. The present invention has been made to solve the above-described problems such as signal separation processing, and an object thereof is to provide a frequency separation circuit with a small separation error.

[0007]

SUMMARY OF THE INVENTION A frequency separating circuit of the present invention is a frequency separating circuit for separating a first frequency signal and a second frequency signal from a frequency separated signal. A first filter that processes a signal that is older than a predetermined time point on the time axis, a second filter that processes a signal that is future than the predetermined time point on the time axis of the first frequency signal to be separated, and a separation Of the second frequency signal of the first and second filters based on the fluctuation amount detecting means for detecting the level fluctuation of the second frequency signal to be detected, and the fluctuation value detected by the fluctuation amount detecting means. It is characterized in that it is provided with a selecting means for selecting one of the filters which is less affected by fluctuations.

[0008]

With this configuration, when the level of the signal of the second frequency to be separated fluctuates greatly, the filter that passes the signal at a point far from this fluctuation is selected. By such selection, a signal that is less affected by fluctuations is passed to improve the accuracy of frequency separation.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of this embodiment, and FIGS. 2 (a) and 2 (b) are circuit diagrams of the left and right filters used to obtain the C signal in this embodiment. Here left means
The left side and the right side with respect to the current signal refer to the right side on the time axis.

Further, in FIG. 1, the video signal Y + C of the input signal is n-bit digital data A / D converted by a sampling clock having a frequency four times that of the subcarrier.

Reference numerals 1 and 2 in FIG. 1 denote right and left filters for selecting the chroma signal C, respectively. The filter right 1 and the filter left 2 are configured as shown in FIGS. 2 (a) and 2 (b), respectively.

As shown in FIG. 2 (a), the filter right 1 is obtained by subtracting the current input signal in the adder 1b from the one delayed by 2 clocks by the delay 1a of the input signal, In the adder 1c, the output of 1b is delayed by 4 clocks of this output by the delay 1d and this output is added, and the output of the adder 1c is multiplied by 1/4 in the multiplier 1e and the amplitude is increased. Is output after being equalized.

As shown in FIG. 2 (b), in the filter left 2, the input signal is subtracted from the input signal delayed by two clocks by the delay 2b in the adder 2a, and the output of the subtracter 2a is output. Is added to this output delayed by 4 clocks by the delay 2d in the adder 2c. Furthermore, the output of the adder 2c is multiplied by ¼ in the multiplier 2e to equalize the amplitude, and then delayed by 6 clocks in the delay 2f before being output.

That is, the current data is Dn, and the data delayed by k clocks (data on the left side on the time axis) is Dn-.
If the data advanced by k, k clocks (data on the right side on the time axis) is Dn + k, the output of the adder 1c of the filter right 1 is (Dn-6-Dn-4) + (Dn-2-Dn) become,
The data after 6 clock delays by the delay 2f of the filter left 2 is relatively Dn (that is, Dn-6 is Dn)
Then, the previous equation becomes (Dn-Dn + 2) + (Dn + 4-Dn +
6), and it can be seen that only the data on the right side of Dn is filtered.

The output of the adder 2c of the filter left 2 is (Dn-Dn-2) + (Dn-4-Dn-6), and D
It can be seen that only the data on the left side of n is filtered.

These filter right 1 and filter left 2
Is selected by the gates 3a, 3b, 3c, and the output of either filter 1 or 2 is sent to the subtractor 4. An input signal Y + is supplied to the subtractor 4 via a delay equalizer 5 having a delay time equal to the delay times of the filter right 1 and the filter left 2.
C is sent, and the subtractor 4 subtracts the C signal selected by the filter right 1 or the filter left 2 from the Y + C signal to obtain the luminance signal Y.

Reference numerals 6 and 7 denote 4-clock delays each having a delay time of 4 clocks, which is V1 of the input signal Y + C.
And the output V2 of the 4-clock delay 6 is sent to the adder 8, and the output V2 of the 4-clock delay 6 is subtracted from V1 of the input signal Y + C to output the subtraction result V1-V2.

The output V2 of the 4C clock delay 6
And the output V3 of the 4-clock delay 7 is sent to the adder 9, and the output V2 of the 4-clock delay 6 is subtracted from the output V3 of the 4-clock delay 7, and the subtraction result V3-V2
Is output.

The outputs of adder 8 and adder 9 are sent to detector left 10 and detector right 11, respectively. Detector left 10 and detector right 11 are sent V1 -V2 and V
It outputs the absolute values ΔV1-2 and ΔV3-2 of 3-V2.

The absolute value outputs ΔV1-2 and ΔV3-2 of the detector left 10 and the detector right 11 are compared by the magnitude comparator 12, and the magnitude comparator 1
The output S of No. 2 is set to output "H" under the condition of ΔV1-2 ≥ΔV3-2 and "L" otherwise.

For example, when the brightness changes greatly from V1 to V2, the above condition ΔV1-2 ≧ ΔV3-2
Is satisfied, the output S of the magnitude comparator 12 outputs “H”.

Output S of the magnitude comparator 12
"H" or "L" signal of the delay equalizer 1 having a delay time commensurate with the delay time of the filter right 1 and the filter left 2
It is sent to the gate 3a and the gate 3b via 3 and these gates 3a and 3b are switched to select either the filter right 1 or the filter left 2. That is, the output S is "H"
In the case of, the filter right 1 is selected, and in the case of "L", the filter left 2 is selected. The operation of the embodiment thus configured will be described with reference to the waveform chart shown in FIG.

In the waveform diagram of the input video signal Y + C shown in FIG. 4A, the signals V1, V2, and V3 are data on the left side of four clocks on the time axis with respect to V2, and V3 is This is data on the right side for four clocks.

The output ΔV1-2 of the detector left 10 shows the amount of change on the left side on the time axis of the waveform shown in FIG. 9A, and the output ΔV3-2 of the detector right 11 is relatively on the right side. The amount of change on the right side is shown. These change amount data are shown in (b) and (c) of the same figure.

These change amount data are compared in the magnitude comparator 12, and the output is sent to the delay equalizer 13 and given a predetermined delay time, and then becomes the output S of the delay equalizer 13. It is sent to the gates 3a and 3b as a filter switching signal as shown in FIG. The gates 3a and 3b select either the filter right 1 or the filter left 2 by the "H" or "L" signal.

Of the filter right 1 and the filter left 2, the filter right 1 performs the arithmetic processing of the input signal Y + C by the data on the right side on the time axis. Even if it exists, it is not affected much.

On the other hand, since the filter left 2 is processing the input signal Y + C by the data on the left side on the time axis,
Even if there is inappropriate data on the right side of the time axis, there is little influence.

That is, when the left side change amount of the input signal Y + C is large, the filter right 1 using the right side data is used, and when the right side change amount of the input signal Y + C is large on the time axis. 3 uses the filter left 2 which uses the data on the left side to prevent the output of an erroneous chroma signal C due to a sudden change in luminance or the like.
It is possible to reproduce the correct chroma signal C which is not affected by the luminance signal Y as shown in (e). Further, by using the obtained correct chroma signal C, the correct luminance signal Y can be separated. The present invention is not limited to the above-mentioned embodiments, and can be modified and carried out without changing the gist.

[0029]

According to the present invention, even if there is a large change in one signal waveform to be separated, a filter that is not affected by this change is selected to perform the frequency separation operation.
Accurate frequency separation is possible. Therefore, for example, when it is used in a Y / C separation circuit of a video signal, color bleeding or the like is reduced and the image quality can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a chroma signal separation filter used in the embodiment.

FIG. 3 is a waveform chart for explaining the operation of the same embodiment.

FIG. 4 is a YC separation circuit diagram of a conventional video signal.

FIG. 5 is a waveform diagram for explaining the operation of the conventional YC separation circuit and its problems.

[Explanation of symbols]

1 ... Filter right 1a ... 2 clock delay 1b ... Adder 1c ... Adder 1d ... 4 clock delay 1e ... Multiplier 2 ... Filter left 2a ... Adder 2b ... 2 clock delay 2c ... Adder 2d ... 4 clock delay 2e ... Multiplier 2f ... 6 clock delay 3a, 3b, 3c ... gate 4 ... subtractor 5 ... delay equalizer 6 ... 4 clock delay 7 ... 4 clock delay 8 ... adder 9 ... adder 10 ... detector left 11 ... Detector right 12 ... Magnitude comparator 13 ... Delay equalizer

Claims (2)

[Claims] 1. A frequency separation circuit for separating a first frequency signal and a second frequency signal from a frequency-separated signal, wherein a signal past a predetermined time point on the time axis of the first frequency signal to be separated is A first filter for processing, a second filter for processing a signal of a first frequency signal to be separated, which is a signal in the future after a predetermined time point on the time axis, and a level fluctuation of a second frequency signal to be separated, detected And a selection of selecting one of the first and second filters that is less affected by the level fluctuation of the second frequency signal, based on the fluctuation value detected by the fluctuation amount detection means. A frequency separation circuit comprising: 2. The fluctuation amount detecting means comprises a first delay means for delaying the frequency-separated signal by a first delay time, and a second delay means for delaying a second delay time longer by a predetermined time than the first delay time. First fluctuation amount detecting means for detecting a level fluctuation amount at the current time point and first delay time of the frequency-separated signal, and second fluctuation amount for detecting a level fluctuation amount at the first delay time and the second delay time. The selecting means has a detecting means, and the selecting means compares the variation amounts of the first and second variation amount detecting means with each other, and the variation amount of the first variation amount detecting means is the second variation amount detecting means. The filter selection is such that the second filter is selected when the variation amount is larger than the variation amount, and the first filter is selected when the variation amount of the second variation amount detecting means is greater than the variation amount of the first variation amount detecting means. A means according to claim 1, further comprising: Wave number separation circuit.