KR940003357A

KR940003357A - Automatic Gain Control and Clamping Circuit of Image Signal

Info

Publication number: KR940003357A
Application number: KR1019920012537A
Authority: KR
Inventors: 지용진
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1992-07-14
Filing date: 1992-07-14
Publication date: 1994-02-21
Also published as: KR950010063B1

Abstract

본 발명은 영상신호의 아날로그/디지탈 변환기의 전처리 기술에 관한 것으로, A/D변환기(12)에서 출력되는 디지탈 영상신호를 흑레벨 비교기(14), 동기레벨 비교기(15) 및 피크레벨 비교기(13)에 공급하여 여기서 기 저장된 해당 기준치와 비교되어 흑레벨 차값이 래치(17A)에 래치되고, 동기레벨 및 피크레벨 차값이 래치(17C)에 래치되며, 이렇게 래치된 값이 적분기(17B), (17D)에 의해 정형화된 후, 그 정형화된 출력이 콘덴서(C_agc), (C_clamp)에 충반전되고, 그 콘덴서(C_agc), (C_clamp)의 출력신호에 의해 영상증폭기(AMP11)의 클램프 및 자동 에이지씨가 제어되도록한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a preprocessing technique of an analog / digital converter of a video signal. The digital video signal output from the A / D converter 12 is converted into a black level comparator 14, a sync level comparator 15, and a peak level comparator 13. ), The black level difference value is latched to the latch 17A, and the sync level and peak level difference values are latched to the latch 17C, and the latched values are integrators 17B and ( 17D) after the shaping by a, of the structured output capacitor (C _agc), (and charge reversal on the C _clamp), the capacitor (C _agc), (the video amplifier (AMP11) by the output signal of the C _clamp) The clamp and automatic age control are controlled.

Description

Automatic Gain Control and Clamping Circuit of Image Signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 일반적인 영상신호 처리기의 클램핑 회로도,1 is a clamping circuit diagram of a general video signal processor,

제2도는 일반적인 자동 이득 조절 회로도,2 is a general automatic gain control circuit,

제3도는 복합 영상신호의 레벨 변환 예시도,3 is an exemplary diagram of level conversion of a composite video signal.

제4도는 본 발명의 영상신호의 자동 이득 조절 및 클램핑 블록도,4 is an automatic gain control and clamping block diagram of a video signal of the present invention;

제5도는 제4도의 상세 블록도,5 is a detailed block diagram of FIG.

제6도의 (가)-(다) 및 제7도의 (가),(나)는 제5도 각부의 파형도,(A)-(c) of FIG. 6 and (a) and (b) of FIG.

제8도의 (가)는 레벨 비교결과에 따른 에지씨용 콘덴서의 충방전표이고, (나)는 레벨 비교결과에 따른 클램피용 콘덴서의 충반전 표.8A is a charge / discharge table of the edge seed capacitor according to the level comparison result, and (b) a charge / discharge table of the clamping capacitor according to the level comparison result.

Claims

An image amplifier OP11 for adjusting the gain of the doublet video signal CV and clamping the complex video signal CV, and a low pass filter 11 for low pass filtering the output signal of the video amplifier OP11; An amplifier OP12 that amplifies the image signal output from the low pass filter 11 to an appropriate level, and converts the analog image signal output from the amplifier OP12 into a digital signal and converts it into a digital signal (0 _TTL ). The output signal of the A / D converter 12 and the A / D converter 12 output to the side are supplied and compared with the preset reference level value to detect the difference values for the peak level, the black level, and the synchronization level, respectively. A peak level comparator 13, a black level comparator 14, a sync level comparator 15, and a sync and black level detector 16 for detecting the level and the black level of the sync signal from the composite video signal CV. ) And the output of the synchronous and black level detector 16 Is to control the seed capacitor (C _clamp) for controlling the clamping and the edge of the peak level of the comparator 13, the black-level comparator 14, it latches the output signal of the synchronizing level comparator 15, the video amplifier (OP11) An automatic gain control and clamping circuit of an image signal, characterized by comprising an age and clamp logic unit (17) for controlling charging and discharging of a capacitor (C _agc ).

The latch 17A according to claim 1, wherein the age and clamp logic unit 17 latches the difference signal output from the black level comparator 14 in synchronization with the signal to the output of the synchronization and black level detector 16. And the peak level comparator in synchronization with the output signal of the integrator 17B for shaping the output signal of the latch 17A and outputting it to the edge seed capacitor C _agc . 13) and the latch 17C for latching the difference signal output from the sync level comparator 15, and the signal supplied from the latch 17C through the oragate OR11, and the clamp capacitor C Automatic gain adjustment and clamping circuit of the video signal, characterized in that consisting of an integrator (17D) output to the _clamp side.

※ Note: The disclosure is based on the initial application.