JP4335081B2 - Signal DC voltage stabilizing circuit and video equipment including the same - Google Patents

Description

  In particular, the present invention performs A / D conversion on video system signals such as an output signal of a CCD (Charge Coupled Devices) area sensor, an output signal of a CCD linear sensor, an output signal of a CMOS sensor, a television signal, a video signal, and an RGB signal. The present invention relates to a signal DC voltage stabilization circuit that performs signal DC voltage stabilization at the time, and a CCD camera, a copying machine, an image scanner device, a television device, a video tape recorder device, and other video equipment having the signal DC voltage stabilization circuit Is.

  There exists patent document 1 as a prior art document which concerns on this invention.

  Further, a circuit as shown in FIG. 7 is used as a conventional signal DC voltage stabilizing circuit. In FIG. 7, an input analog video signal is amplified to an optimum amplitude by the variable gain amplifier 1, and a DC voltage is defined (clamped) in accordance with a control terminal voltage applied to the control terminal 2a by the DC control circuit 2. It is converted into a digital signal by the D converter 3 and output.

  This digital signal, that is, the digital video signal output from the A / D converter 3 is black in the active period of the clamp pulse in which the active period exists in the black reference period in the horizontal blanking period of the input analog video signal in the data extraction circuit 4. The level (DC voltage) is extracted and output as M-bit digital data having the cycle of the clamp pulse, and is converted into analog data by the D / A converter 5.

  This analog data, that is, the analog data output from the D / A converter 5 is compared with the reference voltage of the reference voltage source 6 determined in advance by the subtracting circuit 7. When the analog data is smaller than the reference voltage, the capacitor 8 is turned on. The control terminal voltage that is charged and applied to the control terminal of the DC control circuit 2 is increased, thereby increasing the DC voltage of the analog video signal input to the A / D converter 3.

  Conversely, when the analog data output from the D / A converter 5 is greater than the reference voltage of the reference voltage source 6, the capacitor 8 is discharged to lower the control terminal voltage applied to the control terminal of the DC control circuit 2. Thereby, the DC voltage of the analog video signal input to the A / D converter 3 is lowered.

  When the operation as described above is performed rapidly, video noise is generated due to a rapid change in the black level. Therefore, the relationship between the input differential voltage in the subtraction circuit 7 and the charge / discharge current for the capacitor 8 is shown in FIG. As shown in Accordingly, the black level of the output digital video signal of the A / D converter 3 is stably maintained at a predetermined level by slowly charging and discharging with a relatively small current.

  According to the above conventional signal DC voltage stabilization circuit, when the black level of the output digital video signal fluctuates relatively small with respect to the predetermined level for some reason, it returns to the predetermined level in a relatively short time by feedback. To do. However, when the black level greatly fluctuates with respect to a predetermined level, it takes a long time to recover, and there is a problem that the image is disturbed such that the black of the video shifts during that time.

  Such a state occurs when the power is turned on, an abrupt change in the amplitude of the input analog video signal, that is, a brightness, and a sudden change in the gain of the variable gain amplifier 1 accompanying it, appearing as a lateral noise at the top of the screen, The quality of the image is lowered.

  In order to solve this difficulty, a circuit as shown in FIG. 8 has also been proposed. FIG. 8 is disclosed in Patent Document 1. In FIG. 8, 51 is a capacitor, 52 is an A / D converter, 53 is a first buffer, 54 is a second buffer, 55 is a first comparator, 56 is a switch unit, 57 is a stabilization delay circuit, 58 is The second comparator, 59 is an n-channel CMOS transistor, 60 is a capacitor, and R1 and R2 are resistors.

  In the circuit shown in FIG. 8, when the clamp level (black level) of the output digital signal changes in the vicinity of the clamp code in the first comparator 55, the output of the first comparator 55 changes to High / Low. The first buffer 53 is controlled, whereby the capacitor 51 is charged and discharged with a relatively small current. The clamp level is maintained at a predetermined level by the feedback circuit as described above.

  On the other hand, when the clamp level of the output digital signal is greatly reduced and falls below the limit code in the second comparator 58, the p-channel CMOS transistor constituting the second buffer 54 is turned on, and the capacitor 51 is instantaneously supplied with a large current. Charge and immediately increase the clamp level. FIG. 6 shows the relationship between the difference between the output digital signal and the clamp cord and the charge / discharge current to the capacitor 51 in that operation.

  However, in general, there is noise in the input analog video signal, and even if the clamp level of the output digital signal does not change, if the noise component falls slightly below the limit code in the second comparator 58, The second buffer 54 instantaneously charges the capacitor 51 with a large current, which causes a problem that the clamp level rises higher than a predetermined level, causing image distortion.

In order to avoid this problem, in the circuit of FIG. 8, the stabilization delay circuit 57 causes the switch unit 56 only when the clamp level of the output digital signal is lower than the limit code in the second comparator 58 for a predetermined time. Is turned on and the second buffer 54 is operated to charge the capacitor 51 rapidly.
Japanese Patent Laid-Open No. 11-146229

  However, the operation as described above has a problem in that the disturbance of the image resulting from the decrease in the clamp level continues for a certain period of time until the second buffer 54 is turned on.

  Further, when the decrease in the clamp level of the output digital signal slightly falls below the limit code, the capacitor 51 is rapidly charged with substantially the same large amount of current as in the case where it greatly falls, thereby increasing the clamp level. It becomes too high beyond the level of the above, and has a problem of lacking stability.

  As a countermeasure, if the current value of the second buffer 54 is made relatively small, it takes time to recover when the clamp level of the output digital signal greatly falls below the limit code. If the limit code is set lower as another countermeasure, it takes time to recover when the lowering of the clamp level does not fall below the limit code. There is a problem that the disturbance of the image derived from the problem continues.

  The present invention solves such a problem, and its purpose is to immediately return at a speed corresponding to the amount of change even when the black level of the video signal greatly fluctuates with respect to a predetermined level. It is intended to provide a signal DC voltage stabilization circuit that can be stabilized and suppress image disturbance, and a video device including the signal DC voltage stabilization circuit.

  In other words, in a steady state where the black level of the video signal exists in the vicinity of the predetermined level, the video signal is stabilized without being affected by fluctuation factors such as noise, and when the black level of the video signal greatly fluctuates from the predetermined level, An object of the present invention is to provide a signal DC voltage stabilizing circuit that can restore the black level of a video signal to a predetermined level in a short time without malfunction, and a video device including the signal DC voltage stabilizing circuit.

  In order to solve the above problems, the present invention is a result of comparing a predetermined reference voltage with a value obtained by D / A converting digital data extracted from a black reference period in a horizontal blanking period of an output digital signal of an A / D converter. The capacitor is charged / discharged with a different amount of current depending on the size of the capacitor, and a loop for controlling the DC voltage of the black reference period in the analog video signal input to the A / D converter according to the voltage of the capacitor is configured. And

  According to such a configuration, the DC voltage (black level) of the black reference period in the output digital signal of the A / D converter is set with a time constant corresponding to the magnitude of the fluctuation for various fluctuation factors. It works to always match the value.

  This will be described in detail below.

  The signal DC stabilization circuit of the present invention includes an amplifier that amplifies an input analog video signal, a DC control circuit that defines (clamps) a DC voltage of an output analog video signal of the amplifier according to a control terminal voltage applied to a control terminal, An analog video signal output from the DC control circuit in the conversion cycle is converted to an N-bit digital signal (N is a positive integer) and output, and an N-bit digital signal output from the A / D converter is input. A data extraction circuit that extracts the active period of the clamp pulse having an active period in the black reference period in the horizontal blanking period of the analog video signal and outputs it as M-bit digital data of N bits or less having a clamp pulse period; M bit digital data of N bits or less output from the extraction circuit is converted into analog data The control terminal voltage of the DC control circuit is generated by charging / discharging the capacitor according to the difference between the D / A converter to be converted and the analog data output from the D / A converter and the predetermined reference voltage during the active period of the clamp pulse. Only when the difference between the first subtracting circuit and the analog data output from the D / A converter during the active period of the clamp pulse and the predetermined reference voltage is larger than the predetermined limit voltage, it is output from the D / A converter. And a second subtracting circuit that accelerates charging / discharging of the capacitor with a larger current than the first subtracting circuit in accordance with a difference between the analog data and a predetermined reference voltage.

  According to this configuration, when the DC voltage (black level) of the video signal changes small with respect to a predetermined level, the first subtractor circuit gradually charges and discharges the capacitor with a relatively small current to cause the black voltage. The level can be stabilized by feedback, and when the black level changes greatly with respect to a predetermined level, a large current corresponding to the amount of black level change can be obtained by the second subtraction circuit in addition to the first subtraction circuit. The black level can be quickly returned to a predetermined level by immediately charging and discharging the capacitor in the amount.

  In the signal direct current stabilization circuit of the present invention described above, it is preferable that the second subtracting circuit is composed of an insensitive mechanism built-in operational amplifier circuit that does not charge / discharge the output when the difference voltage between the two inputs is equal to or lower than a predetermined voltage. .

  According to this configuration, when the difference between the analog data and the predetermined reference voltage is smaller than the predetermined limit voltage, the capacitor is not charged / discharged at all, and only when the difference is larger than the limit voltage, the analog data and the predetermined reference voltage are The configuration for accelerating the charging / discharging of the capacitor according to the difference is simplified.

  The video equipment of the present invention has a configuration including the signal DC voltage stabilization circuit of the present invention, and has the same effects as the signal DC voltage stabilization circuit of the present invention.

  According to the signal DC voltage stabilizing circuit of the present invention, in the steady state where the black level of the video signal is in the vicinity of the predetermined level, the signal is always converged to the predetermined level by gradual feedback, and the influence of fluctuation factors such as noise. Therefore, the black level of the output digital signal is stable, and there is an effect that a high-quality image with small noise derived from the clamp mechanism can be obtained.

  On the other hand, even when the black level of the video signal greatly fluctuates from a predetermined level, such as when the power is turned on, when the amplitude of the video signal, that is, when the brightness of the gain variable amplifier changes greatly, Since the black level of the video signal is converged to a predetermined level in a short time, there is an effect that a high-quality video without image disturbance can be obtained.

  Furthermore, the second subtracting circuit constituting the signal DC voltage stabilizing circuit of the present invention uses a configuration of an insensitive mechanism built-in operational amplifier circuit, which facilitates mounting on a semiconductor integrated circuit and is suitable for industrial mass production. This has the effect of realizing a signal DC voltage stabilizing circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a first embodiment of a signal DC voltage stabilization circuit according to the present invention. In FIG. 1, 1A is an amplifier, 2 is a DC control circuit, 2a is a control terminal of the DC control circuit 2, 3 is an A / D converter, 4 is a data extraction circuit, 5 is a D / A converter, 6 is a reference voltage source, Reference numeral 7 denotes a first subtraction circuit, 8 denotes a capacitor, and 9 denotes a second subtraction circuit including, for example, an insensitive mechanism built-in operational amplifier circuit.

  FIG. 3 is a timing chart showing the operation of the signal DC voltage stabilizing circuit, showing the timing of the input analog video signal, clamp pulse and clock.

  As shown in FIG. 3, the input analog video signal has a valid period in which a video signal exists and a horizontal blanking period in which no video signal exists in one horizontal period. In this horizontal blanking period, there is a black reference period that serves as a black reference. Further, as shown in FIG. 3, the clamp pulse described later has an active period in the black reference period of the input analog signal.

  As shown in FIG. 1, this input analog video signal is amplified by a fixed gain or variable gain amplifier 1A to optimize the amplitude, and further, the DC voltage of the output analog video signal of the amplifier 1A according to the control terminal voltage applied to the control terminal 2a. The DC voltage is optimized by the DC control circuit 2 that regulates (clamps). The input analog video signal is converted into an N-bit digital signal by the N-bit A / D converter 3 at a conversion speed according to the input clock, and output in synchronization with the clock. The relationship between this clock and the input analog video signal is as shown in FIG.

  In detecting the signal level of the black reference period of the N-bit digital signal, generally, the level cannot exceed 1/4 to 1/2 of the full scale in the steady state of the operation. The number of processing and output bits is set to M bits that are the same as or smaller than N bits. That is, from the N-bit digital signal output from the A / D converter 3, the data extraction circuit 4 uses the active period of the clamp pulse in which the active period exists in the black reference period in the horizontal blanking period of the input analog video signal. The black level (DC voltage) is extracted by averaging and is output as M-bit digital data having a clamp pulse period, and is further converted to analog data by the M-bit D / A converter 5 to be output to the first subtractor circuit 7. And the second subtraction circuit 9.

  The first subtraction circuit 7 calculates the difference between the output analog data of the M-bit D / A converter 5 and the voltage of the reference voltage source 6 during the active period of the clamp pulse, and charges and discharges the capacitor 8 according to the difference. The control terminal voltage applied to the control terminal 2a of the DC control circuit 2 is generated. That is, when the analog data output from the M-bit D / A converter 5 is smaller than the voltage of the reference voltage source 6, the capacitor 8 is charged and the control terminal voltage applied to the control terminal 2a of the DC control circuit 2 is increased. The DC voltage of the analog video signal input to the A / D converter 3 is increased. Conversely, when the analog data output from the M-bit D / A converter 5 is larger than the voltage of the reference voltage source 6, the capacitor 8 is discharged and the control terminal voltage applied to the control terminal 2a of the DC control circuit 2 is lowered. Thus, the DC voltage of the analog video signal input to the A / D converter 3 is lowered.

  The first subtraction circuit 7 slowly charges and discharges the capacitor 8 with a relatively small current, and functions to stably maintain the black level of the output digital video signal of the A / D converter 3 at a predetermined level. Yes.

  The second subtraction circuit 9 calculates a difference between the output analog data of the M-bit D / A converter 5 and the voltage of the reference voltage source 6 during the active period of the clamp pulse, and the difference is larger than a predetermined limit voltage. However, according to the difference, the charging / discharging of the capacitor 8 is accelerated with a current larger than that of the first subtraction circuit 7, and the control terminal voltage applied to the control terminal 2a of the DC control 2 is rapidly restored. That is, when the analog data output from the M-bit D / A converter 5 is smaller than the voltage of the reference voltage source 6 exceeding the limit voltage, the capacitor 8 is rapidly charged and given to the control terminal 2a of the DC control circuit 2. The control terminal voltage is raised and the DC voltage of the analog video signal input to the A / D converter 3 is rapidly raised. On the contrary, when the analog data output from the M-bit D / A converter 5 is larger than the voltage of the reference voltage source 6 exceeding the limit voltage, the capacitor 8 is rapidly discharged to control the control terminal 2a of the DC control circuit 2. The DC voltage of the analog video signal input to the A / D converter 3 is rapidly lowered by lowering the control terminal voltage applied to the A / D converter 3.

  According to the above-described embodiment, even if the black level of the output digital video signal of the A / D converter 3 fluctuates greatly, it can be converged to a predetermined level in a short time. Further, since the instantaneous noise is averaged within the clamp pulse active period in the data extraction circuit 4 and the output data does not change significantly, the second subtraction circuit 9 does not operate, and charging / discharging does not malfunction. .

  According to the above-described embodiment, the input difference voltage in the first subtraction circuit 7 and the second subtraction circuit 9, that is, the difference voltage between the output analog data of the M-bit D / A converter 5 and the voltage of the reference voltage source 6, and the capacitor The relationship with the charge / discharge current to 8 is as shown in the characteristic diagram of FIG. As shown in the characteristic of FIG. 4, since there is no sudden discontinuous change in the charge / discharge current before and after the limit voltage, the subtraction result between the output analog data of the M-bit D / A converter 5 and the voltage of the reference voltage source 6 The charging / discharging current increases when the voltage slightly exceeds a predetermined limit voltage, which is an amount corresponding to the voltage exceeding the large limit. As a result, the DC voltage of the analog video signal input to the A / D converter 3 increases and decreases due to rapid charging / discharging of the capacitor 8, and the black level of the output digital video signal of the A / D converter 3 increases and decreases. It will never be too high or too low beyond a predetermined level, and there will be no video disturbance due to that.

  A configuration example of an insensitive mechanism built-in operational amplifier circuit used as the second subtraction circuit 9 is as shown in FIG. In FIG. 2, 23, 24, 26, 27, 28, 29, 30, 31, 32, 35, 36 are n-channel transistors, 21, 22, 25, 33, 34 are p-channel transistors, 37, 38, 40 are Constant current source 39 is a constant current source which is turned on only during the clamp pulse active period, 41 is a first input terminal connected from the reference voltage source 6 in FIG. 1, and 42 is connected from the M-bit D / A converter 5 in FIG. The second input terminal 43 is an output connected to the capacitor 8 in FIG.

  The n-channel transistors 26 and 27 are composed of transistors having the same characteristics, and the difference voltage between the gate and the source is Vgs1. The n-channel transistors 23 and 24 are composed of transistors having the same characteristics, and the difference voltage between the gate and the source is Vgs2, and Vgs2> Vgs1.

In FIG. 2, the voltage at the second input terminal 42 is | input 2 −input 1 | <(Vgs 2 −Vgs 1).
That is, when the subtraction result obtained by subtracting the voltage of the reference voltage source 6 from the analog data output from the M-bit D / A converter 5 is smaller than the limit voltage defined by (Vgs2-Vgs1), Vgs2> Vgs1. Therefore, the gate voltage of the p-channel transistor 25 is lower than the gate voltage of the p-channel transistors 21 and 22. Therefore, most of the current of the constant current source 39 that flows during the clamp pulse active period flows to the p-channel transistor 25. As a result, the gate voltages of the n-channel transistors 35 and 36 are increased and turned on, the current that slightly flows through the p-channel transistors 21 and 22 also flows into the n-channel transistors 35 and 36, and no current flows through the n-channel transistors 28 and 29. Not flowing. Therefore, no current flows through the n-channel transistors 31 and 32 and the p-channel transistors 33 and 34. Therefore, no current is input / output at the output 43, and the capacitor 8 is not charged or discharged as a subtraction circuit.

  On the other hand, when the voltage of the second input terminal 42 is | input2-input1 |> (Vgs2-Vgs1), that is, the voltage of the reference voltage source 6 is subtracted from the analog data output from the M-bit D / A converter 5. When the subtraction result is larger than the limit voltage defined by (Vgs2-Vgs1), the gate voltage of the p-channel transistor 21 or 22 is lower than the gate voltage of the p-channel transistor 25. The current of the constant current source 39 that is turned off and flows during the clamp pulse active period is the reference voltage from the difference voltage between the first input terminal 41 and the second input terminal 42, that is, the analog data output from the M-bit D / A converter 5. In accordance with the subtraction result obtained by reducing the voltage of the source 6, the p-channel transistor 21 and the p-channel transistor A current such that the source voltage of the transistor 22 becomes equal to the voltage Vgs flows through each of the p-channel transistors 21 and 22, and a current proportional to the difference current is input and output from the output 43 to charge the capacitor 8 as a subtraction circuit. Operates to discharge.

  According to the above-described embodiment, when the black level of the output digital video signal of the A / D converter 3 fluctuates greatly, the difference between the analog data output from the M-bit D / A converter 5 and the voltage of the reference voltage source 6 is When the voltage exceeds the limit voltage defined by (Vgs2-Vgs1), a current proportional to the difference current is input / output from the output 43 and the capacitor 8 is charged / discharged in a short time, so that the black level changes greatly. The disturbance of the image derived from this does not continue for a certain period.

  Furthermore, the present invention is intended to cover all alternatives, modifications, applications and variations that fall within the scope of the appended claims.

  The signal DC voltage stabilization circuit according to the present invention can obtain a high-quality image with low noise derived from the clamping mechanism in a steady state where the black level of the video signal exists in the vicinity of a predetermined level, Even when the black level greatly fluctuates from a predetermined level, there is an effect that a high-quality video without image disturbance can be obtained, which is useful for realizing a high-quality video device or the like.

1 is a circuit diagram showing a configuration of a signal DC voltage stabilization circuit according to a first embodiment of the present invention; It is a circuit diagram which shows the structural example of the insensitive mechanism built-in operational amplifier circuit in Embodiment 1 of this invention. It is a timing diagram which shows operation | movement of Embodiment 1 of this invention. It is a characteristic view which shows the relationship between the input differential voltage of the subtraction circuit in Embodiment 1 of this invention, and the charging / discharging electric current to a capacitor | condenser. It is a characteristic view which shows the relationship between the input differential voltage of the subtraction circuit in a prior art example, and the charging / discharging electric current to a capacitor | condenser. It is a characteristic view which shows the relationship between the input differential voltage of the subtraction circuit in another prior art example, and the charging / discharging current to a capacitor | condenser. It is a circuit diagram which shows the structure of the signal direct-current voltage stabilization circuit of a prior art example. It is a circuit diagram which shows the structure of the clamp apparatus of another prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Variable gain amplifier 1A Amplifier 2 DC control circuit 3 N bit A / D converter 4 Data extraction circuit 5 M bit D / A converter 6 Reference voltage source which generates a reference voltage 7 First subtraction circuit 8 Capacitor 9 Second subtraction Circuits 23, 24, 26 to 28, 29 to 32, 35, 36 n-channel transistors 21, 22, 25, 33, 34 p-channel transistors 37, 38, 40 constant current source 39 constant current source which is turned on only during the clamp pulse active period 41 First input terminal 42 Second input terminal 43 Output terminal

Claims (3)

An amplifier for amplifying the input analog video signal;
A DC control circuit that regulates the DC voltage of the output analog video signal of the amplifier according to the control terminal voltage applied to the control terminal;
An A / D converter for converting an analog video signal output from the DC control circuit at a predetermined conversion cycle into an N-bit digital signal (N is a positive integer), and
An N-bit digital signal output from the A / D converter is extracted in an active period of a clamp pulse having an active period in a black reference period in a horizontal blanking period of the input analog video signal, and has a period of the clamp pulse. A data extraction circuit that outputs M-bit digital data of N bits or less;
A D / A converter for converting M-bit digital data of N bits or less output from the data extraction circuit into analog data;
A first subtraction circuit that generates a control terminal voltage of the DC control circuit by charging and discharging a capacitor according to a difference between analog data output from the D / A converter and a predetermined reference voltage during an active period of the clamp pulse. When,
Only when the difference between the analog data output from the D / A converter and a predetermined reference voltage is larger than a predetermined limit voltage during the active period of the clamp pulse, the analog data output from the D / A converter and a predetermined A signal DC voltage stabilization circuit comprising: a second subtraction circuit that accelerates charging and discharging of the capacitor with a larger current than the first subtraction circuit according to a difference from a reference voltage.   2. The signal DC voltage stabilizing circuit according to claim 1, wherein the second subtracting circuit includes an insensitive mechanism built-in operational amplifying circuit that does not charge / discharge the capacitor when a difference voltage between two inputs is equal to or lower than a predetermined voltage.   A video equipment comprising the signal DC voltage stabilization circuit according to claim 1.

Images