JPH0329470A - Picture signal reception circuit - Google Patents

Abstract

PURPOSE:To obtain a stable operation under automatic gain control by detecting a synchronizing pulse level from a signal before synchronization clamp, applying automatic gain control based on the synchronizing pulse level and applying synchronization clamp in the timing obtained from the synchronizing signal. CONSTITUTION:The circuit is provided with synchronizing pulse level detection circuit 3, 4 detecting a synchronizing pulse level from an output of a gain control amplifier 1 to generate a control signal corresponding to the synchronizing pulse level and inputting the control signal to a gain control terminal of the gain control amplifier 1 and a clamp pulse generating circuit 8 detecting the synchronizing signal from the output of the gain control amplifier 1 to generate a synchronization clamp timing pulse and inputting the pulse to the synchronization clamp circuit 2. Then feedback control utilizing the synchronization pulse level is applied to the gain control amplifier 1 and feedforward control is acted on the synchronization clamp circuit. Thus, the automatic gain control is realized, in which the pedestal level of a reception signal is stable.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image signal receiving circuit. More specifically,
The present invention relates to a novel structure of an image signal receiving circuit that receives a composite signal in which an analog image signal such as a video signal and a synchronization signal are superimposed.

2. Description of the Related Art In analog video signal transmission using an optical fiber or the like as a transmission medium, the amount of attenuation of an image signal upon reception changes significantly. Therefore, in an image signal receiving circuit that receives such an analog image signal, a gain control amplifier is used to stably reproduce the received signal.

FIG. 3(a) is a block diagram showing a typical structure of this type of image signal receiving circuit.

As shown in the figure, this circuit includes a gain control amplifier 31 that amplifies an input signal under a gain control signal, which will be described later, and a peak value clamp circuit 39 connected to the output of this gain control amplifier 31. , and is configured to output an image signal via an output basso circuit 38.

Here, in order to perform automatic gain control, this circuit receives the synchronization signal separation circuit 35 and the synchronization pulse level detection circuit 34 connected to the output of the peak value clamp circuit 39, and the output of the synchronization signal separation circuit. a synchronous pulse level detection pulse generation circuit 33 that outputs synchronization timing to the synchronous pulse level detection circuit 34; and a DC amplifier that amplifies the output of the synchronous pulse level detection circuit 34 and inputs it as a gain control signal to the gain control amplifier 31. 37.

FIG. 3(b) is a waveform diagram for explaining the operation of the circuit as described above.

That is, in the circuit shown in FIG. 3(a), a synchronization signal is separated from the output of the peak value clamp circuit 39 by the synchronization signal separation circuit 35, and from this synchronization signal, the synchronization pulse level detection pulse generation circuit 33 A synchronization pulse level detection pulse is generated to instruct the operation timing of the synchronization pulse level detection circuit 34. Synchronous pulse level detection 1i [1r34
The synchronous pulse level detection pulse detects the synchronous pulse level from the output of the peak value clamp circuit 39, and this level is fed back to the gain control amplifier 31 as a gain control signal via the DC amplifier 37, thereby detecting the image. It realizes automatic gain control during signal reception.

However, in the conventional image signal receiving circuit as described above, the output of the peak value clamp circuit is used for automatic gain control, so the level of the detected synchronization pulse is equal to the level of the synchronization pulse at the output of the gain control amplifier. is not expressed proportionally. Therefore, the pedestal level, which is the reference for the video signal, is likely to fluctuate, resulting in unstable image signal reception.

Therefore, a circuit has been proposed in which the peak value clamp circuit is changed to a synchronous clamp circuit, and a pedestal clamp is performed using a clamp pulse. FIG. 4(a) is a block diagram showing a typical configuration of an image signal receiving circuit configured in this manner.

As shown in the figure, this circuit is configured such that an input signal is received by a synchronous clamp circuit 42 via a gain control amplifier 41, and its output is output via an output buffer circuit 48. Further, the output of the synchronous signal separation circuit 45 is input to the clamp pulse generation circuit, and the synchronous clamp circuit 42 is controlled by this output. Also in this circuit, the output of the synchronous pulse level detection circuit 44 is fed back as a control signal to the gain control amplifier 41 via the DC amplifier 47 to realize automatic gain control, as shown in FIG. 3(a). ) is similar to the circuit shown in ).

FIG. 4(b) is a waveform diagram for explaining the operation of the circuit as described above.

In this circuit, a clamp pulse generation circuit 46 generates a clamp pulse from a synchronization signal outputted from a synchronization signal separation circuit 45, and the synchronization clamp circuit 42 is operated by this pulse. Therefore, the synchronization pulse level detection circuit 44 detects the synchronization pulse level from the signal after synchronization clamping. That is, as shown in FIG. 4, when an image signal is received by this circuit, the synchronous clamp level becomes the vedestal level.

However, although the pedestal level is stable in the image signal receiving circuit configured in this way, since the information after the synchronous clamp is used for generating the synchronous clamp pulse and for automatic gain control, the operation is unstable and oscillations may occur. The disadvantage is that it tends to cause

Problems to be Solved by the Invention As described above, conventional image signal receiving circuits have low stability in image signal reception due to automatic gain control, and cannot operate stably in applications where the amount of attenuation changes significantly as described above. The realization of an image signal receiving circuit that does this is an important issue.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above and to provide a novel image signal receiving circuit that operates stably under automatic gain control.

Means for Solving the Problems According to the present invention, there is provided a gain control amplifier equipped with a gain control terminal that receives and amplifies a composite signal obtained by superimposing an analog image signal and a synchronization signal. In an image signal receiving circuit comprising a synchronous clamp circuit that clamps the signal level of an image signal output from the gain control amplifier and outputs an analog image signal at a timing instructed by a trigger signal, the output of the gain control amplifier is synchronized. a synchronous pulse level detection circuit that detects a pulse level, generates a control signal corresponding to the synchronous pulse level and inputs it to a gain control terminal of the gain control amplifier; and detects the synchronous signal from the output of the gain control amplifier. An image signal receiving circuit is provided, comprising a clamp pulse generation circuit that generates a synchronous clamp timing pulse and inputs the generated synchronous clamp timing pulse to the synchronous clamp circuit.

The image signal receiving circuit according to the present invention detects the synchronization pulse level from the signal before the synchronization clamp, performs automatic gain control based on this synchronization pulse level, and performs the synchronization clamp at the timing obtained from the synchronization signal. Its main feature is that it is structured like this.

In other words, the conventional image signal receiving circuit shown in FIG. 3(a) performs gain control by clamping the peak value of the synchronization signal, so it does not operate so that the pedestal level is always constant. do not have.

Furthermore, in the second conventional example shown in FIG. 4(a), the information after synchronous clamping is processed into two types of control, such as extracting the clamp pulse from the output of the clamp circuit and extracting the automatic gain control signal. It is difficult to stabilize the operation because it is used against

Therefore, in the image signal receiving circuit according to the present invention, as will be specifically described later, feedback control using a synchronous pulse level is adopted for the gain control amplifier, and feedforward control is adopted for the synchronous clamp circuit. By doing this, automatic gain control with a stable bed scale level of the received signal is realized.

Hereinafter, the present invention will be described in more detail with reference to the drawings, but the following disclosure is only one embodiment of the present invention, and does not limit the technical scope of the present invention in any way.

Embodiment 1 FIG. 1(a) is a block diagram showing an example of the structure of an image receiving circuit according to the present invention.

As shown in the figure, in this image signal receiving circuit,
It is configured to output a received image signal via a gain control amplifier 1, a synchronous clamp circuit 2, and an output buffer circuit 8. Here, the gain control amplifier l is provided with a gain control terminal.

Furthermore, the synchronous clamp circuit 2 clamps the input signal level at the timing specified by the clamp trigger pulse input to the trigger input.

Furthermore, this circuit includes a pair of first and second synchronous pulse level detection circuits 3 connected to the output of the gain control amplifier l.
and 4, a synchronization signal separation circuit 5 connected to the l-th synchronization pulse level detection circuit, and a clamp pulse generation circuit 6 that generates a clamp pulse from the output of the synchronization signal separation circuit 5.
and a DC amplifier 7 connected to the first and second synchronous pulse level detection circuits 3 and 4. Here, the output of the clamp pulse generation circuit 6 is connected to the trigger input of the aforementioned synchronous clamp circuit 2 and the second synchronous pulse level detection circuit 4.
is entered. Further, the output of the DC amplifier 7 is fed back to the gain control terminal of the gain control amplifier 1 described above.

FIG. 1(b) is a signal waveform diagram for explaining the operation of the image signal receiving circuit shown in FIG. 1(a).

That is, the image signal input to the image receiving circuit shown in FIG. 1(a) is amplified by the gain control amplifier 1 and then input to the synchronous clamp circuit 2. Here, the output of the gain control amplifier 1 is also input to synchronous pulse level detection circuits 3 and 4.

The synchronization pulse level detection circuit 3 extracts the signal level on the high level side of the synchronization signal from the input image signal. The extracted high level side synchronous pulse level is transferred to the DC amplifier 7.
The synchronization signal separation circuit 5 extracts a synchronization signal by using this high-level synchronization pulse level.

Subsequently, the clamp pulse generation circuit 6 extracts a timing pulse for the clamp operation of the synchronous clamp circuit 2 from the synchronous signal extracted by the synchronous signal separation circuit 5.

The timing pulse output from the clamp pulse generation circuit 6 is input to the trigger input of the synchronous clamp circuit 2, and is also input to the synchronous pulse level detection circuit. 4 is also input. The synchronization pulse level detection circuit 4 extracts a signal level on the low level side of the synchronization pulse level from the image signal at the timing instructed by this timing pulse. The extracted low-level synchronization pulse level is input to the negative phase input of the DC amplifier 7.

The DC amplifier 7 calculates the synchronization pulse level from the high level side and low level side signal levels of the input synchronization pulse
That is, a gain control signal corresponding to the peak value of the synchronization pulse is generated, and this signal is input to the gain control terminal of the gain control amplifier l. Automatic gain control based on the synchronization pulse level is performed as described above.

In this way, the image signal receiving circuit according to the present embodiment performs automatic gain control based on the synchronization pulse level in the amplified image signal output from the gain control amplifier, so that the bed scale of the image signal is reduced. The level is stable. In addition, separation of synchronization signals and generation of clamp timing are
Since the output signal of the gain control amplifier 1 is used before synchronous clamping, the operation of the circuit itself is stable.

FIG. 2 shows a specific example of the structure of the image signal receiving circuit shown in FIG. 1(a).

As shown in the figure, in this image signal receiving circuit,
The input received image signal is outputted via the gain control amplifier 21, the synchronous clamp circuit 22, and the output buffer circuit 28. The gain control amplifier 21 is constituted by an amplifier equipped with a gain control terminal, and the synchronous clamp circuit 22 performs synchronous clamping in response to input of a trigger pulse, which will be described later.

Other elements constituting this circuit correspond to the block diagram shown in FIG. 1(a) as follows. That is, the peak hold circuit 23, as the synchronization pulse level detection circuit 3, extracts the peak on the high level side of the synchronization signal from the received signal. Further, the comparator 25 compares the received signal with a certain threshold level based on the output of the peak hold circuit 23, and
The synchronizing signal separation circuit 5 operates by generating pulses corresponding to the period exceeding the dark value level. The differentiator 26, which receives the output pulse of the comparator 25, functions as the crank pulse generating circuit 6 by generating one shot pulse at the falling edge of the pulse. The output of this circuit is the synchronous clamp circuit 22
This serves as a trigger for the clamp operation for the signal and a gate pulse for the analog gate 24a, which will be described later.

Since the analog gate 24a performs a gate operation in response to the clamp pulse, the peak hold 24b connected thereto holds the peak value during the period when the gate is open, that is,
The signal level on the low level side of the synchronization pulse is detected. Here, since the clamp pulse is used as the gate pulse as described above, the peak hold 24b
will extract the clamp level of the synchronization signal.

That is, in this circuit, the synchronous pulse level detection circuit 4 is controlled by the analog gate 24a and the peak hold 24b.
It is considered.

The high-level peak level and clamp level of the synchronization signal extracted as described above are input to the operational amplifier 27 as the feedback DC amplifier 7, and the operational amplifier 27
By inputting the output of the gain control amplifier 21 to the control input of the gain control amplifier 21, automatic gain control as described above is realized.

Effects of the Invention As detailed above, the image signal receiving circuit according to the present invention has the following effects:
Although it has a simple structure, it is a stable circuit with little fluctuation in the pedestal level.

Therefore, it is possible to receive a good analog video signal over a wide dynamic range, and it can be advantageously used in optical analog video links, etc., where level fluctuations are significant. Furthermore, since it has a simple structure, it can be made smaller and lower in price, which is also preferable.

[Brief explanation of drawings]

FIG. 1(a) is a block diagram showing the basic configuration of the image signal receiving circuit according to the present invention, and FIG. 1(b) is a block diagram showing the basic configuration of the image signal receiving circuit according to the present invention. FIG. 2 is a diagram showing a specific example of the structure of the circuit shown in FIG. 1(a), and FIG. 3(a) is a waveform diagram for explaining the operation of the conventional circuit. 3(b) is a waveform diagram for explaining the operation of the image signal receiving circuit shown in FIG. 3(a); FIG. FIG. 4(a) is a block diagram showing another example of the configuration of a conventional image signal receiving circuit, and FIG. 4(b) explains the operation of the image signal receiving circuit shown in FIG. 4(a). FIG. [Main reference numbers] 1, 21, 31, 41...Gain control amplifier, 2, 2
2, 42...Synchronous clamp circuit, 3, 4, 34, 4
4...Synchronized Hals level detection circuit, 5, 35, 45...
... Synchronization signal separation circuit, 6, 46 ... Clamp pulse generation circuit, 7, 37, 47 ... DC amplifier, 8, 28, 38, 48 ... Output buffer circuit 23, 24
b...Peak hold circuit, 24a...
・Analog gate circuit, 25... Comparator, 26...
・Differentiator, 27... operational amplifier, 39... peak value clamp circuit

Claims (2)

[Claims] (1) A gain control amplifier equipped with a gain control terminal that receives an input signal and amplifies a composite signal obtained by superimposing an analog image signal and a synchronization signal, and the gain control amplifier is operated at a timing specified by an input trigger signal. and a synchronous clamp circuit that clamps the signal level of an image signal outputted by a synchronous clamp circuit to output an analog image signal, detects a synchronous pulse level from the output of the gain control amplifier, and detects a synchronous pulse level from the output of the gain control amplifier, a synchronous pulse level detection circuit that generates a corresponding control signal and inputs it to the gain control terminal of the gain control amplifier; and a synchronous pulse level detection circuit that detects the synchronous signal from the output of the gain control amplifier and generates a synchronous clamp timing pulse. An image signal receiving circuit comprising: a clamp pulse generating circuit input to a synchronous clamp circuit. (2) In the image signal receiving circuit according to claim 1, the synchronization pulse level detection circuit detects a peak value of the output signal of the gain control amplifier to detect a peak on the high level side of the synchronization signal. a first synchronization pulse level detection circuit; a second synchronization pulse level detection circuit that detects a low level side level of the synchronization signal at a timing indicated by a pulse generated by the clamp pulse generation circuit; an operational amplifier connected to the outputs of the first and second synchronous pulse level detection circuits, and whose output is connected to the control terminal of the gain control amplifier.