JP2830599B2 - Pedestal clamp device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pedestal clamp device, and more particularly to a pedestal clamp device for generating a digital video signal by setting a pedestal level indicating a DC potential of an input video signal to a predetermined level.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional pedestal clamping device.

[0003] The pulse generation circuit 12 includes a synchronization separation circuit 11.
Then, based on the synchronization signal separated from the input video signal S1, a clamp pulse P1 corresponding to the timing position where the pedestal level is set is generated.

The A / D conversion circuit 15 includes a differential amplifier 13
Is converted into a digital video signal S2.

[0005] A latch circuit 42 latches the luminance signal separated from the digital video signal S2 by the luminance separation circuit 41 using a clamp pulse P1, and extracts a digital pedestal level signal P2 indicating a pedestal level.

The arithmetic circuit 43 receives the digital pedestal level signal P2 and a signal Ps indicating the reference pedestal level supplied from the outside, and calculates a difference between the level values of the two signals to generate a signal L1 indicating the level difference. The signal L1 indicating the level difference is converted into an analog signal L2 indicating the level difference by the DA converter 17 and fed back to the differential amplifier circuit 13. It is also supplied to the arithmetic circuit 18.

[0007] The differential amplifier circuit 13 controls the DC potential of the input video signal S1 according to the analog signal L2 indicating the level difference, and controls the pedestal level to a predetermined level.

The arithmetic circuit 18 generates a digital video signal S
The signal L1 indicating the level difference is subtracted from 2 and sent out as an output digital video signal S3. Thus, conventionally,
The input video signal is digitized to detect the difference between the pedestal level and the reference level, and the level difference is DA-converted and fed back to correct the level of the input video signal. The error can be suppressed to the minimum quantization level in the long term without being affected by the drift of the conversion circuit. Further, even if the DC potential of the input video signal changes sharply, a clamping error is instantaneously eliminated by the feedforward effect of the arithmetic circuit 18.

[0009]

The above-described conventional pedestal clamp device does not operate effectively for a level difference smaller than the minimum quantization level. That is, generally, the A / D conversion circuit of a video signal has an 8-bit configuration and the minimum quantization step is about 4 mV, so that it does not operate effectively for a level difference of 4 mV or less. However, since the detection limit of periodic noise is about 1 mV, when periodic noise larger than the detection limit and smaller than the minimum quantization level is mixed, it cannot be suppressed below the detection limit. is there.

It is an object of the present invention to provide a pedestal clamp device which operates even with a level difference equal to or less than the minimum quantization level, and which can suppress mixed periodic noise below the detection limit.

[0011]

A pedestal clamp device according to the present invention is a pedestal clamp device for generating a digital video signal by setting a pedestal level of an input video signal to a predetermined level. Means for generating a clamp pulse indicating a set timing position, amplifying means for increasing the degree of amplification when receiving the clamp pulse, and a digital video signal which is obtained by digitizing a video signal outputted by the amplifying means. A / D conversion means for transmitting as
Means for calculating a level difference between the digital video signal and a signal indicating a reference pedestal level supplied from the outside when receiving the clamp pulse to generate a level difference signal; and converting the level difference signal into an analog signal. It comprises means for sending out as a level difference analog signal, and control means for controlling the DC potential of the input video signal according to the level difference analog signal and sending it to the amplifying means. Further, the level difference signal generating means may be provided with means for removing a high-frequency noise component included in the level difference signal on the output side. A first delay means for delaying the digital video signal by one line and sending it as a delayed digital video signal; a second delay means for delaying the level difference signal by one line and sending it as a delayed level difference signal; Means for receiving the level difference signal and the delayed level difference signal to generate an inter-line error signal for interpolating a level error between lines; and means for subtracting and outputting the inter-line error signal from the delayed digital video signal. You may comprise and comprise.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which the same components as those of the conventional example shown in FIG.

Sync separation circuit 11 and pulse generation circuit 1
2 separates the synchronization signal from the input video signal S11 and generates a clamp pulse P1 corresponding to the timing position where the pedestal level is set.

The selection amplifier circuit 14 outputs the clamp pulse P1
This is an amplification circuit for increasing the degree of amplification when receiving the signal and improving the quantization accuracy of the pedestal portion. The A / D conversion circuit 15 converts the video signal output from the selection amplification circuit 14 into a digital video signal S12.

The arithmetic circuit 16 calculates a level difference between the digital video signal S12 and a signal Ps indicating a reference pedestal level supplied from the outside during a period of receiving the clamp pulse P1, thereby generating a level difference signal L11. I do.
The level difference signal L11 is converted into an analog signal L12 indicating a level difference by the DA converter 17 and fed back to the differential amplifier circuit 13. It is also supplied to the arithmetic circuit 18.

The differential amplifier circuit 13 controls the DC potential of the input video signal S11 according to the analog signal L12 indicating the level difference, and controls the pedestal level to a predetermined level.

The arithmetic circuit 18 generates a digital video signal S
By subtracting the level difference signal L11 from 12, the output digital video signal S13 is transmitted immediately while the pedestal potential is held even when the feedback loop is not established. By doing so, for example, if the amplification degree when the selective amplification circuit 14 amplifies the pedestal portion is increased by 16 times, even if the A / D conversion circuit has an 8-bit configuration and the minimum quantization level is about 4 mV, , The quantization accuracy in the pedestal portion is improved to 12 bits, the minimum quantization level is about 1/4 mV, and the periodic noise detection limit can be 1 mV or less.

FIG. 2 is a block diagram showing a second embodiment of the present invention, wherein the same components as those of the first embodiment shown in FIG. The difference from the first embodiment is that an arithmetic circuit 19 and an integrating circuit 20 are provided.

Here, the arithmetic circuit 19 calculates a level difference between the digital video signal S12 and a signal Ps indicating a reference pedestal level supplied from the outside, and generates a level difference signal L21. The integrating circuit 20 receives the level difference signal L21 output from the arithmetic circuit 19 and receives the clamp pulse P
The level difference signal L22 is generated for each period during which the signal 1 is received, that is, for each line of the video signal to remove high-frequency noise components. This level difference signal L22 is DA
The signal is sent to the differential amplifier circuit 13 via the conversion circuit 17 and also sent to the arithmetic circuit 18.

By doing so, random noise and impulse noise included in the level difference signal for controlling the DC potential of the input video signal by feeding back to the differential amplifier circuit can be removed, so that noise-resistant control is possible. Becomes

FIG. 3 is a block diagram showing a third embodiment of the present invention, wherein the same components as those of the second embodiment shown in FIG. The difference from the second embodiment is that line memory circuits 21 and 22 and a ramp waveform generating circuit 23 are provided.

Here, the line memory circuit 21 delays the digital video signal S12 by one line and sends it to the arithmetic circuit 18 as a digital video signal S14.
Further, the line memory circuit 22 delays the level difference signal L22 output from the integration circuit 20 by one line and sends it to the ramp waveform generation circuit 23 as a level difference signal L23.

The ramp waveform generating circuit 23 generates a sawtooth line-to-line error signal L24 for interpolating the level error between lines from the level difference signals L22 and L23, and sends it to the arithmetic circuit 18.

By doing so, the arithmetic circuit 18
Is an inter-line error signal L2 for interpolating a level error between lines from the digital video signal S14 delayed by one line.
By subtracting 4, it is possible to remove not only the feedforward effect but also the differential residual error generated between lines.

[0026]

As described above, according to the first aspect of the present invention, the selective amplification circuit for selectively amplifying only the pedestal portion of the video signal is provided on the input side of the A / D conversion circuit. Can be improved even if the level difference is smaller than the minimum quantization level, and the periodic noise can be suppressed below the detection limit.

According to the second aspect of the present invention, by providing an integrating circuit to remove random noise and impulse noise contained in the level difference signal, it is possible to perform control with noise tolerance.

According to the third aspect of the present invention, a line memory circuit for delaying a digital video signal by one line and a line memory circuit for delaying a level difference signal by one line are provided. A ramp waveform generating circuit for generating an inter-line error signal for interpolating a level error between lines from the level difference signal delayed by only In addition to the effect, the differential residual error generated between lines can be removed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional pedestal clamp device.

[Description of Signs] 11 Synchronous separation circuit 12 Pulse generation circuit 13 Differential amplification circuit 14 Selective amplification circuit 15 A / D conversion circuit 16, 18, 19 Operation circuit 17 D / A conversion circuit 20 Integrator circuit 21, 22 Line memory circuit 23 Ramp waveform generation circuit S11 Input video signal S12 to S14 Digital video signal P1 Clamp pulse Ps Signal indicating reference pedestal level L11, L21 to L23 Level difference signal L12 Analog signal indicating level difference L24 Line-to-line error signal

Continuation of the front page (56) References JP-A-60-212063 (JP, A) JP-A-3-14368 (JP, A) JP-A-3-131177 (JP, A) JP-A-4-74068 (JP) JP-A-3-175878 (JP, A) JP-A-63-90276 (JP, A) JP-A-59-149468 (JP, A) JP-A-3-108875 (JP, A) (58) Surveyed fields (Int.Cl. ⁶ , DB name) H04N 5/14-5/217

Claims (3)

(57) [Claims] 1. A pedestal clamp device for generating a digital video signal by setting a pedestal level of an input video signal to a predetermined level, wherein the pedestal clamp device outputs a clamp pulse indicating a timing position at which the pedestal level of the input video signal is set. Means for generating, and amplifying means for increasing the degree of amplification when receiving the clamp pulse,
A / D conversion means for digitizing the video signal output from the amplification means and sending it out as a digital video signal; and a signal indicating the digital video signal and an externally supplied reference pedestal level when receiving the clamp pulse. Means for calculating a level difference between the level difference signal and the analog signal, means for converting the level difference signal into an analog signal and transmitting the analog signal as a level difference analog signal, A pedestal clamp device, comprising: a control unit for controlling the output of the pedestal to the amplification unit. 2. The pedestal clamping device according to claim 1, further comprising: means for removing a high-frequency noise component included in the level difference signal, provided on an output side of the level difference signal generating means. Pedestal clamping device. 3. The pedestal clamp device according to claim 1, wherein the digital video signal is delayed by one line and transmitted as a delayed digital video signal.
Second delay means for delaying the level difference signal by one line and sending it as a delayed level difference signal; and inter-line error signals for interpolating a level error between lines in response to the level difference signal and the delayed level difference signal. A pedestal clamping device, comprising: means for generating; and means for subtracting and outputting the inter-line error signal from the delayed digital video signal.