JPH0356916Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a PCM processor, and more specifically, to an improvement of a PCM processor that uses a VTR as a recording and reproducing means.

In recent years, PCM processors designed so that VTRs can be used as means for recording and reproducing PCM signals have been attracting attention in the market.

The reason why PCM processors with such specifications are attracting attention is that PCM signals have a much wider signal frequency band (approximately 1 MHz) than analog original signals, and are
Hz), but since VTRs handle video signals, they have a recording frequency band of at least 4.5MHz, and have the technical advantage of being fully compatible with PCM signals.
This is due to the fact that VTRs are now quite popular and have commercial value for those who already own a VTR, as they can easily enjoy digital audio by purchasing just a PCM processor. .

However, VTRs were originally designed to be suitable for recording and reproducing video signals, and it cannot be said that sufficient consideration has been given to the connection of PCM processors.

For example, special playback modes such as slow playback, high-speed playback, and still image playback are now very important functions of VTRs, but when playing PCM signals, the tape running speed is completely different, and the rotating magnetic head and track are It becomes impossible to track the PCM signal, leading to coding errors in the PCM signal and unpleasant noise due to missing PCM signals.

Therefore, conventionally, in order to prevent the reproduction of the above-mentioned noise, a significant increase in the code error rate in the reproduced PCM signal during special reproduction was detected and the reproduced signal transmission system of the PCM processor was muted.

However, recent improvements in VTR technology have been remarkable, and even if a tracking error occurs during special playback, it is hardly affected by crosstalk from adjacent tracks or noise generated at track boundaries, and the above-mentioned code error There was a risk that the method of detecting and muting an increase in the ratio could not prevent noise from occurring due to incorrect operation of the VTR.

The present invention eliminates the above-mentioned drawbacks of the conventional technology, and it can be used to reliably and quickly prevent a VTR from being accidentally set to special playback mode during PCM signal playback.
The present invention provides a new muting means for muting the reproduced signal transmission system of a PCM processor.

First, before describing embodiments of the present invention, the basic principle of the present invention will be explained.

In the video signal, a vertical erasure period including a vertical synchronization signal is provided for each field.
In order to prevent switching noise from appearing on the TV screen when switching between multiple rotating heads during VTR playback, the joint position between tracks is made to correspond to the vertical erasing period, and these operations are performed using a vertical synchronization signal. I will do it.

This vertical synchronization signal continues for a total of 3H (1H: 1 horizontal scanning period) as shown in Figure 1a,
A notch P is inserted every H/2, and the rising time of each notch coincides with the phase of horizontal synchronization. In other words, as is clear from the differential waveform diagram of the vertical synchronizing signal shown in Figure 1b, by focusing only on the positive pulse of the differential waveform, an accurate H/2 synchronized signal can be obtained, and the horizontal period in the vertical synchronizing signal period can be completely corrected. can be held.

When special playback is performed on a VTR, periodic noise is generated due to misalignment of the relative position between the track and the rotating head. To counter this, in VTRs, the time point at which the noise occurs corresponds to the vertical blanking period, and the noise is controlled to be located outside the television screen. That is, a method is used in which a pseudo vertical synchronization signal is added to the noise generation period in the reproduced signal. However, this pseudo vertical synchronization signal does not include a horizontal synchronization component. This is because current televisions are configured so that they can maintain horizontal synchronization during the vertical blanking period by themselves, without relying on the horizontal synchronization component in the video signal. On the other hand, when recording a PCM signal with a VTR,
Within the PCM processor, the same pulses for vertical and horizontal synchronization as the video signal are added, and the signal is formatted into the same signal format as the video signal.
When playing back a VTR at normal speed, a vertical synchronization signal containing a horizontal synchronization component is present in the PCM signal. However, as in the case of the video signal described above, in the special reproduction mode, a vertical synchronization signal that does not include a horizontal synchronization component is present in the reproduced PCM signal.

Therefore, one possible method for confirming that the VTR is in special playback mode is to detect the missing 3H period of the horizontal synchronization signal in the PCM signal, but the code error correction ability of the PCM processor during normal playback is Even though the omission of the 32H period can be corrected, if the determination is made based on the omission of the horizontal synchronizing signal of the 3H period, there is a risk that the normal reproduction mode and the special reproduction mode cannot be distinguished.

This invention focuses on the points mentioned above,
Inside the PCM processor, the vertical synchronization signal in the PCM signal input from the VTR is separated, the presence or absence of a horizontal synchronization component in the vertical synchronization signal is detected, and if there is no horizontal synchronization component, a muting circuit is activated to process the PCM signal. This is characterized by cutting off the signal transmission system of the processor.

The present invention will be explained below based on the illustrated embodiments.

Figure 2 shows the mutating control device of the present invention installed in a PCM processor, and 1 is a VTR.
a synchronization signal separation circuit for separating a horizontal synchronization signal and a vertical synchronization signal from a video signal supplied from the video signal;
is an identification circuit that separates and identifies a horizontal synchronization signal and a vertical synchronization signal from a composite synchronization signal supplied from a synchronization signal separation circuit, and includes an integrating circuit 3 and a vertical synchronization signal detector 4 for separating and identifying vertical synchronization signals It is comprised of a differentiation circuit 5 for separating and identifying horizontal synchronization signals and a horizontal synchronization signal detector. 7 is an AND circuit, which applies the vertical synchronization pulse (output terminal VO) and horizontal synchronization pulse (output terminal HO) output from the identification circuit 2 to each input terminal, respectively.
Outputs the horizontal sync pulse added during the vertical sync pulse input period. 8 is a smoothing circuit, AND circuit 7
Convert the horizontal synchronization pulse obtained from this into a DC signal. 9 is a level comparator, the (+) input terminal is supplied with the DC signal from the smoothing circuit, the (-) input terminal is supplied with the reference signal generated from the reference power supply 10, and the DC output from the smoothing circuit 8 is supplied. If not supplied, the comparator 9 outputs a reference signal,
When a DC output is obtained from the smoothing circuit 8, a comparison output cannot be obtained. By the output of comparator 9,
The PCM signal transmission system or the transmission system of the original analog signal demodulated by DA conversion is operated by a muting circuit. In addition, the synchronization separation circuit 1, the integration circuit 3 of the identification circuit 2, and the differentiation circuit 5
may be used as is, which is originally provided in the PCM processor.

The configuration is as described above, and its operation will now be explained with reference to the waveform diagram of each part shown in FIG.

In the special playback state of the VTR, the synchronization separation circuit 1 is supplied with the PCM signal shown in FIG. 3a.
As shown in the figure, this PCM signal is added with a vertical synchronization signal V (pseudo vertical synchronization signal) that does not include a horizontal synchronization component. The composite synchronization signal (FIG. 3b) obtained by the synchronization separation circuit 1 is supplied to the identification circuit 2,
A pseudo vertical synchronizing signal V shown in FIG. 3c is obtained at the output terminal VO, and a horizontal synchronizing signal shown in FIG. 3d is obtained at the output terminal HO.

Next, each output of the discrimination circuit 2 is supplied to each input terminal of the AND circuit 7, but there is no horizontal synchronization signal during the vertical synchronization signal period (Fig. 3d), and the output of the AND circuit 7 does not appear. No (Figure 3c).

Therefore, no sign is supplied to the (+) input terminal of the comparator 9, and the output of the comparator 9 becomes a signal whose polarity is inverted from the reference voltage applied to the (-) input terminal. (Fig. 3 f). This negative polarity comparison output controls the signal transmission system of the PCM processor to be muted.

As mentioned above, when the VTR is in special playback mode,
No playback signal is output from the PCM processor.
On the other hand, in the normal reproduction mode, since a horizontal synchronization component exists in the reproduced vertical synchronization signal, a horizontal synchronization pulse is output from the AND circuit 7 (vertical synchronization signal period), and this horizontal synchronization pulse is transmitted to the smoothing circuit. Since the signal is DC exchanged at 8 and supplied to the (+) input terminal of the comparator 9, the above-mentioned muting control signal (negative polarity) is not output, and a reproduced output can be obtained from the PCM processor.

In this case, the relationship between the level of the DC signal and the level of the reference signal supplied to the (+) input terminal of the comparator 9 is set so that they are equal or the level of the DC signal is high. This is because in this embodiment, the muting operation output is a negative polarity signal. Note that the present invention does not limit the polarity and level of the muting operation output, and various modifications are possible in this respect.

Further, in this embodiment, the synchronization separation circuit 1 may be omitted and the PCM signal from the VTR may be directly applied to the identification circuit 2. FIG. 4 shows another embodiment of the present invention, in which it is determined that the special reproduction mode is in effect when a vertical synchronization signal that does not include a horizontal synchronization component is detected a plurality of times. In other words, in the embodiment shown in Fig. 2, if the horizontal synchronization component in the vertical synchronization signal is missing on the VTR side during normal playback, it will be mistakenly determined to be in special playback mode (in addition, if the omission is of this degree, a code error will occur). This can be sufficiently covered by the correction ability), so this is a method to avoid this.

The other embodiment shown in FIG. 4 has almost the same circuit configuration as the embodiment shown in FIG. The terminals HO are each connected to the other input of the AND circuit 7 via the inverter 11. The output of the AND circuit 7 is connected to the (+) input terminal of the comparator 9 via a smoothing circuit. To explain the operation using the waveform diagram in FIG. 5, FIGS. 5a and 5b show the output waveforms of the output terminals VO and HO, respectively, and the vertical synchronizing signal V from the output terminal VO is directly applied to the AND circuit. The horizontal synchronizing signal from the output terminal HO is inverted in polarity and applied to the AND circuit 7 (FIG. 5c). Therefore, in the special reproduction mode, the output waveform of the AND circuit 7 is as shown in FIG.
The pulse R that continues for the vertical synchronization signal period as shown in
is obtained and stored in the capacitor of the smoothing circuit. In this embodiment, when three vertical synchronization signals that do not include a horizontal synchronization component arrive in succession, that is, three pulses R are output (Fig. 5e), and the output voltage of the smoothing circuit reaches the predetermined value Q. When this is reached (FIG. 5f), the comparator 9 provides a muting operation output.

As mentioned above, the present invention is a PCM processor that uses a VTR as a recording/playback means.
If the VTR is accidentally switched to special playback mode, the playback signal transmission system is muted by detecting the presence or absence of a pseudo vertical synchronization signal that does not include the horizontal synchronization component that is added to the playback signal during special playback mode. Therefore, it has the effect of reliably preventing harsh noise during special playback.

[Brief explanation of drawings]

Fig. 1 is a waveform diagram showing a vertical synchronizing signal in a video signal and its differential waveform, Fig. 2 is a block diagram showing an embodiment of the muting control circuit of the present invention, and Fig. 3 is an explanation of the embodiment of the present invention. FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. 5 is a waveform diagram for explaining the embodiment shown in FIG. Explanation of symbols, 1... Synchronization separation circuit, 2... Identification circuit, 3... Integrating circuit, 4... Differentiating circuit, 5...
Vertical synchronizing signal detector, 6... Horizontal synchronizing signal detector, 7... AND circuit, 8... Smoothing circuit, 9...
Comparator.

Claims (1)

[Scope of utility model registration request] A PCM processor that uses a VTR as a recording and reproducing means includes an identification device that distinguishes and separates the horizontal synchronization signal and vertical synchronization signal in the PCM signal, and inputs each synchronization signal output from the identification device to generate the vertical synchronization signal. It is equipped with a detection device that detects the presence or absence of a horizontal synchronization signal in the period in which it exists, and a muting device that interrupts the reproduction signal transmission system of the PCM processor based on the detection signal from the detection device.
PCM processor.