JPS6286972A - Synchronizing signal reproducing device - Google Patents

Abstract

PURPOSE:To prevent the malfunction due to noise by deciding the regularity of the external synchronizing signal, when the regularity exists, deciding that a correct external synchronizing signal is reaching and fetching this. CONSTITUTION:To a conventional circuit, a frequency deciding circuit 7 to decide the frequency, in which the arriving synchronizing signal enters into a window W1, is added. A frequency deciding signal 7 investigates and compares the frequency in which an arriving synchronizing signal E enters into the window W1 outputted from a window output generating circuit 6 and the frequency in which the signal does not enter, when the former is many, the E is acknowledged as the correct synchronizing signal, (M1 output generation), by an AND circuit A1, it is prevented that a counter 5 is reset by the E and the counter 5 is reset by a self-excitation trigger I. For example, to AND circuits A3 and A4, the inverting output by the window W1 and an inverter N1 are inputted together with an external synchronizing signal E. When the external synchronizing signal E exists in the window W1, the output appears at the output side of the AND circuit A3 and when the E exists at the outside of the window W1, the output appears at the output side of an AND circuit A4.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is applicable to television receivers, video tape recorders (VTRs), etc.
), relates to a synchronization signal reproducing device used in various display devices, etc., and is particularly suitable for use when receiving external synchronization signals in poor reception environments such as weak electric fields and ghost signals. The present invention relates to a synchronization signal reproducing device.

[Background of the invention]

FIG. 7 is a circuit diagram showing a vertical synchronization signal separation and reproduction circuit in a conventional television receiver, in which 1 is an integrating circuit, 2 is a comparator, and 5 is a reference power source.

FIG. 8 is a waveform diagram of various signals in FIG. 7.

In these figures, Vl is a synchronizing signal in a well-known television signal, and v2 is an integrated waveform by the integrating circuit 1. The integral waveform v2 is compared with the reference voltage Vr of the reference power supply 3 by the comparator 2, and an output V3 is obtained. The rising edge tv of output (3) is used as a reproduced vertical synchronization signal.

As shown in the figure, a fine ripple component due to the horizontal synchronizing signal component is superimposed on the integral waveform (2), and it will be understood that the rising edge tv changes depending on the magnitude of the ripple component. This ripple component fluctuates due to the mixing of noise and ghost signals, resulting in fluctuations in the rising edge tv. This fluctuation is particularly noticeable as screen flickering on large-screen TVs, so in order to overcome this drawback, counter systems, analog or digital PLLs (phase lock systems), etc. have recently begun to be used.

Generally speaking, the counter method performs synchronous playback without fluctuations, but it is vulnerable to loss of external synchronization signals and large fluctuations.
Furthermore, the PLL system has drawbacks such as a long synchronization pull-in time.

Among the conventional methods, the method disclosed in Japanese Patent Application Laid-Open No. 51-23022 has the excellent features of being extremely quick to pull in and being resistant to loss and fluctuation of external synchronization signals, but it also suffers from malfunctions due to noise. It also has the disadvantage of being easy.

FIG. 9 is a chart showing the operation flow of the conventional method disclosed in the above publication, and includes steps (1) to (2). Moreover, FIG. 10 is a timing chart of signals in the same system.

First, in FIG. 9, start corresponds to turning on the power, switching channels, etc. This start causes a counter (not shown) to clock f. Start counting (step ■). clock f.

For example, it has a frequency of 2 which is twice the horizontal synchronization frequency fH.

Moreover, this color/return is designed to generate a self-excited trigger (2) exactly at a count number corresponding to the vertical synchronization period T. At the same time, the counter also generates a window output W near this self-excitation trigger I.

This situation is illustrated in FIG. If the external synchronization signal E is not input, the television receiver is vertically synchronized by this self-excitation trigger (2) output from the counter (see steps (2) and (3)).

In step ■, if the external synchronization signal E is input and present, and if it is further outside the window output W (step ■), this external synchronization signal E is used as a trigger (step ■) and the The counter is reset and then every vertical synchronization period T seconds the counter generates a self-running trigger I.

At this time, if E is a correct external synchronization signal, then the incoming E will fall within the window W. E, which falls within window W, is ignored as seen in step (3). Therefore, at this time, the self-excited trigger I continues to be used as the correct internal synchronization signal.

If E is included in the window W, E is ignored, so it is not affected by its omission or fluctuation, and therefore no jitter occurs on the screen.

Furthermore, since the periods of the self-excited trigger and the external synchronization signal E are the same, the phase pull-in is immediately completed when E arrives first. In other words, it also has the advantage of extremely short pull-in time.

FIG. 11 is a circuit diagram showing a hardware configuration for realizing the above conventional system. In the same figure, the counter 5 is clock f. is counted and reset by R terminal input. The counter 5 outputs a self-exciting trigger every predetermined count value, and when the external synchronization signal E is not input, the self-exciting trigger is input to the R terminal via the OR circuit 01 and resets itself.

Therefore, the counter 5 is repeatedly reset every cycle of the self-excited trigger. A window output W1 is simultaneously generated from the counter 5 using a window output generation circuit 6. When the external synchronization signal E arrives during the inversion period of the window output w1 (outside the window width W1), this synchronization signal E is sent to the AND circuit AI.

Since the signal is input to the R terminal via the OR circuit 01, the counter 5 is reset.

From then on, if the periods of E and I match, E is the window W.
1, no reception is made and the counter 5 continues to be reset by the self-excitation trigger I.

In the conventional synchronization signal reproducing device described above, in a noisy environment, the noise pulse outside the window W1 may be mistaken for the correct external synchronization signal E, and the counter may be reset. There are also problems such as screen skipping.

[Purpose of the invention]

The object of the present invention is to overcome the drawbacks of the prior art as mentioned above,
It is an object of the present invention to provide a synchronization signal reproducing device that prevents a noise pulse outside the window from being mistaken for a correct external synchronization signal.

[Summary of the invention]

As mentioned above, conventional synchronization signal reproducing devices have the problem of malfunction due to noise.

In the present invention, we focus on the difference that external synchronization signals have regularity while noise occurs irregularly, and determine the regularity of external synchronization signals. Assuming that an external synchronization signal has arrived, it will be taken in.

Furthermore, when the present invention is applied to multiple broadcasting systems, the synchronization signal period differs depending on the broadcasting system, so conventionally this was determined using a separate counter. This improves the reliability of the judgment and simplifies the circuit configuration.

[Embodiments of the invention]

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The circuit configuration shown in the figure consists of the conventional circuit shown in FIG. 11 with the addition of a frequency determining circuit 7 for determining the frequency with which an incoming synchronization signal enters the window W1.

This frequency determination circuit 7 examines and compares the frequency at which the incoming synchronization signal E enters the window W1 outputted from the window output generation circuit 6 and the frequency at which it does not enter the window W1, and if the former is in the majority, this Make sure to recognize E as the correct synchronization signal.
1 output), the AND circuit A1 is used to prevent the counter 5 from being reset by this E, and the counter 5 is
is set to be reset by the self-excitation trigger ■.

FIG. 2 is a circuit diagram showing a specific example of the frequency determination circuit 7 in FIG. 1.

In the figure, AND circuits A3 and A4 have windows W
1 and its inverted output by inverter N1 are input together with external synchronization signal E. If the external synchronizing signal E is within the window W1, an output will appear on the output side of the AND circuit A3, and if E is outside the window W1, an output will appear on the output side of the AND circuit A4.

The outputs of AND circuits A3 and A4 are applied to up input terminals U of up/down counters 8 and 9, respectively. If the frequency of E being within the window W1 is high, the counter 8 will generate a full count output earlier than the counter 9.

In the opposite case, the output of counter 9 becomes faster (counter 8,
The full count outputs of 9 are collected in OR circuit 03, and the outputs are applied to the down input terminals of counters 8 and 9.

For example, when the counter 8 reaches a full count, either counter is incremented, and the operation is repeated. Therefore, in counters 8 and 9,
The one with higher frequency of up inputs will reach the full count first, and the other side will have more down inputs than up inputs, so one side will always have a full count and the other will reach zero or 1.
It settles into a state of counting.

Since the output M1 of the counter 8 is evidence that E frequently arrives in the window W1, the inverted signal of the output M1 is applied to the AND circuit A1 as shown in FIG. Prevent it from being reset. On the contrary, if E is frequently present outside the window W1, the M1 output is not generated and the AND circuit A1 passes E, so that the counter 5 is reset by E.

The circuit shown in FIG. 2 is a kind of inertial circuit, and for example, even if the output of the AND circuit A4 happens to occur when the up/down/counter 8 is at full count, the circuit in FIG. The state where the counter 8 is at full count is maintained. That is, even if the number of cases where E is inside or outside the window W1 fluctuates, as long as one of them is in the majority, the output M1 is kept constant.

In a normal case, the circuit scale of the circuit shown in FIG. 2 can be extremely small because it is sufficient to use counters of about 2 bits each as the up/down counters 8 and 9.

The embodiments of the present invention described above are for reproducing only one type of synchronization signal that arrives. The present invention can be applied to a multi-system, that is, a multi-system for reproducing one type of synchronization signal that arrives from among multiple types of synchronization signals with different periods. An example in which the method is applied will be described below.

The first method is to arrange the circuit system shown in FIG. 1 by the number of types of incoming synchronization signals.

To simplify the explanation, a case will be described in which 20,000 types of synchronization signals in which two types of synchronization signals arrive in FIG. 3 are handled.

In FIG. 6, two sets of the circuit configurations in FIG. 1 are drawn vertically symmetrically, and the portions surrounded by broken lines are newly added.

Regeneration synchronization outputs (self-excited triggers) 1 and I2 are obtained from the upper and lower circuit blocks, respectively. Of these, you must choose the correct one. Furthermore, it is necessary to decide which of the self-running self-excited triggers 1 and I2 will be output when there is no signal.

In this case, if iI2 is correct, the M2 output is set, so this is used to output I2, and in other cases, 11 is output. Therefore, even when there is no signal, signal 1 becomes an output. Circuit blocks surrounded by broken lines (AND circuits A71A8
and OR circuit 05) make this selection.

A second embodiment that deals with multiplication will be described with reference to FIGS. 4 and 5. In the multi-system, one type of external synchronization signal that has arrived is selected from among several types of external synchronization signals with different periods, and this signal is reproduced. Therefore, in order to multiply the method described with reference to FIG. 1, as many internal synchronization signals (self-excited triggers) I and windows W as there are types of external synchronization signals to be handled are required.

Also, after resetting the counter with external synchronization signal E, the next E
It is necessary to determine which window is in and select the appropriate technique.

FIG. 4 is a flowchart used to explain this aspect of the invention, and FIG. 5 is a timing chart of signals used in conjunction.

In Fig. 4, start the count at the start (step ■), wait for the arrival of the external synchronization signal E (step ■),
If E is not present, an internal synchronization signal I4 is generated (step 2). Unlike the case of FIG. 1, this I4 is generated at the outermost part of each window, as shown in FIG.

In step ■, if E is found, proceed to step ■,
Window W1.E was prepared. If it is not within either W2 or W3, but outside of them, the process proceeds to step (3), and at step E, the counter is reset as in the case of FIG.

The next E is the prepared window W1 r W2 r W
Fall into one of 5. The number of windows W is equal to the number of methods to be handled (the number of types of synchronization signals). In this case, it is 30,000 types.

FIG. 5 shows a case where the next E1, that is E2, enters the window W2, and correspondingly, an internal synchronization signal 2 is generated from the trailing edge of the window W2.

If E2 enters the window W5, a cut 3 is similarly generated from the trailing edge of the window W5.

The method of generating defects in this area is different from that in the embodiment shown in FIG. That is, in the case of the embodiment shown in FIG.
There was only one wind W, and if E entered the instep, it was ignored and a predetermined self-excited trigger was generated. In the case of the multi-system, since there are many windows W, it is first necessary to identify which window W has entered, and after that identification, the corresponding self-excitation trigger I must be generated. It will be at the rear.

In this case, each I is assumed to occur at the trailing edge of each window W, but it may be extracted from the clock f○ following E, for example.

FIG. 6 is a specific circuit configuration diagram for realizing the operation described with reference to FIGS. 4 and 5. FIG. From the counter 11, three windows w1. w2 and W3 are generated, and internal synchronization signals 11. I2 and work 3 are created. The OR circuit 04 calculates the logical sum of these six windows (Wl +W2
+Ws) is taken, and this and external synchronization signal E are ANDed by AND circuit A5. As a result, the AND circuit A5 generates an output when E is within any window W. The flip-flop 12 is set (S) by the output of the AND circuit A5. This flip-flop 12 is each made by the OR circuit 05.
It is reset by the logical sum (I+ +I2 +I3) of (I+ +I2 +I3), but in reality, after being set, it is first reset by *.

The inverted output of the flip-flop 12 due to this reset is differentiated and sent to the counter 1 via the OR circuit 01.
In addition to the R terminal of 1, it is used as a reset signal. By doing K in this way, Kara/Re 11 will be reset at ■ immediately after E that enters any window W, so that I
becomes the correct playback synchronization signal.

As a means to avoid malfunctions due to noise, measures similar to those described with reference to FIGS. 1 and 2 are applied. That is, the frequency determining circuit 14 determines the frequency with which E appears in each window W, and if the frequency is large, E
This prevents the counter 11 from being reset.

There is no need to explain that the loop shown by the broken line plays this role.

〔Effect of the invention〕

According to the present invention, there is an advantage that malfunctions due to noise can be prevented in synchronization signal reproducing devices used in television receivers, video tape recorders, displays, etc.

Furthermore, it is possible to realize a multi-system synchronized playback device that accepts and reproduces only the system input that has arrived from among a large number of system inputs with a simple circuit configuration, and it has the advantage of being able to prevent malfunctions due to noise. be.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
5 is a circuit diagram showing a specific example of the frequency determination circuit in the figure; FIG. 5 is a circuit diagram showing another embodiment of the present invention; FIG. 4 is a chart showing the flow of operation of still another embodiment of the present invention; FIG. 5 is a signal timing chart in the same embodiment, FIG. 6 is a circuit diagram showing the same embodiment, FIG. 7 is a circuit diagram showing vertical synchronization signal separation and regeneration circuit in a conventional television receiver, and FIG. 7 is a waveform diagram of various signals in FIG. 7, FIG. 9 shows the flow of operation in the conventional synchronous signal regeneration method, FIG. 10 is a timing chart of signals in the same method, and FIG. 11 is a node diagram of the same method.・It is a circuit diagram showing a − code configuration. Explanation of symbols 1...Integrator circuit, 2...Comparator, 6...Reference power supply, 5...Counter,
6...Window output generation circuit, 7...
Frequency judgment circuit, 8, 9... Up/down counter, 11... Counter, 12...
Flip-flop, 13A to 13C... Window output generation circuit, 14... Frequency judgment circuit Representative Patent attorney Akio Namiki Figure 1 Figure 3 Figure 4 Figure 5 Figure 6 Figure 9

Claims (1)

[Scope of Claims] 1) A synchronization signal reproducing device that detects and reproduces an external synchronization signal that is repeatedly input from the outside at a predetermined period, which counts clock signals and is reset by the output obtained at a predetermined count value. The reset period is made to match the period of the external synchronization signal, and the reset output is used as a synchronous reproduction output, and the window output generation circuit of a predetermined time width synchronized with the reset period is connected to the counter. In a synchronization signal reproducing device attached to a counter, which detects only when an external synchronization signal arrives outside the window width and resets the counter using the external synchronization signal, the external synchronization signal that arrives means for comparing the frequency of cases in which the number falls within the window width and the number of cases in which the number does not fall within the window width to determine which is the majority; A synchronization signal reproducing device comprising: means for prohibiting the counter from being reset. 2) A multi-system synchronization signal reproducing device that detects and reproduces one external synchronization signal from among a plurality of external synchronization signals each having its own predetermined period, which counts clock signals and performs a predetermined calculation. The counter includes a counter that is reset numerically, and the counter is capable of generating a plurality of reset signals corresponding to a plurality of count values depending on the number of types of external synchronization signals, and the reset period of these signals is set according to the number of external synchronization signals. Matching each cycle of the signal, it is possible to output any of the reset signals in synchronization, and
A plurality of window output generation circuits that generate window outputs of a predetermined time width in synchronization with each of the reset cycles are attached to the counter, and when an incoming external synchronization signal does not fall within any of the windows, the external A synchronization signal resets the counter, and if the external synchronization signal falls within any of the windows, one of the reset signals corresponding to that window resets the counter, and the external synchronization In a multi-system synchronization signal reproducing device that resets the counter with a separately prepared no-signal reset signal in addition to the reset signal when the signal does not arrive, the external synchronization signal that has arrived is located in either of the windows. means for comparing the frequency of cases in which the frequency falls within the above range and the frequency of cases in which the frequency falls within the above range to determine which of the cases is in the majority; A synchronization signal reproducing device comprising: means for prohibiting the counter from being reset.