JPH04207576A - Vertical synchronizing signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain stable vertical synchronizing performance by automatically changing over by which of 1st and 2nd gate pulses a sampling output is gated to a sampling output. CONSTITUTION:The window pulses for gate to be applied on the vertical pulse VP outputted from a sampling circuit 3 are formed in plurality and are automatically changed over by the input state of the vertical synchronizing signal VSync that the window pulse of a narrow width is inputted to a terminal 7 in the stable input state at which the vertical pulses VP are periodically and continuously obtd. and the window pulse of a broad width is inputted in the astable input state at which the above-mentioned pulses are not obtd. Then, the pulse separate from the vertical synchronizing signal VSync is masked even if this pulse is generated by noise, etc., when the periodic and continuous vertical synchronizing signal VSync is obtd. The erroneous recognition of this pulse as the vertical pulse VP is thus obviated. On the other hand, the pulse of the broad width is used as the gate pulse in the case of a phase deviation or the input of the non-standard signal and, therefore, a vertical pull in is executed over a wide range. The stable vertical synchronization performance is obtd. in this way.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is directed to vertical synchronization in television receivers that prevent circuit malfunctions in weak electric fields or when noise is mixed in, thereby obtaining stable vertical synchronization. It relates to a synchronous signal processing circuit.

(Prior Art) FIG. 4 shows a vertical synchronization signal processing circuit using a conventional countdown method. Vertical synchronization signal V S y obtained by separating the composite synchronization signal from a vertical synchronization separation circuit (not shown)
nc is supplied as an input to input terminal 7. Input terminal 7
The vertical synchronizing signal ■Sνnc input to the vertical synchronizing signal VSync is used by the sampling circuit 3 to obtain a vertical pulse ■P having the same phase and period as the vertical synchronizing signal VSync. Based on this pulse P, a vertical pulse P' is obtained from the output of the gate circuit 4, and the reset pulse generating circuit 5, which receives this pulse VP', generates a reset signal for the vertical counter. A vertical counter 1 counts vertical periods, and a decoder 2 inputs the output of this counter and decodes it to obtain a vertical output Vo synchronized with V Sync.

If noise is present in the vertical pulse VP, the vertical counter 1 will have to be reset repeatedly, which will cause a problem with the vertical synchronization counter and eventually disrupt the vertical synchronization. Therefore, in the conventional vertical synchronization signal processing circuit, a gate window pulse Win of the vertical pulse VP is provided near the phase at which the vertical pulse VP will arrive, and pulses arriving outside the window are masked as noise. From this, it is possible to obtain a vertical pulse P' from which noise components have been removed, and disturbances in vertical synchronization can be suppressed.

On the other hand, as shown in Fig. 5, when the phase of the vertical pulse VP deviates from the phase of the vertical counter due to channel switching, etc., the vertical pulse vP appears outside the window.
This may be masked. If this happens, it will appear to be exactly the same situation as if the vertical synchronization (No. 6 V sync or V sync is missing), and the vertical synchronization will be disrupted. Is it necessary to have a wide window?Therefore, the width of the gate pulse Win was made wide, as shown in Figure 6.However, with this, there is a possibility that the noise generated within the window may be mistaken for the vertical pulse VP. It can be said that it is insufficient to achieve the original purpose of masking noise.

(Problem to be solved by the invention) The gate window pulse in the conventional vertical synchronization signal processing circuit has contradictory drawbacks: increasing the width deteriorates the noise resistance performance, and decreasing the width reduces the pull-in range. We are prepared.

An object of the present invention is to provide a vertical synchronization signal processing circuit that has stable vertical synchronization performance by masking noise components that enter the input without narrowing the vertical synchronization pull-in range.

[Structure of the invention] (Means for solving the problem) A narrow window pulse is used in a stable input state where vertical pulses VP are obtained periodically and continuously, and a wide window pulse is used in an unstable input state where the vertical pulse VP is not obtained periodically and continuously. The vertical pulse ■P depends on the input state of the vertical synchronization signal VSync.
To automatically switch between multiple gate window pulses applied to a gate.

(Function) According to the above means, the periodic and continuous vertical synchronization signal V
When Sync is obtained, the narrow path is used as the gate pulse, so the vertical synchronization signal V S
Even if a pulse other than ync occurs, it is masked, so it will not be mistaken as a vertical pulse ■P. on the other hand,
In cases where there is a phase shift or non-standard signal input, vertical synchronization can be pulled in over a wide range by using a wide pulse as a gate pulse.

(Embodiment) An embodiment of the present invention will be explained using FIG.
The same parts as in the figures are given the same reference numerals.

A vertical synchronizing signal V sync is inputted to a terminal 7, and the sampling circuit 3 performs sampling to obtain a pulse having the same phase and period as the vertical synchronizing signal 5ync, and outputs a vertical pulse P. - side, vertical counter 1
is 2n times the horizontal synchronization frequency fH (n-0, 1,...)
is used as a clock and frequency-divided to produce divided outputs Ql, Q2 .
Q3... is applied to the decoder 21 to generate a narrow window pulse N-W at the phase where the vertical pulse VP is expected to arrive.
A wide window pulse W-Win is output. This window pulse N-Win, W-Win is, for example, 282.5 if the vertical synchronization frequency is 60 Hz.
11.50H2, 31.2,5) Generate a window centered at t. Note that the wide window pulse W-Win must not be below the set vertical synchronization pull-in range.

The vertical pulse ■P and narrow window pulse N-Win are input to the coincidence/continuity detection circuit 8, and the vertical pulse VP1 and wide window pulses N-Win and W-Win are input to the control signal generation circuit 9. The coincidence/continuity detection circuit 8 detects whether the vertical pulses P arrive periodically and continuously, and outputs this detection output to the control signal generation circuit 9. The control signal generation circuit 9 outputs a control signal for the coincidence/continuity detection circuit 8 from the vertical pulse VP, narrow width, wide window pulses N-Win, W-Win, and further outputs a control signal for the coincidence/continuity detection circuit 8 from the coincidence/continuity detection output. It outputs a window control signal WC that determines which window to select as a pulse. Narrow and wide window pulses N selected by window control signal WC
-Win, W -Wln is applied as a gate signal to the vertical pulse VP in the gate circuit 4, and the reset pulse CL of the vertical counter 1 is sent to the reset pulse generation circuit 5 from VP' which outputs the vertical pulse ■P'. and output it to the vertical counter]. As a result, the vertical counter performs a counter operation synchronized with the vertical frequency.

The no-signal detection circuit 10 also sends a signal T for resetting the vertical counter 1 in an extremely weak electric field where the vertical synchronization signal VSynC cannot be sampled or in an unattended state.
Output V RESET.

FIG. 2 shows a specific example of the control signal generation circuit 9 and the coincidence/continuity detection circuit 8 of FIG. 1, which will be explained below together with the timing chart of FIG. 3.

In this circuit, depending on the input state of the vertical synchronization signal VS)'e, the gate window pulse of the vertical pulse ■P is set as N-Wln when the vertical pulse VP is periodic and has no noise, or periodic and has noise. , VP is aperiodic, out of phase, or when there is no signal input, W−Wjn is used. In other words, if stable human power is available such that the vertical synchronization signal v syc arrives periodically and continuously, the narrow window pulse N-Win is used as the gate window.

If a stable input such as the vertical synchronization signal Vsyc that arrives periodically and continuously is obtained, the narrow window pulse N-Win is used as the gate window.

To determine whether the vertical pulse ■P arrives periodically, input the vertical pulse VP and the narrow window pulse N-Win to the AND 18 of the coincidence/continuity detection circuit 8, perform coincidence detection, and check A.
It can be determined whether the vertical pulse (P) is obtained depending on the output state of the ND18. The output of the detected match is input to the D-FF 20.degree. 21 via the NOR 19, and continuous detection is performed.

At this time, the Q output of D-FF20, 21 in the initial state is "
Since L o-, the output of N0R19 is AND 18
equals output. In the circuit example of FIG. 2, it is assumed that the input is stable if the vertical pulse VP exists within the narrow window pulse N-Win three times in a row, and AND 17
The window control signal WC, which is the output of Therefore, AND24 has vertical pulse VP1 narrow width,
Three signals, wide window pulses N and W-Win, are supplied, and as a result, narrow width N-Win masks the vertical pulse vP to obtain the vertical pulse VP'.

Furthermore, if noise is mixed in or a vertical synchronization phase shift occurs, it is expected that a pulse will rise outside the narrow window pulse N-Win. It is not known whether this pulse is a vertical pulse (P) or noise at the time the pulse is generated. Therefore, if a pulse is detected within the narrow window pulse N・Wln, which is the expected timing of the next vertical pulse VP, this is regarded as VP, and the gate window pulse is set as the narrow window pulse N−WIn. If not detected, switch to wide window pulse w-win. In other words, the narrow window pulse N-Win is applied to AND12.
AND13 the signal inverted by TII and the vertical pulse VP.
A narrow window pulse N-W j n is generated by manually applying a narrow window pulse N・Win and a vertical pulse VP.
If a pulse exists outside the period, R5-FF 15 is set. Then narrow window pulse N −W i
If a pulse arrives within the n period f'41, it is regarded as a vertical pulse VP and reset. Input the Q output of R3-FF to D-FF16 and generate wide window pulse W*
At the trailing edge of W in, the Q output is “Lo
”, the Q output of the D-FF 16 is kept at “Lo”, and if it is still at “H4”, the continuous detection D-FF 20, 2'l is reset with ")If".D-
When the D-FF 20.21 whose Q output of the FF 16 is Lo' is not reset, the gate window pulse remains N-Win as described above. Also D-FF1
When the D-FFs 20 and 21 whose Q outputs are "Hl" are reset, the window control signal WC becomes "Lo", so the output of the NAND 23 becomes "Hi", resulting in a wide window pulse. W-Win or MLL'
! A gate is applied to the pulse ■P.

Also, the output TV I? of the no-signal detection circuit 10? Even when ESfT becomes “Hi”, by adding a set signal to D −F F ], 6, the window control signal WC becomes “
Lo” and set the gate window pulse to wide window pulse W-Win.However, TV RI'SET
During this period, the wide window pulse W.Win is always set to "Hj" so that vertical synchronization can be pulled in even if the vertical pulse VP appears in the same phase as the vertical pulse VP.

In this way, when it can be determined that the vertical pulse VP is arriving periodically and continuously, the VP gate window pulse can be set to narrow N-Win to mask noise outside the N-Win period. . In addition, when there is a phase shift in vertical synchronization or when there is no signal by hand, the wide W-Win is used as the gate window for vertical pulse (P) to detect the vertical pulse VP over a wide range, so that the pull-in range of vertical synchronization can be widened.

[Effects of the Invention] As described above, according to the vertical synchronization signal processing circuit of the present invention, it is possible to obtain vertical synchronization performance that is less susceptible to the influence of noise without narrowing the pull-in range, and is suitable for integration into an integrated circuit. Become something.

[Brief explanation of the drawing]

Fig. 1 is a system diagram showing an embodiment of the present proposal of this invention, Fig. 2 is a specific circuit diagram of the main part of Fig. 1, and Fig. 3 is a time chart diagram for explaining Fig. 2. , FIG. 4 is a conventional system diagram, and FIGS. 5 and 6 are time charts for explaining FIG. 1, respectively. 1... Vertical counter 3... Sun printer circuit 4...
...Gate circuit 5...Reset pulse generation circuit 8...
・・・・・・Coincidence/continuity detection circuit 9 ・・・・・・・・・
Control signal generation circuit 10...No signal detection circuit 21...Decoder CL/no>

Claims (3)

[Claims] (1) A vertical counter that is reset in synchronization with a vertical synchronization signal and counts pulse signals with a frequency that is an integral multiple of the horizontal period, a sampling circuit that generates a pulse signal with a vertical period from the vertical synchronization signal, and the sampling circuit a gate pulse generation circuit that generates a wide first gate pulse and a narrow second gate pulse for gating the sampling output of the first or second gate pulse, and a comparison between the first or second gate pulse and the sampling output. a detection circuit that detects whether the vertical synchronization signal is continuous and stable with a constant period; A vertical synchronization signal processing circuit comprising: a switch circuit that automatically switches whether to apply a gate using a gate pulse; and a gate circuit that applies a gate pulse selected by the switch circuit to the sampling output. (2) The vertical synchronization signal processing circuit according to item 1, wherein the gate pulse generation circuit is configured to obtain the output from a decoded output of the output of the vertical counter. (3) The vertical synchronization signal processing circuit according to item 1, wherein a pulse having a trailing edge of the gate circuit output as a rising edge is generated and supplied as a reset signal of a vertical counter.