JPS62281688A - Data sampling circuit for teletext receiver - Google Patents

Abstract

PURPOSE:To insure signals against being affected by a noise component overlapping with a character signal by sampling the character signal by a clock pulse synchronizing with a bit synchronizing pulse. CONSTITUTION:By releasing a gate as long as a gate pulse (b) is given, a gate circuit 2 takes out the bit synchronizing pulse (c) from the character signal (a). Given with the bit synchronizing pulse (c), an oscillator circuit 3 outputs a clock pulse at 5.7272 mHz synchronizing with the bit synchronizing pulse (c). Given with a clock pulse (d), a data gate pulse generator circuit 4 outputs a gate pulse (g). Since an analog switch 1 becomes conductive as long as the gate pulse (g) is given, the character signal is sampled. The sampled character signal (h) is compared with a slice voltage V2 set to half the peak of the character signal. As a result a pulse signal (i) is outputted from a comparator 7. Thus noise hardly affects a comparison output signal.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention (Technical Field) The present invention relates to a data extraction circuit for a character multiplex receiver that extracts character data from character signals superimposed during the vertical blanking period of a television signal. Regarding.

(Prior Art) A data sampling circuit of a conventional text multiplex receiver inputs a text signal as it is to a comparator, compares the text signal with a slice voltage set at an appropriate level, and shapes the text signal into a waveform. On the other hand, character data is extracted by extracting a bit synchronization pulse (CR multiplied signal) from the transmitted character signal and sampling the waveform-shaped character signal at the timing of a clock pulse synchronized with this.

However, if the character signal input to the comparator contains noise components such as impulse noise or ghosts, the effect of the noise is reflected in the output of the comparator because conventional circuits input the character signal as is to the comparator. As a result, there is an inconvenience that errors occur in the character data.

(Object of the Invention) The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data extraction circuit for a text multiplex receiver that is less susceptible to the effects of noise components superimposed on text signals. There is.

(Structure of the Invention) In order to achieve the above object, the present invention has the following structure.

That is, the data extraction circuit of the character multiplex receiver according to the present invention includes a clock pulse generation means for extracting a bit synchronization pulse included in a character signal and generating a clock pulse synchronized with the bit synchronization pulse, and a clock pulse generation means for generating a clock pulse from the clock pulse generation means. A sampling means that receives a pulse and samples a character signal at the timing of the clock pulse, and a comparison means that compares the character signal sampled by the sampling means with an appropriately set slice voltage. It is characterized by

As described above, by sampling the character signal with a clock pulse synchronized with the bit synchronization pulse, noise components superimposed outside the sampling period are removed. Therefore, since the comparison means is only slightly affected by noise, the occurrence of errors in character data is reduced.

(Example) Hereinafter, the present invention will be described in detail based on an example shown in the drawings.

FIG. 1 is a block diagram schematically showing the configuration of a data sampling circuit of a character multiplex receiver according to an embodiment of the present invention.

The character signal superimposed on the vertical blanking period of the television signal is applied to the analog switch 1 as the sampling means and the gate circuit 2. In the gate circuit 2, a bit synchronization pulse included in the character signal is taken out, and this bit synchronization pulse is applied to the oscillation circuit 3. The oscillation circuit 3 outputs a 5,7272 MHz clock pulse synchronized with the bit synchronization pulse. Here, the gate circuit 2 and the oscillation circuit 3 correspond to the clock pulse generation means.

The clock pulse is applied to a data gate pulse generation circuit 4. The gate pulse of the data gate pulse generation circuit 4 is applied to the analog switch l and also applied to the clock pulse input terminal CK of the latch circuit 6 via the inverter 5.

On the other hand, the output of the analog switch 1 is given to one side of the comparator 7 as the comparison means. The comparator 7 is supplied with the slice voltage output from the slice voltage generation circuit 8 as the other input. The output of the comparator 7 is given to the D terminal of the latch circuit 6. The output of the latch circuit 6 is taken out as character data via an inverter 9.

Next, the operation of the data extraction circuit of the character multiplex receiver having the above-described configuration will be explained with reference to FIG.

Suppose now that a character signal a as shown in FIG. 2 ta+ is input to the data sampling circuit according to this embodiment. In the same figure (al), Sl indicates a horizontal synchronization signal, Sl indicates a color burst signal, S3 indicates a bit synchronization pulse, and S4 indicates information data. A gate pulse b shown in FIG. [b] is applied. The gate circuit 2 extracts a bit synchronization pulse C as shown in FIG. 2 fcl from the character signal a by opening the gate only during the period during which the gate pulse b is applied. The oscillation circuit 3 given this bit synchronization pulse C outputs a clock pulse d of 5,7272 MHz synchronized with the bit synchronization pulse C as shown in FIG. 2 (dl).

In addition, in FIG. 2 tel, the information data S4 of the character signal a is
Fig. 2 (ff) shows the clock pulses d shown in Fig. 2 (dl) with their respective time axes extended.

Description will be given below with reference to these figures.

The data gate pulse generation circuit 4 given the clock pulse d outputs a gate pulse g as shown in the 211th ffl (gl).The analog switch 1 becomes conductive only during the period when the gate pulse g is given. As a result, a character signal as shown in Figure 2 fhl is sampled.The sampled character signal is approximately half the peak value of the character signal shown in Figure 2 (hl). As a result, the comparator 7 outputs a pulse signal i as shown in FIG. 2 (1). This pulse signal i is applied to the launch circuit 6. , is latched at the timing of the gate pulse g applied via the inverter 5, so that the inverter 9 outputs character data j as shown in FIG.

By the way, as shown in FIG. 2 (al), it is assumed that impulse noise N is superimposed on the character signal.

At this time, unless the impulse noise N is superimposed within the sampling period, the noise does not pass through the analog switch 1, so such noise does not affect the output of the comparator 7. Therefore, in the output of character data j shown in FIG. 2 (jl), the impulse noise N
This does not include data errors due to

In the above embodiment, the output of the comparator 7 is sent to the launch circuit 6.
Although the latch circuit 6 facilitates subsequent signal processing, it is possible to achieve the intended purpose of the present invention, which is to reduce the influence of noise on character data, without using such a latch circuit 6. The invention does not necessarily require such a latch circuit.

(Effects of the Invention) As is clear from the above explanation, the data sampling circuit of the character multiplex receiver according to the present invention samples a character signal in advance using a clock pulse synchronized with a bit synchronization pulse, and Character data is obtained based on comparing the signal with the slice voltage. Therefore, according to the present invention, compared to the case where the character signal is directly input to the comparison means as in the conventional circuit, the influence of noise is less likely to appear on the comparison output signal, so that errors in character data due to the noise are less likely to occur. The occurrence can be reduced.

[Brief explanation of the drawing]

Part 1II is a block diagram schematically showing the configuration of a data extraction circuit of a character multiplex receiver according to an embodiment of the present invention;
The figure is an operation waveform diagram of each part of the embodiment shown in FIG. 1. 1...Analog switch, 2...Gate circuit, 3.
...Oscillation circuit, 4...Data gate pulse generation circuit,
6... Launch circuit, 7... Comparator, 8... Slice voltage generation circuit.

Claims (1)

[Claims] Clock pulse generation means for extracting a bit synchronization pulse included in a character signal and generating a clock pulse synchronized with the bit synchronization pulse; Data for a character multiplex receiver, comprising: a sampling means for sampling a character signal at a timing; and a comparison means for comparing the character signal sampled by the sampling means with an appropriately set slice voltage. Sampling circuit.