JPH04297187A - Synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To execute the synchronizing separation with high accuracy in a position in the vicinity of a pedestal of a composite video signal, and to realize the synchronizing separation being free from a malfunction by providing a pedestal clamp circuit, a comparator, and a reference bias circuit. CONSTITUTION:A pedestal clamp circuit 10 clamps a pedestal part of an input composite video signal by first DC potential. This comparator 11 inputs an output signal of this pedestal clamp circuit 10 to one input terminal and to the other input terminal, second DC potential set to the potential of the synchronizing tip side being lower than first DC potential is applied and compared, and an output signal of this comparator 11 becomes a synchronizing separation output.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization separation circuit for separating a synchronization signal from a composite video signal.

0002

2. Description of the Related Art Conventionally, when separating a synchronization signal from a composite video signal, a circuit as shown in FIG. 4 has been used. In the figure, the composite video signal input from input terminal 1 has its DC component cut by capacitor C1, and resistors R1 and R
After being divided by 2, it is input to the base of transistor Q1. Here, since the input composite video signal is input with synchronous positive polarity, if the division ratio of resistors R1 and R2 is set appropriately, transistor Q1 is turned on only during the synchronous signal period, and current flows through resistor R3. The transistor Q2 is turned on, the potential of the resistor R4 rises, and a pulse is obtained at the output terminal 2 that is high only during the synchronization signal period and low during the other periods, allowing synchronization separation. Note that terminal 3 is a power supply terminal.

0003

[Problems to be Solved by the Invention] In this conventional synchronization separation circuit (FIG. 4), when the APL (average picture level) of the composite video signal changes, the DC level of the synchronization signal changes. There is a risk that the black part of the image may be mistakenly separated from the sync signal. In order to avoid this, it is necessary to separate the resistor R at the tip of the synchronization signal.
It is necessary to set a division ratio of 1, R2.

On the other hand, in a television receiver, for example, a composite video signal has a low level due to synchronization signals being clogged in a weak electric field. Alternatively, when so-called dubbing, which involves repeated recording and playback using a video tape recorder, the synchronization signal becomes clogged, and therefore, if separation is performed at the leading end of the synchronization signal, the synchronization signal cannot be separated. There is a drawback that it becomes a problem.

[0005] The purpose of the present invention is to eliminate such drawbacks,
An object of the present invention is to provide a synchronization separation circuit that can reliably perform synchronization separation near a pedestal of a synchronization signal.

[0006]

[Means for Solving the Problems] The configuration of the synchronization separation circuit of the present invention includes a pedestal clamp circuit that clamps the pedestal portion of an input composite video signal at a first DC potential, and an output signal of this pedestal clamp circuit that is connected to one input. and a comparator that applies and compares a second DC potential set to a potential closer to the synchronization tip side than the first DC potential to the other input terminal, and performs synchronization separation of the output signal of this comparator. It is characterized by output.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram illustrating a synchronization separation circuit according to an embodiment of the present invention. An input composite video signal is applied to a pedestal clamp circuit 10 from an input terminal 1. This pedestal clamp circuit 10 is a reference bias circuit 1
The pedestal portion of the input composite video signal is clamped by the first DC potential V1 created in step 2, and a signal in which the pedestal portion of the composite video signal is at the DC potential V1 is obtained. A timing signal for clamping is input from the clamp pulse input terminal 13.

The composite video signal thus clamped is input to the comparator 11 at the next stage. The comparator 11 slices the clamped composite video signal using the second DC potential V2 generated by the reference bias circuit 12 as a reference voltage, and outputs the obtained signal from the output terminal 2 as a synchronization signal. .

Next, FIG. 2 is a waveform diagram illustrating the operation of the circuit of FIG. 1. The clamped synchronous negative polarity composite video signal A has a pedestal level equal to the first DC potential V1.
Therefore, the synchronizing signal is always at a lower potential than the first DC potential V1.

On the other hand, the second DC potential V2 is set to be slightly lower than the first DC potential. Since the copanlator 11 performs slicing based on this second DC potential V2, the output of the comparator 11 can obtain a high or low signal only during the synchronization signal period, and only the synchronization signal can be separated.

These first and second DC potentials V1 and V2
Since they are created by the same reference bias circuit 12, they can be made with extremely high precision, and the difference between the two potentials can be set small, so it is possible to separate them near the pedestal level of the synchronizing signal, and it is stable even if synchronization jams occur. works. Further, since pedestal clamping is performed, even if the APL of the composite video signal changes, the DC potential of the synchronizing signal does not change, and there is no possibility of erroneously separating black parts. A clamp pulse for obtaining the timing of this clamp pulse can be obtained by a conventional deflection processing circuit (not shown).

FIG. 3 is a circuit diagram specifically implementing the block diagram of FIG. The input composite video signal is inputted with synchronous negative polarity from the input terminal 1, and is led to the non-inverting input terminal of the comparator 11 via the capacitor C1.

The reference bias circuit 10 includes a transistor Q
6 to Q8, resistors R8 to R13, and Zener diode D1, the constant voltage of Zener diode D1 is connected to the base-emitter voltage of transistor Q6 and resistor R1.
0, R11, and R12, and the voltage at the connection point of resistors R10 and R11 is stepped down by the base-emitter voltage of transistor Q8 to obtain a first DC potential V1. On the other hand, the voltage at the connection point of resistors R11 and R12 is stepped down by the base-emitter voltage of transistor Q6 to obtain a second DC potential V2.
is obtained.

A negative polarity clamp pulse is input to the clamp pulse input terminal 13, and when this clamp pulse is high, the transistor Q5 is turned on, and the base potential of the switching transistors Q3 and Q4 becomes low, and the switching transistors Q3 and Q4 are turned on. is turned off and the input composite video signal is input to the non-inverting input terminal of the comparator 11. When the clamp pulse is low, that is, during the pedestal period of the input composite video signal, transistor Q5 is turned off and the base potential of switching transistors Q3 and Q4 is high, and these transistors Q3 and Q4 are turned on and the first DC potential V1 is charged (or discharged) to the capacitor C1, and the pedestal period of the input composite video signal is fixed to the first DC potential V1, thereby performing a pedestal clamp operation. A second reference potential V2 is applied to the inverting input terminal as a reference voltage of the comparator 11, and a portion of the input composite video signal having a lower potential than the second DC potential V2, that is, a synchronization signal, is separated and output as a negative polarity signal. obtained at terminal 2.

Resistors R10, R11, in the circuit of FIG.
When R12 is implemented as a semiconductor integrated circuit, good relative accuracy can be obtained, so the first and second DC potentials V1 and V2 can be realized with extremely high accuracy. Further, the comparator 11 has been realized as a product made into a semiconductor integrated circuit, and it is also possible to make the entire circuit into a single chip semiconductor integrated circuit.

[0016]

As explained above, the present invention is equipped with a pedestal clamp circuit, a comparator, and a reference bias circuit, thereby enabling accurate synchronization separation in the vicinity of the pedestal of a composite video signal, thereby preventing malfunctions. The effect is that it is possible to realize synchronization separation that is not possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating the operation of FIG. 1;

FIG. 3 is a circuit diagram showing a specific example of FIG. 1;

FIG. 4 is a circuit diagram of a conventional example.

[Explanation of symbols]

1 Input terminal 2 Output terminal 3 Power terminal 10 Pedestal clamp circuit 11 Comparator 12 Standard bias circuit 13 Clamp pulse terminal

Claims (1)

[Claims] 1. A pedestal clamp circuit that clamps a pedestal portion of an input composite video signal at a first DC potential; A synchronous separation circuit comprising: a comparator that applies and compares a second DC potential set to a potential on the synchronization tip side with respect to the DC potential of the second DC voltage, and outputs an output signal of the comparator in synchronous separation.