JPH07162707A - Synchronization separator circuit - Google Patents

Abstract

PURPOSE:To provide a synchronization separator circuit which is capable of always and exactly separating a synchronizing signal even when the signal amplitude of the synchronizing signal collapses in some degree. CONSTITUTION:This circuit is provided with a clamping circuit 11 where composite video signals including a video signal and a synchronizing signal are inputted and the tip level of the synchronizing signal is set to a clamp voltage, an amplifier circuit 12 amplifying the output signal of this clamp circuit by defining clamp voltage as a reference, a pedestal level detection holding circuit 13 detecting and holding the pedestal level of the output signal of this amplifier circuit, a reference voltage generation circuit 14 generating reference voltage having an arbitrary intermediate level between the pedestal level held by this pedestal level detection holding circuit and the tip level of the synchronizing signal and a voltage comparison circuit 15 comparing the output voltage of this reference voltage generation circuit and the output signal of the amplifier circuit and outputting the synchronizing signal part of the video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync separation circuit for separating a sync signal from a composite video signal, and more particularly, it is used for separating a horizontal sync signal in a television receiver, a video reproducing device and the like. It

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional horizontal sync separation circuit, and examples of its operation waveforms are shown in FIGS. 4 (a) to 4 (d). That is, the composite video signal including the video signal and the sync signal is input to the clamp circuit 11 and the sync tip level (tip level) of the horizontal sync signal is set to the clamp voltage Vs, and then the low frequency band for noise removal is set. It is amplified by the differential amplifier circuit 12 through the pass filter (LPF) 16. In this case, the clamp voltage Vs is applied as a reference voltage input to the differential amplifier circuit 12. And
The video signal output of the differential amplifier circuit 12 is input to the voltage comparison circuit 15 and compared with the reference voltage Vref2 (= Vs + ΔV1) to obtain a separated horizontal synchronizing signal as a comparison output.

Next, problems of the above-described conventional horizontal sync separation circuit will be described. FIG. 5 shows the waveform of the video signal input (amplifier circuit output) and the reference voltage V in the voltage comparison circuit 15.
The relationship with the level of ref2 (= Vs + ΔV1) is shown, and FIG. 6 shows the sync signal portion of the video signal input extracted and enlarged.

The following two points must be taken into consideration as conditions for determining the reference voltage Vref2 (= Vs + ΔV1). (1) Assuming that 1/100 of the level from the pedestal level of the video signal to the white level is represented by 1RIE, it is standard that the amplitude of the sync signal is set to 40RIE, but the change of the sync signal due to the transmission path, etc. Due to
Signal amplitude is 30% from standard value (40RIE × 0.3 = 1
There is a risk of being crushed by about 2 RIE), so you must deal with it.

(2) The reference voltage Vref2 must have a certain margin from the pedestal level. Therefore, as shown in FIG. 6, the voltage Δ from Vs to Vref2
V1 is set to a value within 12 RIE and a value obtained by subtracting the margin of the reference voltage Vref2 from the pedestal level (usually 7 to 10 RIE). That is, the reference voltage Vref2 is a voltage deviated to a considerably lower side within the sync signal amplitude (7 to 10 RI from the sync tip level).
It is set to a certain level (higher than E).

However, near the lower end of the sync signal, the L
The waveform is blunted by passing through the PF 16, and jitter is easily generated due to a slight level fluctuation of the synchronizing signal. Further, near the lower end (tip) of the sync signal, the waveform distortion and the like caused by the clamp circuit 11 is large, which also causes the jitter.

[0007]

As described above, in the conventional sync separation circuit, the lower end of the sync signal is detected to perform the sync separation, so that the jitter is easily caused by a slight level fluctuation of the sync signal. However, there is a problem that jitter occurs even when waveform distortion occurs near the lower end of the sync signal.

The present invention has been made to solve the above problems, and always synchronizes accurately even when the waveform at the lower end of the synchronizing signal is dull or waveform distortion occurs near the lower end of the synchronizing signal. An object is to provide a synchronization separation circuit that can separate signals.

[0009]

SUMMARY OF THE INVENTION A sync separation circuit of the present invention is a clamp circuit to which a composite video signal including a video signal and a sync signal is input, and which sets the leading end level of the sync signal to a clamp voltage, and the clamp circuit. An amplifier circuit that amplifies the output signal of the circuit with the clamp voltage as a reference, a pedestal level detection holding circuit that detects and holds the pedestal level of the output signal of the amplifier circuit, and a pedestal level detection holding circuit. A reference voltage generating circuit for generating a reference voltage having an intermediate level between the pedestal level and the tip level of the synchronizing signal, and comparing the output voltage of this reference voltage generating circuit with the output signal of the amplifier circuit, And a voltage comparison circuit for outputting a synchronizing signal portion of the video signal.

[0010]

Since the pedestal level detecting and holding circuit for detecting and holding the pedestal level of the output signal of the amplifier circuit is provided, even if the signal amplitude of the synchronizing signal included in the composite video signal is crushed to some extent, the pedestal is always accurate. It becomes possible to detect and hold the level.

Since the reference voltage having an arbitrary intermediate level between the detected and held pedestal level and the sync tip level of the sync signal is compared with the output signal of the amplifier circuit, the lower end of the sync signal is compared. Even if the waveform is blunted in the vicinity, a highly accurate sync signal with less jitter can be obtained by selecting an appropriate value for the reference voltage with respect to the sync signal amplitude.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows, as an embodiment of the present invention, a horizontal sync separation circuit formed in an integrated circuit used in, for example, a television receiver.

The sync separation circuit receives a composite video signal IN including a video signal and a sync signal, and the sync tip level (tip level) of the sync signal is applied to the clamp voltage source 10.
Of the clamp voltage Vs and the output signal of the clamp circuit 11 from the clamp voltage Vs.
And an amplifier circuit 12 for amplifying with reference to
Pedestal level detection holding circuit 13 for detecting and holding the pedestal level Vp of the output signal 2 and an arbitrary intermediate value between the pedestal level Vp held by the pedestal level detection holding circuit 13 and the sync tip level Vs. A reference voltage generation circuit 14 for generating a reference voltage Vref1 having a level, and a voltage comparison for comparing the output voltage of the reference voltage generation circuit 14 and the output signal of the amplifier circuit 12 and outputting the synchronizing signal portion of the video signal. And a circuit 15.

The clamp circuit 11 and the amplifier circuit 1
An LPF 16 for removing a high frequency noise component of the output signal of the clamp circuit 11 is inserted between the LPF 16 and A differential amplifier circuit is used as the amplifier circuit 12, and the clamp voltage Vs is used as a reference voltage input thereof.
Is given.

Further, the pedestal level detecting and holding circuit 13 selects the pedestal period of the output signal of the amplifier circuit 12 and extracts the pedestal level from the switch circuit 2.
1, a capacitor 22 that holds the signal extracted by the switch circuit 21, and a buffer amplifier circuit 2 that buffer-amplifies the signal held by the capacitor 22.
3 and a pedestal gate pulse generation circuit 24 for generating a pedestal gate pulse signal for turning on the switch circuit 21 during the pedestal period.

The reference voltage generating circuit 14 is composed of, for example, a resistance voltage dividing circuit connected between the output node of the buffer amplifier circuit 23 and the clamp voltage source 10. The reference voltage generating circuit 14 is, for example, a resistance element R.
Assuming that 1 and R2 are connected in series, the reference voltage Vref1 is represented by Vref1 = (Vp-Vs) * R2 / (R1 + R2).

2A to 2F show an example of operation waveforms of the horizontal sync separation circuit of FIG. The horizontal sync separation circuit of the above embodiment has the pedestal level detecting and holding circuit 13 which detects and holds the pedestal level Vp of the output signal of the amplifier circuit 12, and therefore the signal amplitude of the sync signal included in the composite video signal. It is possible to always accurately detect and hold the pedestal level Vp, even if is crushed to some extent.

Then, an arbitrary intermediate level between the detected and held pedestal level Vp and the sync tip level Vs of the sync signal is taken out as a reference voltage Vref1 and compared with the output signal of the amplifier circuit 12. Even if the waveform is blunted near the lower end of the signal, the reference voltage is selected as an appropriate value for the sync signal amplitude (a part where the sync signal is stable, for example, a position of 50% of the signal amplitude). As a result, a highly accurate synchronization signal with less jitter can be obtained.

[0019]

As described above, according to the sync separation circuit of the present invention, even if the signal amplitude of the sync signal is crushed to some extent or the waveform distortion occurs near the lower end of the sync signal, the sync separation circuit can always accurately The sync signal can be separated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a sync separation circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing an operation example of the circuit of FIG.

FIG. 3 is a block diagram showing a conventional horizontal sync separation circuit.

FIG. 4 is a waveform diagram showing the operation of the circuit of FIG.

5 is a diagram showing the relationship between the waveform of the video signal input and the level of the reference voltage Vref2 in the voltage comparison circuit in FIG.

FIG. 6 is a waveform diagram showing a sync signal portion of an output of the amplifier circuit in FIG. 5, which is taken out and enlarged.

[Explanation of symbols]

11 ... Clamp circuit, 12 ... Amplification circuit, 13 ... Pedestal level detection holding circuit, 14 ... Reference voltage generation circuit, 15
... voltage comparison circuit, 16 ... LPF, 21 ... switch circuit,
22 ... Capacitor, 23 ... Buffer amplifier circuit, 24 ... Pedestal gate pulse generation circuit, R1, R2 ... Resistor element.

Claims (2)

[Claims] 1. A clamp circuit for inputting a composite video signal including a video signal and a sync signal, and setting a tip level of the sync signal to a clamp voltage, and an output signal of the clamp circuit is amplified with the clamp voltage as a reference. Amplifier circuit, a pedestal level detection and holding circuit that detects and holds the pedestal level of the output signal of the amplifier circuit, and a pedestal level between the pedestal level held by the pedestal level detection and holding circuit and the tip level of the synchronizing signal. A reference voltage generating circuit for generating a reference voltage having an arbitrary intermediate level, and a voltage comparing circuit for comparing the output voltage of the reference voltage generating circuit and the output signal of the amplifier circuit and outputting the synchronizing signal portion of the video signal. And a circuit for providing a sync separation circuit. 2. The synchronization separation circuit according to claim 1, wherein the pedestal level detection holding circuit selects a pedestal period of an output signal of the amplifier circuit and extracts a pedestal level, and the switch circuit extracts the pedestal level. Capacitor for holding the signal, a buffer amplifier circuit for buffer-amplifying the signal held by the capacitor, and a resistor voltage divider circuit connected between the output node of the buffer amplifier circuit and the voltage source of the clamp voltage. And a sync separation circuit comprising: