JPH05183775A - Clamping device - Google Patents

Abstract

PURPOSE:To prevent the delay of synchronization pull-in owing to a fluctuation in the DC potential of a video Y signal in a step-out state. CONSTITUTION:A MUSE base band signal adding clamp information with a fixed cycle is inputted to a signal processing circuit 22 with a clamping circuit 12, a buffer circuit 16 and an A/D converter 18. The signal processing circuit 22 discriminates a phase synchronization, generates a phase synchronization discriminating signal and transmits it to a switch circuit 26. The switch circuit 26 is made to lean against the one input end 26a at the time of the synchronizing state so that the clamping circuit 12 operates normal clamping. The switch circuit 26 is made to lean against the other input end 26b at the time of the step-out state so that a bias voltage is applied to the clamping circuit 12 and the circuit executes an operation as a high-pass filter which removes the DC portion of the video Y signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp device, and more particularly to a clamp device used in, for example, a MUSE television signal receiver.

[0002]

2. Description of the Related Art Technical Report of the Television Society of Japan TBES95
-2 "Satellite 1 channel transmission system for high definition television (MU
SE) ”, a system for transmitting a high-definition television signal having a wideband image signal by one channel of satellite broadcasting has been proposed by the Japan Broadcasting Corporation as a MUSE system.

This MUSE signal is positive polarity synchronized, that is,
Since the sync signal is included in the video amplitude, it is not possible to separate the sync in the amplitude direction. Therefore, the frame synchronizing signal inserted in the vertical blanking period as shown in FIG. 4 is extracted by utilizing the correlation between the scanning lines, and then the horizontal synchronizing signal is extracted and the input television signal and the phase synchronization oscillation of the receiver are extracted. It is in phase synchronization with the circuit.

Further, since the sync separation, the phase synchronization, and various other signal processing are digitally performed, it is necessary to convert the MUSE signal into an analog / digital signal. And
When the MUSE signal is input to the A / D converter, it is necessary to clamp the DC potential so as to fix it accurately. One method for performing this clamping is to use the clamp level information (line numbers 563 and 1125) in the MUSE signal transmission format shown in FIG. 5 for the flat portion A of the horizontal synchronization signal shown in FIG. 6 and Table 1 or the horizontal synchronization signal. It is conceivable to perform at the clamp level B following the signal.

[0005]

[Table 1]

[0006]

However, in order to extract the clamp level information, frame synchronization must be established, and since the clamp pulse is generated from the phase-locked oscillation circuit, horizontal synchronization is required. Must also be established. If frame synchronization is not established,
If the clamp level information cannot be extracted and the horizontal synchronization is not established, the position that is not the proper position will be clamped. Therefore, the DC potential of the video Y signal fluctuates, which causes the sync separation circuit to malfunction.
It delays the synchronization pull-in.

Therefore, a main object of the present invention is to provide a clamp device capable of preventing a delay in pulling in synchronization even in a state of being out of synchronization.

[0008]

SUMMARY OF THE INVENTION According to the present invention, a clamp circuit for receiving a positive polarity synchronous television signal containing clamp information of a constant cycle and clamping it, and removing a direct current component of a video Y signal of the positive polarity synchronous television signal. The clamp device includes a high-pass filter circuit and switching means for activating the clamp circuit in the synchronous state and activating the high-pass filter circuit in the out-of-synchronization state according to the synchronization determination signal.

[0009]

For example, by determining the synchronization state of the phase-locked oscillating means for generating the clamp timing pulse of the clamp circuit, the synchronization determination signal indicating whether the synchronization state or the out-of-synchronization state is output. The synchronization determination signal is given to a switching means such as a switch circuit. The switching means activates the clamp circuit in the synchronized state and activates the high-pass filter circuit in the out-of-synchronized state. Thus, the DC component of the video Y signal is removed by the high-pass filter circuit in the out-of-synchronization state, the influence of the DC potential fluctuation can be prevented, the malfunction of the sync separation circuit can be eliminated, and the malfunction of the clamp can be prevented.

[0010]

According to the present invention, it is possible to prevent erroneous clamp operation when the phase is out of synchronization with a simple structure, and thus it is possible to prevent a delay in synchronization pull-in. The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a clamp device 10 of this embodiment includes a clamp circuit 12 composed of a capacitor C and a resistor R1. Then, from the input terminal 14, a positive polarity synchronous television signal including clamp information of a constant cycle, that is, M
The USE baseband signal is input, and the clamp circuit 12
And the A / D converter 18 via the buffer circuit 16
Entered in. The output from the A / D converter 18 is input to the signal processing circuit 22 and the clamp level control unit 24 which perform synchronization separation, phase synchronization oscillation, phase synchronization determination and other signal processing. In the signal processing circuit 22, a clamp timing pulse, a clamp information extraction pulse and a phase synchronization determination signal are created, the clamp timing pulse and the clamp level information extraction pulse are sent to the clamp level control unit 24, and the phase synchronization determination signal is described later. Also provided to circuit 26.

When the phase synchronization circuit is in the synchronization state, the switch circuit 26 responds to the phase synchronization determination signal by one input terminal 2
It falls to the 6a side. As a result, the clamp potential and the clamp timing or the bias potential is supplied from the clamp level control unit 24 to the output terminal of the capacitor C of the clamp circuit 12 via the resistor R1, the switch circuit 26 and the resistor R2. Then, the normal clamp operation is performed.

On the other hand, when the phase locked loop circuit is in the out-of-sync state where the phase locked loop circuit is not in the locked state, the switch circuit 26 responds to the phase locked loop decision signal and the other input terminal 26 of the switch circuit 26.
fall to the b side. As a result, the bias potential is supplied to the output terminal of the capacitor C of the clamp circuit 12 through the resistor R3, the switch circuit 26, and the resistor R1. At this time, the clamp circuit 12 operates as a high pass filter including the capacitor C and the resistors R1 and R3. Then, if the time constant of this high-pass filter is set so that the longest clock width of the frame pulse (16 clocks ≈ 1 MHz) can be passed, FIG. 2 (b) to FIG. 2 (a)
As described above, the DC component of the video Y signal is removed and the influence of the DC potential fluctuation can be prevented.

At this time, the waveform of the frame pulse is distorted as shown in FIG. 3, but there is no problem in detecting the frame pulse, and the clamp circuit 12 performs a normal clamping operation when the phase locked circuit is in the locked state. ..

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram showing how a DC component of a video Y signal is removed by a high pass filter operation.

FIG. 3 is a waveform diagram showing distortion of a frame pulse during a high pass filter operation.

FIG. 4 is a waveform diagram showing a frame pulse.

FIG. 5 is an illustrative view showing a MUSE signal transmission format.

FIG. 6 is a waveform diagram showing a horizontal synchronizing signal and a clamp position.

[Explanation of symbols]

 10 ... Clamping device 12 ... Clamp circuit 22 ... Signal processing circuit 24 ... Clamp level control unit 26 ... Switch circuit

Claims (1)

[Claims] 1. A clamp circuit for receiving a positive-polarity synchronous television signal containing clamp information of a constant cycle and clamping it, a high-pass filter circuit for removing a DC component of a video Y signal of the positive-polarity synchronous television signal, and synchronization discrimination. A clamp device comprising switching means for activating the clamp circuit in a synchronous state and activating the high-pass filter circuit in a non-synchronous state in response to a signal.