JPS6114229Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical synchronization signal detection circuit suitable for use in a ghost removal device.

One example and another example of an apparatus for removing ghosts in a video stage are shown in FIGS. 1 and 2, respectively.
The ghost removal device shown in FIG. 1 uses a transversal filter to realize the ghost transfer function in the video stage after synchronous detection. A video signal including a ghost is supplied to an input terminal indicated by 1 and is supplied to a synthesizer 2.
A cancellation signal simulated by a ghost is supplied from the transversal filter to the synthesizer 2, and a video signal with the ghost canceled is obtained as an output of the synthesizer 2, and is taken out to an output terminal 3. The video signal appearing at the output of this synthesizer 2 is transmitted to the delay circuit 4.
supplied to In the delay circuit 4, a plurality of delay elements each having a sampling period as a unit are connected, and taps are derived from between each stage. The output of each tap of the delay circuit 4 is supplied to a weighting coefficient circuit 5 configured as a multiplier, so that the weighting coefficients are weighted, and all outputs are supplied to an adder 6, and the output of this adder 6 is A cancellation signal is generated.

The weighting factors for the weighting factor circuit 5 described above are generated from an analog accumulator 7. The ghost component is detected by supplying the signal appearing at the output terminal 3 to the detection circuit 8. As a signal for detection and measurement, a signal included in a standard television signal and not affected by other signals for as long as possible, such as a vertical synchronization signal, is used. As shown in Figure 3, weighting is performed to give proportional weighting based on the waveform that characterizes the leading edge VE of the vertical synchronization signal and the subsequent 1/2H (H is the horizontal section). Coefficients are formed. For example, the phase difference with the video signal φ (=ω _c γ, where ω _c
When a ghost of 45 degrees (video carrier angular frequency at the high frequency stage) is included, a video signal having a waveform as shown in FIG. 4A is obtained by synchronous detection.
This signal is separated and the polarity is inverted to produce a fourth signal.
The characteristic waveform shown in Figure B is generated. This characteristic waveform is
Since it can be approximately regarded as an impulse response of a ghost, a weighting coefficient proportional to this characteristic waveform is formed. Therefore, the signal of the characteristic waveform appearing from the detection circuit 8 is supplied to the demultiplexer 9. Similar to the delay circuit 4, the demultiplexer 9 is constructed by connecting multiple stages of delay elements each having a sampling period as a unit, and taps are derived from between each stage, and the output of each tap is supplied to the accumulator 7. Ru.

As mentioned above, the delay circuit 4 and the weighting coefficient circuit 5
By inserting a transversal filter composed of the adder 6 and the adder 6 into the feedback loop, an inverse filter is constructed and ghosts can be removed. In this case, after detecting the leading edge of a certain vertical synchronization signal and the waveform distortion in the 1/2H section before and after it and determining the weighting coefficient, if ghosts remain unerased, perform the above-mentioned detection and eliminate them. An analog accumulator 7 is provided to reduce the remainder.

The ghost removal device shown in FIG. 2 is an example in which a ghost is divided into an in-phase component and a quadrature component, the levels of each component are detected, and a cancellation signal is formed by this detection. That is, the output signal of the synthesizer 2 is supplied to a delay circuit 10 having taps, a delayed video signal is extracted from the tap selected by the switching means 11, and this is supplied to the in-phase and quadrature component generation circuit 12. Ru. on the other hand,
The detection circuit 13 detects the in-phase and quadrature components of the ghost from the waveform distortion in the H/2 section from the leading edge VE of the vertical synchronization signal as shown in FIG. 4A, and each detection output is converted into an analog cumulative signal. Calculator 14I, 14
Q is supplied.

The in-phase and quadrature component generation circuit 12 can be formed by using the original signal as it is as the in-phase component.
The orthogonal components can be formed by a transversal filter or a distribution circuit, and these in-phase and orthogonal components are formed by multipliers 15I and 15, respectively.
Q is supplied. The outputs of accumulators 14I and 14Q are supplied as weighting coefficients to multipliers 15I and 15Q, and each output of multipliers 15I and 15Q is supplied to an adder 16, and a cancellation signal is obtained from the output of this adder 16. be able to.

The ghost removal device shown in FIG. 2 is applied to remove a single ghost, and the switching means 11 is manually switched. The tap of the delay circuit 10 is selected using the switching means 11 while viewing the received image in which a ghost has occurred. The sum of the delay amount determined by the tap selected to minimize the ghost and the time delay generated in the in-phase and quadrature component generating circuit 12 becomes the ghost delay with respect to the desired signal.
Even when removing ghosts by dividing into in-phase components and quadrature components, analog accumulators 14I and 14Q are provided as in the case of FIG.
Through repeated control operations, the number of unerased ghosts is reduced as much as possible.

As can be understood from the above explanation, the ghost removal device uses the H/2 interval from the leading edge VE of the vertical synchronization signal as the detection interval, so in order to form the cancellation signal, this leading edge VE must be It is necessary to detect with high accuracy. For example, in the ghost removal device shown in FIG. need to be given to In order to define the timing of this gate, the leading edge of the vertical synchronization signal must be accurately detected. In addition, in the ghost removal device shown in FIG. 2, the leading edge of the vertical synchronization signal is accurately detected in order to generate sampling pulses for level detection to detect the in-phase and quadrature components of the ghost in the detection circuit 13. Must.

By the way, the vertical synchronization separation circuit used in conventional television receivers etc. is configured to separate the amplitude of the synchronization signal from the video signal, supply this synchronization signal to an integrator, and determine the level of the output of the integrator. Ta. With such a configuration, the leading edge of the separated vertical synchronization signal typically lags the leading edge of the video signal by some amount due to the slope of the rise of the integrator.

The present invention takes this point into consideration and aims to realize a vertical synchronization signal detection circuit that can form a detection pulse whose phase matches the leading edge of a vertical synchronization signal in a video signal.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 5 shows the overall configuration of this embodiment, and the video signal S ₁ is supplied to the input terminal 17. This video signal appears at the output side of the synthesizer 2 in the ghost removal apparatus having the configuration shown in FIG. 1, and appears at the output side of the switching means 11 in the ghost removal apparatus having the configuration shown in FIG. .
18 indicates a horizontal sync separation circuit, 19 indicates a vertical sync separation circuit, and both sync separation circuits 18 and 19
A video signal is supplied to the The horizontal synchronization separation circuit 18 is configured to supply the video signal via a clamp circuit to an integrating circuit with a short time constant, and to shape the output of this integrating circuit into a waveform. A synchronization signal Sh appears. The vertical synchronization separation circuit 19 is configured to supply the video signal via a clamp circuit to an integration circuit with a long time constant, and to compare the output of this integration circuit with a reference voltage. signal
Sv is supplied.

As an example, as shown in FIG. 6A, after a 3H equivalent pulse period EQ _1, a 3H vertical synchronization signal period
When a video signal S ₁ in which VD is located and an equivalent pulse period EQ ₂ of 3H is located thereafter is supplied to the input terminal 17, the output voltage Sv' of the vertical synchronization separation circuit 19 is as shown in FIG. It will be as shown below. During the vertical synchronization signal period VD, the output voltage Sv' exceeds the reference voltage, and a vertical synchronization signal Sv that rises at this timing is generated. This vertical synchronization signal
The rising edge of Sv triggers the monostable multivibrator 20, which generates the output pulse _S2 shown in FIG. 6C. A monostable multivibrator 21 is provided which is triggered by the rising edge of this output pulse _S2 . The delay time of the monostable multivibrator 21 is (1V-H/2) (where V is the vertical period), so its output pulse _S3 is:
As shown in FIG. 6D, the level is low in the interval (To=1V-H/2), and the level is high in the interval (T ₁ =H/2).

The output pulse S ₃ of the monostable multivibrator 20 is supplied to the ant gate 22, and the ant gate 22 is also supplied with the horizontal synchronization signal Sh shown in FIG. 6E from the horizontal synchronization separation circuit 18. Therefore, the leading edge VE of the vertical synchronization signal in the rising video signal _S1 is applied to the output terminal 23 of the AND gate 22.
It is possible to obtain a detection pulse _S4 whose phase matches that of .

The configuration of the monostable multivibrator 21 described above is shown in FIG. Similar to a normal monostable multivibrator, the emitters of a pair of NPN transistors 24a and 24b are grounded, and the transistor 24
The collector of b is led out as the output terminal 25.
In addition, the collectors of the transistors 24a and 25b are connected to the power supply voltage (+
Vcc), the collector of the transistor 24a is connected to the base of the transistor 24b via a resistor 28, and the collector of the transistor 24b is connected to the power supply terminal 27 via a capacitor 29 and a resistor 30. The connection point between the capacitor 29 and the resistor 30 is connected to the base of the transistor 24a. The output pulse S ₂ of the monostable multivibrator 20 in the previous stage is supplied to the trigger terminal 31, divided by the capacitor 32 and resistor 33, and the positive divided pulse is sent to the base of the transistor 24b via the diode 34. supplied to

The collector of transistor 24b is grounded via resistors 35 and 36, and the connection point between both resistors is connected to the base of transistor 37. The emitter of this transistor 37 is grounded via an emitter resistor 38, and its collector, collector resistor 3
9 and a capacitor 40, and the collector of transistor 37 is connected to the base of transistor 24a through a large value feedback resistor 41. The gain of the transistor 37 is approximately determined by the ratio of the sizes of the emitter resistor 38 and the collector resistor 39, and this gain is selected to be sufficiently large, such as 1000 times.

In the monostable multivibrator 21 having the above configuration, the collector output voltage of the transistor 24a is _S3 , the base voltage of the transistor 24a is _S5 ,
Control voltage S ₆ generated at the collector of transistor 37
shall be. When the pulse _S2 shown in FIG. 8A is applied to the trigger terminal 31, the transistor 24b turns on at the rising edge of this pulse _S2 , its collector is grounded, and the output pulse _S3 becomes O as shown in FIG. 8C.
It becomes [V]. On the other hand, the base potential S ₅ of the transistor 24a becomes negative as shown in FIG. 8D, and it is turned off, and its collector output voltage S ₃ rises to the power supply voltage Vcc as shown in FIG. 8B. Power supply voltage 2
7 through the resistor 30 and the transistor 3
The capacitor 29 is charged by the circuit from the collector of the transistor 7 to the resistor 41, and the transistor 2
The base potential _S5 of the transistor 4a gradually rises, and after a delay time To from the leading edge of the pulse _S2 , the transistor 24
a turns on. The base potential _S5 at this time is equal to the base-emitter voltage drop of the transistor 24a. When transistor 24a turns on, transistor 24b turns off and output pulses _S3 and _S3
level is reversed. It is triggered again by a pulse S ₂ applied after the next period T ₁ and the above-described operation is repeated. The values of the resistor 30 and the capacitor 29 are selected so that the delay time To of the monostable multivibrator 21 is approximately (1V-H/2).

While the output pulse S ₃ is at a high level, the transistor 37 is turned on, and the charge in the capacitor 40 is discharged through the transistor 37 and the resistor 38 . On the other hand, during the period when the output pulse _S3 is at a low level, the transistor 37 is off, so the capacitor 4
0 is charged by the current flowing from the power supply terminal 27 through the resistor 39. In this case, since the gain of the transistor 37 is large, the discharging current becomes larger than the charging current. Since the value of resistor 39 is sufficiently larger than resistor 38, it may be considered that the charging time constant is considerably longer than the discharging time constant. Therefore, as shown in FIG. 8E, the control voltage _S6 generated at the collector of the transistor 37 is a nearly constant voltage during the delay time To, and the level changes rapidly during the period _T1 . Become something to do. In Figure 8, the period of T ₁ is shown to be relatively long, but
(To=(1V-H/2)=262H) ( _T1 =0.5H), which is the length ratio of ( _T1 /To=0.019).

In the monostable multivibrator 21 configured as described above, the value of the capacitor 29 or resistor 30 may fluctuate due to temperature changes, or due to fluctuations in the power supply voltage Vcc, as shown by the broken lines in FIG. 8B and C. , period T ₁ is longer than H/2. If such an output pulse _S3 is used, there is a risk that the equivalent pulse before the vertical synchronization signal will be extracted.
However, according to the configuration of the above-mentioned embodiment, the eighth
As shown by the dashed line in diagram E, the drop in the level of the control voltage S ₆ becomes greater and therefore the next period
The level of control voltage S ₆ at T ₁ becomes small. Since this control voltage S ₆ is fed back to the base of the transistor 24a, when it becomes smaller, the slope of the rise in the base voltage S ₅ becomes gentler. In this way, the period T ₁ is controlled to become shorter,
The period _T1 is set to be H/2.

To further explain the stabilization of the delay time To according to the embodiment of the present invention described above, the relationship between the control voltage _S6 and the period _T1 can be expressed as shown in FIG. 9A. (T ₁ = O), that is, when the delay time To exceeds one vertical period, (S ₆ = +Vcc), and when (T ₁ = H), (S ₆ = 0),
(T ₁ =H/2) That is, in the normal case, the control voltage S ₆ becomes the reference value S ₆₀ . On the other hand, control voltage S ₆ and delay time To
As is clear from the above explanation, the relationship between the delay time To and the delay time To becomes as shown in FIG. 9B, in which the smaller the control voltage _S6 becomes, the longer the delay time To becomes. And when the control voltage S ₆ is equal to the reference value S ₆₀ , (To = (1V
−H/2), T ₁ =H/2). Therefore, if the factors determining the delay time To of the monostable multivibrator fluctuate due to temperature changes, aging, etc., feedback control is performed to cancel out this fluctuation. The loop gain of this feedback control is the product of the slopes of the straight lines shown in FIG. 9A and B. In reality, the feedback path from the collector of the transistor 37 to the base of the transistor 24a is left open, and a DC voltage equal to the reference voltage S ₆₀ is applied to the base of the transistor 24a via the resistor 41, and in this state (To= (1V-H/2), T ₁ =H/2), and then a return path may be formed and used.

As is clear from the above description of the embodiment, according to the present invention, it is possible to form a pulse that extracts the leading edge of the vertical synchronization signal with high accuracy by using only one monostable multivibrator. Unlike the present invention, sampling pulses can be formed with high accuracy by counting the output of the reference oscillator with a counter, but in this case, the configuration has the disadvantage of being expensive and complicated. In addition, there is no problem even if the synchronization signal cannot be separated in a section other than the vicinity of the leading edge of the vertical synchronization signal due to ghost or other noise, and the noise resistance is excellent.

Note that, unlike the above embodiment, the resistor 30 may be configured as a variable impedance element, and its value may be controlled by the control voltage _S6 .

[Brief explanation of the drawing]

1 and 2 are block diagrams of one example and another example of a ghost removal device to which the present invention can be applied;
4 and 4 are waveform diagrams used to explain the ghost removal device, FIG. 5 is a block diagram of an embodiment of the present invention, and FIG. 6 is a waveform diagram of each part used to explain its operation.
FIG. 7 is a connection diagram of essential parts of an embodiment of the present invention, and FIGS. 8 and 9 are schematic diagrams used to explain its operation. 17 is an input terminal, 18 is a horizontal synchronization separation circuit, 1
9 is a vertical synchronization separation circuit, 20 and 21 are monostable multivibrators, and 23 is an output terminal.

Claims (1)

[Claims for Utility Model Registration] It has a synchronization separation circuit that separates the vertical synchronization signal from the video signal and a time constant circuit, and the delay time is approximately (1V-H/2) (1V is one vertical period, 1H is a monostable multivibrator in which the time constant of the above-mentioned time constant circuit is selected so that the time constant is 1 horizontal period), and a control voltage of a level corresponding to the pulse width of approximately H/2 generated from this monostable multivibrator. triggering the monostable multivibrator at the leading edge of the vertical synchronization signal separated by the synchronization separation circuit, and feeding back the control voltage to the time constant circuit of the monostable multivibrator to A vertical synchronization signal detection circuit which makes the delay time of the monostable multivibrator constant and extracts the leading edge of the vertical synchronization signal in the video signal by the output of the monostable multivibrator.