JPH0342778Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ghost detection device that is applied to remove ghosts that are a problem when receiving television signals.

A method for removing ghosts in the video stage is to detect the level of the in-phase component or quadrature component of the ghost, and use this detection output to form a cancellation signal that is simulated as a ghost, and to remove the ghost from the video signal containing the ghost. There are some that synthesize signals. Another method is to simulate the ghost transfer function using a transversal filter to form a cancellation signal. In either method, it is necessary to detect ghosts from a constant waveform that is included in standard television signals and is independent of the video signal. Usually, as shown in FIG. 1A, the detection period is often an H/2 period up to the equalization pulse after (and before) the leading edge VE of the vertical synchronizing signal.

The waveform of the ghost varies depending on the phase difference between the desired signal and the unnecessary signal at the high frequency stage. When the delay time of the unnecessary signal with respect to the desired signal is τ, and the image carrier angle wave number at the high frequency stage is ωc,
(=ωcτ). As an example, a waveform including a ghost (=180°) and a considerably small delay time τ is shown in FIG. 1B.

By the way, when receiving television signals,
As shown in Figure 2A, if large pulse noise Sn is included on the negative (black) side of the synchronization signal, this noise Sn disturbs the synchronization system, causing screen distortion and peak AGC. In some cases, the operation of AGC is disturbed. To prevent this, the second
The tip level Et of the synchronization signal indicated by the broken line in the figure
The detection level is set to a slightly more negative side, and when noise Sn larger than this detection level is mixed in, ANC (automatic noise removal) operates to reduce the level of noise Sn to the tip level Et, as shown in Figure 2B. ) circuit is provided. Therefore, as shown in Figure 1B, if the delay time τ is small and there is a ghost that appears as a negative direction pulse at the leading edge VE of the vertical synchronization signal, the above-mentioned ANC circuit will treat this as noise. It was judged that
The waveform is converted to the one shown in Figure C. Therefore, in reality, there is a drawback that the waveform may have no ghost even though there is a ghost, or the waveform may be distorted, and erroneous ghost information different from the actual one may be detected.

Further, an AGC circuit is provided in association with the tuner's RF amplifier and video intermediate frequency amplifier.
Since the AGC circuit operates to keep the level of the leading edge of the synchronization signal constant, this AGC operation also transforms the waveform of the video signal into something different from the actual one.

In view of the above-mentioned points, the present invention provides that, in the section including the leading edge of the vertical synchronization signal where ghost detection is performed,
The ANC operation of the ANC circuit is disabled.

FIG. 3 shows the basic configuration of an embodiment of the present invention. In the figure, 1 is a tuner, 2 is a video intermediate frequency amplifier, 3 is a synchronous detection circuit, and 4 is a synchronous detection circuit.
This is an ANC circuit. The video signal from the ANC circuit 4 is supplied to the ghost removal circuit 5, and
The voltage is supplied to an AGC circuit 6, from which an AGC voltage is generated for the RF amplifier and video intermediate wave amplifier 2 of the tuner 1. At the output terminal 7 of the ghost removal circuit 5, a video signal from which the ghost has been removed appears. This video signal is supplied to a control signal generation circuit 8, which generates a control signal Ps. This control signal Ps disables the operation of the ANC circuit 4 and switches the time constant of the AGC circuit 6, so that during the ghost detection period, the AGC circuit 4 is disabled.
The time constant of the circuit 6 is assumed to be large.

FIG. 4 shows a detailed configuration of an embodiment of the present invention. The ghost removal circuit 5 of this example is designed to remove ghosts with a simple configuration, taking into account that most actual ghosts are one delayed ghost. In other words, the levels of the in-phase and quadrature components of the ghost change depending on the difference in reception channels (that is, the difference in ωc), but when the ghost is transmitted from one location, the delay time τ of the ghost remains constant. be. Therefore, the delay time τ is determined and the levels of the in-phase component and quadrature component are controlled to form a cancellation signal.

The leading edge of the vertical synchronization signal is used to detect the levels (including polarity) of the in-phase and quadrature components. FIG. 5 shows the waveform near the leading edge of the vertical synchronization signal according to the phase difference between the desired signal and the ghost at the high frequency stage. In the case of (=0°), there is a ghost with only the in-phase component and the same polarity, and in the case of (=180°), there is only the in-phase component with the opposite polarity, and similarly, in the case of (=90゜)
and (=270°), only orthogonal components exist. Taking into consideration the peculiarities of such waveforms, the level of the video signal is determined at at least three points: a first position determined by the ghost delay time τ with respect to the desired signal, and second and third positions before and after the first position determined by the ghost delay time τ. Detect. Figure 6 shows an example (
= 225°), the first position X ₁ and the second position X ₂
and a third position X ₃ respectively. Assuming that the detection levels at each position are V ₁ , V _{2 ,} and V ₃ , the detection signal _VI obtained by the calculation of (V ₂ − V ₃ ) corresponds to the level and polarity of the in-phase component of the ghost, and is expressed as (V The detection signal V _Q obtained by the calculation of ₂ - V ₁ ) corresponds to the level and polarity of the orthogonal component if the ghost of the in-phase component is removed.

Therefore, an in-phase component and a quadrature component are formed for the video signal delayed by τ, and the levels and polarities of the in-phase component and quadrature component are weighted in proportion to the above-mentioned detection signals V _I and V _Q. ,
Thereafter, the ghost can be canceled by adding the two and combining the output of this addition, that is, the cancellation signal, with the video signal.

In Figure 4, the synthesizer indicated by 9 has an ANC
A video signal Sd obtained from the circuit 4 is supplied,
The synthesizer 9 combines the signal with the cancellation signal. The output S ₁ of this synthesizer 9 is taken out to the output terminal 7. A cathode ray tube (not shown) is connected to the output terminal 7 via a video amplifier or the like, as in a normal television receiver. Further, the output of the synthesizer 9 is supplied to a delay circuit 11. The delay circuit 11 can be realized using a delay line, a charge transfer element, etc., and includes a plurality of delay lines such that the difference in delay amount between the i-th tap and the (i+1) or (i-1)th tap is equal. Taps have been derived. One of the plurality of taps is selected by the switching means 12, and the video signal _S2 appearing at the selected tap is supplied to the in-phase and quadrature component generating circuit 13. The in-phase component is multiplier 1
4I, the orthogonal component is supplied to multiplier 14Q, and the outputs of multipliers 14I and 14Q are supplied to adder 1
5, and a cancellation signal _S3 is generated at the output of this adder 15.

The output of the synthesizer 9 is applied to an in-phase and quadrature component detection circuit 16, which is shown surrounded by a broken line. This detection circuit 16 includes sampling and holding circuits 17, 18, and 19 to which the output of the synthesizer 9 is supplied, and output voltages V1 and _V1 of the sampling and holding circuits 17 and 18.
A synthesizer 20Q is supplied with V ₂ and generates a detection output of (V ₂ −V ₁ =V _Q ), and output voltages V ₂ and V ₃ of sampling and hold circuits 18 and 19 are supplied,
A synthesizer 20 that generates a detection output of (V ₂ −V ₃ =V _I )
I and the outputs V _Q and V _I of combiners 20Q and 20I
Analog accumulators 21Q and 21I that cumulatively add
It is equipped with The output of accumulator 21I is supplied to multiplier 14I as a multiplication coefficient, and the output of accumulator 21Q is supplied to multiplier 14Q as a multiplication coefficient. This makes it possible to form cancellation signals corresponding to the in-phase and quadrature components of the ghost, respectively.

sampling hold circuit 17 of the detection circuit 6;
Sampling pulses for each of 18 and 19
P ₁ , P ₂ , and P ₃ are formed by a sampling pulse generation circuit 22 shown surrounded by a broken line. The sampling pulse generation circuit 22 can generate the sampling pulse P ₁ at a position corresponding to the ghost delay time τ. The video signal S2 appearing at the tap of the delay circuit 11 selected by the switching means ₁₂ is supplied to the leading edge detection circuit 23 of the vertical synchronizing signal, and a detection pulse Pv that rises at the position of the leading edge is generated at its output. . Since the leading edge of the sync-separated vertical synchronizing signal generally lags slightly behind that in the input video signal, the leading edge detection circuit 23 forms a detection pulse Pv that coincides with that in the video signal. From this detection pulse Pv, monostable multivibrator 2
4, 25, 26, 27, and 28 form sampling pulses P ₁ , P ₂ , and P ₃ . Monostable multivibrators 24, 25 are for defining the positions of sampling pulses _P1 and _P3 ,
The monostable multivibrators 26, 27, 28 are
This is to define the pulse width of sampling pulses P ₁ , P ₂ and P ₃ . The position of the leading edge of each sampling pulse is the detection position in Figure 6.
Corresponds to X ₁ , X ₂ , and X ₃ .

The in-phase and quadrature component generation circuit 13 is configured to generate orthogonal components using a transversal filter or a differentiating circuit, and also to generate an in-phase component via a delay circuit that corrects the delay time caused by these components. The delay time caused by the in-phase and quadrature component generating circuit 13 in this way is assumed to be τ ₂ .

A monostable multivibrator 29 is also provided which is triggered by the output of the leading edge detection circuit 23 and generates a control signal Ps. This control signal Ps is supplied to the ANC circuit 4 and the AGC circuit 6, and the operation of the ANC circuit 4 is prohibited only during the high level period of the control signal Ps, and the time constant of the AGC circuit 6 is switched to a longer one.

FIG. 7 shows an example of the leading edge detection circuit 23. A video signal S ₂ is supplied to an input terminal indicated by 30 in FIG. 7, and this video signal S ₂ is supplied to a vertical sync separation circuit 31 and a horizontal sync separation circuit 32. The video signal S ₂ is what appears at the output of the switching means 12. The vertical synchronization separation circuit 31 has an integrator with a long time constant, and the horizontal synchronization separation circuit 32
has an integrator with a short time constant, and both are
In both cases, a clamp circuit is provided before the integrator to perform APL.
(average video signal level). When the level of a ghost, especially a ghost of an opposite phase, is high, the video carrier wave becomes small, making it difficult to detect a horizontal synchronizing signal, and in some cases, a horizontal synchronizing signal is dropped. In order to prevent this, if the integration time constant is shortened, the vertical synchronization signal cannot be detected accurately due to the presence of the equalization pulse. Therefore, two separate sync separation circuits, a vertical sync separation circuit 31 and a horizontal sync separation circuit 32, are provided.

As shown in Figure 8A, it consists of equalized pulses.
A video signal S 2 in which a 3H vertical synchronizing signal period VD is located after a 3H equalization pulse period EQ ₁ , and _a 3H equalization pulse period EQ ₂ is located further after that is input to the input terminal 3.
0, the output Sv' of the integrator of the vertical synchronization separation circuit 31 becomes as shown in FIG. 8B. In other words, for the horizontal synchronization signal or equalization pulse,
Because the time constant is large, the level of the integrator output Sv′ does not reach the reference level, and the vertical synchronization signal period
At VD, the integrator output Sv' reaches the reference level, and a vertical synchronization signal that rises at this timing is generated. The monostable multivibrator 33 is triggered by the rise of this vertical synchronization signal, and as shown in FIG.
A pulse _P4 shown in is generated. The monostable multivibrator 34 is triggered by the rise of this pulse _P4 , and the reset pulse shown in FIG.
_P5 occurs. The time constant of the monostable multivibrator 33 is selected so that the pulse width of its output pulse _P4 is slightly longer than the vertical synchronization signal period VD, and the noise contained in the vertical synchronization signal period VD prevents the monostable multivibrator from becoming monostable. Multivibrator 34 is prevented from being triggered.

This reset pulse _P5 is supplied to the counter 35. The counter 35 counts the output of the reference oscillator 36 at a sufficiently higher frequency (200 [kHz] to 1 [MHz]) than the horizontal frequency. As the reference oscillator 36, for example, a crystal oscillator can be used.
At the rising edge of the reset pulse _P5 mentioned above, counter 3
5 is reset, and the output pulse _P6 shown in FIG. 8E is generated from the counter 35 after a period of approximately (1V-1H) (where 1V is one vertical period). Further, the horizontal synchronization signal Sh (including the equalization pulse) is separated from the horizontal synchronization separation circuit 32 as shown in FIG. 8F, and this horizontal synchronization signal Sh and the output pulse _P6 of the counter 35 are The signal is supplied to the AND gate 37. Therefore, the output terminal 38 of the AND gate 37
As shown in FIG. 8G, a detection pulse Pv whose rise coincides with the leading edge VE of the vertical synchronizing signal of the next field is obtained.

Further, by triggering the monostable multivibrator 29 at the leading edge of the output pulse _P6 of the counter 35, a control signal Ps shown in FIG. 8H is generated at the output terminal 39. This control signal Ps is
It becomes high level during the period from approximately H/2 before the leading edge VE of the vertical synchronizing signal to the next equalization pulse.
The control signal Ps may have a pulse width wider than that shown in the figure so that its fall is delayed.

FIG. 9 shows the configuration of the AGC circuit 6. In the figure, a constant current source indicated by 40 generates a constant current at a level corresponding to the leading edge level of the synchronization signal, and this is transmitted to the loop filter 41 indicated by a broken line. is supplied to The time constant of the loop filter 41 is determined by the resistor 42.
and a capacitor 43, and the AGC voltage is taken out at its output terminal 44. A series circuit of a capacitor 45 and a discharge resistor 46 is inserted between the output terminal 44 of the loop filter 41 and the ground, and the connection point between the two is connected to the collector of an NPN transistor 47. The emitter of this transistor 47 is grounded, and the aforementioned control signal is connected to a terminal 48 derived from its base.
Ps is supplied. Therefore, when the transistor 47 is turned on while the control signal Ps is at a high level, the capacitor 45 is connected in parallel to the capacitor 43, and the time constant becomes large. Control signal
When the transistor 47 is off during the period when Ps is at a low level, the value of the resistor 46 is large, so the loop filter 41 has the original time constant. In addition, the loop filter 41 part is
Even if the circuit is implemented as an IC, it is an external configuration, so the capacitor 45, resistor 46,
Adding transistor 47 is easy.

In addition to switching the time constant of the AGC circuit to a larger one, the operation of the AGC circuit may be disabled. For example, a configuration may be considered in which a predetermined DC voltage is used instead of the AGC voltage during a period when the control signal Ps is at a high level.

FIG. 10 shows a configuration of an example of a specific connection of the ANC circuit 4. A video signal from the synchronous detection circuit 3 is supplied to an input terminal 49 and applied to the base of a transistor 50. The transistor 50 has an emitter follower type structure having emitter resistors 51 and 52 connected in series, and a connection point between the resistors 51 and 52 is connected to the base of an emitter follower type transistor 53 having an emitter resistor 54. The emitter of this transistor 53 is connected to the base of a transistor 55, and the emitter of the transistor 55 is grounded via a constant current source 56 and led out as an output terminal 57. This input terminal 49
The path from there to the output terminal 57 via transistors 50, 53, and 55 is the main video signal transmission path.

Further, the emitter of the transistor 50 is connected to the base of one transistor 59 of the differential amplifier 58, and the base of the other transistor 60 is connected to the connection point between the resistor 61 and the capacitor 62. This connection point is connected to a diode 63 and a resistor 64.
It is connected to the emitter of transistor 53 via. The collector of this transistor 60 is connected to the base of a PNP transistor 65. A series circuit of resistors 66, 67, and 68 is inserted between the power supply terminal (+Vcc) and ground, and the collector-emitter path of transistor 65 is inserted in parallel with resistor 66. The connection point between the resistors 67 and 68 is connected to the base of the transistor 69 and the collector of the transistor 70, the emitter of the transistor 70 is grounded, and a control signal is sent to the terminal 71 connected to the base.
Ps is supplied. The collector-emitter path of transistor 69 is parallel to that of transistor 55.

The capacitor 62 described above is charged through the resistor 61 and discharged through the diode 63 and resistors 64 and 54. If the value of the resistor 61 is R ₁ , and the combined value of the resistors 64 and 54 is R ₂ , then (R ₁ ≫ _{R 2} )
is selected. Further, assuming that the capacitor 62 is C, the discharging time constant R ₂ C is sufficiently larger than the pulse width of the vertical synchronization signal (for example, 10 [ms]), and the charging time constant R ₁ C is even larger than this. (e.g. 560
[ms]). An input video signal appears at the emitter of the transistor 50 (point A), and a video signal of a low level corresponding to the voltage drop across the resistor 51 appears at the base of the transistor 53 (point B). By selecting the time constant as described above, the potential at the connection point (point C) between the resistor 61 and the capacitor 62 becomes equal to the leading edge level of the synchronizing signal in the video signal at point B. Due to the voltage drop across resistor 51, transistor 59 of differential amplifier 58 is turned on and transistor 60 is turned off, so transistor 65 is also turned off. Therefore, a voltage of (Vcc×r ₃ /r ₁ +r ₂ +r ₃ ) is applied to the base of the transistor 69 (point E). r ₁ , r ₂ , r ₃ are resistances 6
The values are 6, 67, and 68. r ₁ to _{r 3} are selected so that the potential at point E is lower than the potential at the emitter (point D) of transistor 53, so transistor 69 is turned off. This is normal operation.

Note that the transistor 70 is turned off outside the ghost detection section.

Then, when the pulse-like negative noise Sn contained in the video signal is supplied, the potential at point A becomes lower than the potential at point C because the discharge time constant of the capacitor 62 is large, and the differential amplifier The transistor 59 of 58 is turned off and the transistor 60 is turned on. This turns on the transistor 65, bypasses the resistor 66, and the potential at point E becomes (Vcc×
r ₃ / r ₂ + r ₃ ). This voltage setting is such that when the transistor 69 is on, the emitter voltage of the transistor 69 is higher toward the white side than the level of the tip of the synchronizing signal appearing at the output terminal 57 when the transistor 69 is off. This prevents the noise Sn from becoming larger on the black side than the level of the leading edge of the synchronizing signal.

Further, when the control signal Ps becomes high level in the ghost detection section, the transistor 70 is turned on, so the transistor 69 is forcibly turned off, and the above-described ANC operation is prohibited.

In the embodiment of the present invention described above, the operation when a video signal Sd including a ghost is supplied from the synchronous detection circuit 3 as shown in FIG. 11A will be described. First, the user operates the switching means 12 while viewing the received video, and selects the tap of the delay circuit 11 that minimizes ghosts. In this state, the video signal _S1 from which the ghost has been removed is output to the output terminal 7, as shown by the dashed line in FIG. 11B. Also, a video signal S ₂ having a delay time τ ₁ obtained by subtracting the delay time τ 2 generated in the in-phase and quadrature component generation circuit 13 from the ghost delay time τ (shown by _a solid line in FIG. 11B)
is taken out from the delay circuit 11. Therefore, the leading edge detection circuit 23 generates a detection pulse Pv shown in FIG. 11C, which rises at a timing coinciding with the position of the leading edge of the vertical synchronizing signal of the video signal _S2 . The rising edge of this detection pulse Pv triggers the monostable multivibrators 24 and 26, and the monostable multivibrator 26 generates a sampling pulse _P2 . Furthermore, by making the delay time of the monostable multivibrator 24 equal to τ ₂ , the sampling pulse P ₁ can be generated from the monostable multivibrator 27 triggered by its output. Furthermore, the sampling pulse
Sampling pulse _P3 can be generated at a position later than _P1 . These sampling pulses P ₁ , P ₂ and P ₃ are shown in FIG. 11D.

In this way, the sampling pulse generation circuit 22
Since the sampling pulse is formed from the video signal _S2 appearing at the tap of the selection circuit 11 selected by the switching means 12, the sampling pulse corresponding to the ghost delay time τ can be automatically generated.

_{From the} multiplier _14I as shown _{in FIG .} An in-phase component S _I shown in E is generated, and a quadrature component S _Q shown in FIG. 11F is generated from the multiplier 14Q by the cumulative output of the detection signal V _Q (=V ₂ -V ₁ ). Therefore, from the adder 15 the first
The canceling signal S ₃ (=S _I +S _Q ) shown in Figure 1G is generated,
The ghost is canceled by combining it with the video signal shown in FIG. 11A in the combiner 9.

As understood from the description of one embodiment above,
According to the present invention, in the ghost detection section,
Since the ANC operation of the ANC circuit is disabled, it is possible to prevent the waveform of the detection section from differing from the original waveform as explained at the beginning, and therefore it is possible to accurately detect ghosts.

FIG. 12 shows another embodiment of the invention. In this example, the ghost removal circuit 5 is configured to simulate a ghost using a transversal filter and form a cancellation signal. That is, the video signal appearing at the output of the synthesizer 9
S ₁ is supplied to delay circuit 72 . Delay circuit 72
is equipped with n (for example, 256) taps at intervals of sampling period Δτ (for example, 100 [ns]),
The output of each tap is supplied to multipliers 73 ₁ to 73 _o , and the outputs of the multipliers 73 ₁ to 73 _o are supplied to adder 74, which generates a cancellation signal S ₃ . Further, the video signal appearing at the output of the synthesizer 9 is supplied to a differentiating circuit 75, and its differentiated output waveform is supplied to a demultiplexer 76. Like the delay circuit 72, the demultiplexer 76 has n taps spaced apart by sampling periods Δτ, and the output of each tap is supplied to an analog waveform accumulator 77. The analog waveform accumulator 77 includes, for example, n analog accumulators configured as a sampling and holding circuit, and the demultiplexer 76 has a detection interval (an interval of about H/2 after the leading edge VE of the vertical synchronization signal). ) is finished being supplied, the sampling gate is turned on, and n values obtained by sampling the ghost differential waveform at a sampling period Δτ are stored in the hold capacitor.
The n values from the hold capacitor of the analog waveform accumulator 77 are supplied as weighting coefficients to the multipliers 73 ₁ to 73 _o , and the canceling signal S ₃ can be generated from the adder 74. .

The video signal _S1 appearing at the output side of the synthesizer 9 of the ghost removal circuit is supplied to the control signal generation circuit 8 to generate the control signal Ps. This control signal Ps
is the leading edge of the vertical synchronization signal as in the previous embodiment.
It reached a high level slightly before VE, and due to this
The operation of the ANC circuit 4 is prohibited, and the time constant of the AGC circuit 6 is switched to a larger one. Therefore, there is an advantage that ghosts can be detected accurately as described above.

Note that the ghost removal device is not limited to the feedback type, but may be of the feedforward type. Of course, the present invention may be applied not only to a ghost removal device but also to a ghost measurement device that measures the level of ghosts and the like.

[Brief explanation of drawings]

Figures 1 and 2 are waveform diagrams of video signals used to explain the present invention, Figure 3 is a basic configuration diagram of an embodiment of the present invention, and Figure 4 is a detailed block diagram of an embodiment of the present invention. , 5 and 6 are waveform diagrams used in the explanation, FIGS. 7 and 8 are block diagrams of an example of a leading edge detection circuit of the vertical synchronization signal and waveform diagrams used in the explanation, and FIG. 9 is a waveform diagram used in the explanation. A connection diagram showing the general configuration of an AGC circuit, FIG. 10 is a connection diagram of an example of an ANC circuit, FIG. 11 is a waveform diagram used to explain the ghost removal operation of an embodiment of the present invention, and FIG. 12 is a diagram of the present invention. FIG. 3 is a block diagram of another embodiment of the invention. 3 is a synchronous detection circuit, 4 is an ANC circuit, 5 is a ghost removal circuit, 6 is an AGC circuit, 8 is a control signal generation circuit, and 9 is a synthesizer.

Claims (1)

[Scope of utility model registration request] In a ghost detection device in which a part of a vertical blanking period including a predetermined period from the leading edge of a vertical synchronization signal of a video signal from an ANC circuit connected to a video detector is set as a ghost detection period, at least the ghost detection period A ghost detection device that disables the above-mentioned ANC operation.