JPH0438075A - Vertical synchronism reproducing circuit - Google Patents

Abstract

PURPOSE:To stably reproduce a vertically synchronizing signal from a video signal including a pulse noise by comparing a detected vertically synchronizing pattern with a reference vertically synchronizing pattern stored in a receiving side memory, and when the detected pattern is matched with the reference pattern, outputting a vertically synchronizing signal. CONSTITUTION:A composite video signal (a) including a pulse noise is separated into a synchronizing signal (b) by a synchronizing separating circuit 1, the signal (b) is integrated by an integrating circuit 2 and a vertically synchronizing signal (e) is obtained from a comparator circuit 3. The pattern of the signal (e) is compared with a digital reference vertically synchronizing pattern (f) previously stored in a memory 5 by a pattern comparing circuit 4, and when both patterns match with each other, a vertical reset signal (g) is outputted from the circuit 4. If the pattern of the signal (e) does not completely match with the pattern (f), the signal (g) is not outputted from the circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a reproducing circuit that reproduces a vertical synchronizing signal of a transmitted television signal by eliminating pulse noise on the receiving side.

(Summary of the Invention) This invention relates to a vertical synchronization signal regeneration circuit for television signals, in which an integrator circuit for detecting a vertical synchronization signal after a synchronization separation circuit on the receiving side is reset to have a cycle half the horizontal synchronization cycle. The detected vertical synchronization pattern is reset with a pulse and compared with a predetermined setting level, and the detected vertical synchronization pattern is compared with the reference vertical synchronization pattern stored in the memory, and only when it matches with the reference pattern, the vertical synchronization signal is output. is output.

By doing so, a vertical synchronization signal reproducing circuit is provided that can stably reproduce a vertical synchronization signal from a video signal containing pulse noise.

(Prior Art) Since a television separates and combines images by scanning, it is necessary to correctly synchronize the scanning on the transmitting and receiving sides. A synchronization signal plays this role, and the synchronization signal includes a horizontal synchronization signal and a vertical synchronization signal, and these signals are multiplexed onto the video signal. The synchronization signal is normally multiplexed with the opposite polarity to the video signal so that it can be easily separated from the video signal. On the receiving side, the signal is separated from the video signal by a synchronization separation circuit using the difference in amplitude. In order to easily separate the horizontal and vertical synchronizing signals, the pulse width of the vertical synchronizing signal is much wider than that of the horizontal synchronizing signal. The vertical synchronization timing is extracted using the amplitude difference of the continuous output signal. On the other hand, the horizontal synchronization signal is separated by a differentiating circuit, and the above is a general conventional example of a synchronization reproducing circuit.

(Problem to be solved by the invention) Although the synchronization signal described above has been devised to be less susceptible to noise when being multiplexed with the video signal and transmitted, it is still possible for pulse noise to be mixed into the video signal. In the conventional vertical synchronization reproducing circuit, erroneous detection of the vertical synchronization signal occurs on the receiving side, causing the screen to shake up and down.

SUMMARY OF THE INVENTION An object of the present invention is to provide a vertical synchronization reproducing circuit that can stably reproduce a vertical synchronization signal even when such pulse noise is mixed into a video signal.

(Means for Solving the Problem) In order to achieve this object, the vertical synchronization regeneration circuit of the present invention has the following features:
A synchronization separation circuit, an integration circuit that integrates its output while resetting it with a reset pulse having a period half the horizontal synchronization period, a comparator circuit in which the output of the integration circuit is compared with a predetermined setting level, and the comparator circuit A pattern comparison circuit that compares the pattern of the output signal with a reference vertical synchronization pattern stored in a memory, and an output from the pattern comparison circuit when the memory in which the reference vertical synchronization pattern is stored and the compared pattern match. The present invention is characterized by comprising a horizontal synchronization pulse counter circuit to which a vertical reset signal and a horizontal synchronization signal are inputted, and a vertical synchronization signal is outputted accordingly.

(Function) According to the reproducing circuit of the present invention, when the synchronizing signal is separated from the video signal on the receiving side and then passed through the integrating circuit, the integrating circuit is reset with a reset pulse having a period half the horizontal synchronizing period. Since we are comparing with a predetermined setting level,
Vertical synchronization and pulse noise can be separated, and the detected vertical synchronization pattern is compared with the reference vertical synchronization pattern stored in the memory of the receiving side, and vertical synchronization is performed only when the pattern matches the reference pattern. Since the signal is output, the vertical synchronization signal can be stably reproduced from a video signal containing pulse noise.

(Examples) The present invention will be described in detail below by way of examples with reference to the accompanying drawings.

FIG. 1 shows a block diagram of a non-limiting example configuration according to the present invention, and FIG. 2 shows waveforms of each part thereof.

The synchronization separation circuit 1 extracts a composite video signal a (
(Only the vertical synchronization part is shown in FIG. 2) is separated into synchronization signals. The synchronizing signal a contains noise corresponding to the pulse noise contained in the input signal a (only the pulse noise having the same polarity as that part of the signal is the signal that caused a problem in the conventional example).

The synchronizing signal is integrated by the integrating circuit 2, which integrates the reset pulse d, which has a period half the horizontal synchronizing period.
0 to obtain the output signal waveform C of the integrating circuit.
Next, this output signal C is processed in a comparator circuit such that it is sliced at its set level (-dotted chain line), and the signal portion above the slice level is a digital signal level, and the signal portion that does not exceed the slice level is processed as a digital signal. A digital signal of zero level is output, and a vertical synchronizing signal e after the comparator is obtained.

The pattern of this vertical synchronization signal e is then compared with a reference vertical synchronization pattern in digital form stored in advance in the memory 5 in a pattern comparison circuit 4, and when both patterns match, a vertical reset signal g is sent from the pattern comparison circuit 4. Output. When the pattern of the vertical synchronization signal e does not completely match the reference vertical synchronization pattern f, the vertical reset signal g is not output.

A vertical reset signal g is input to the reset input of the horizontal synchronization pulse count circuit 6. A horizontal synchronization pulse count circuit 6 counts horizontal synchronization signals and outputs a reproduced vertical synchronization signal.

The phase of the output vertical synchronization signal is determined by the vertical reset signal g. Further, since the horizontal synchronization pulse count circuit 6 outputs a vertical synchronization signal at predetermined intervals as a horizontal synchronization pulse count even if no vertical reset signal is input, short-term malfunctions of this type of vertical synchronization regeneration circuit are tolerated.

Although one embodiment of the present invention has been described above, it will be obvious to those skilled in the art that various modifications and changes can be made to the present invention within the scope of the claims.

(Effects of the Invention) As described above in detail, in the vertical synchronization regeneration circuit of the present invention, if the pattern of the synchronously separated vertical synchronization signal e and the reference vertical synchronization signal pattern f do not completely match, the vertical reset signal g is not output, and the phase of the reproduced vertical synchronization signal is a phase dependent on the horizontal synchronization pulse count circuit.

In this way, when pulse noise enters the video signal in the conventional vertical synchronization reproducing circuit, it is possible to eliminate malfunctions such as the vertical synchronization signal being reproduced twice in a regular period, which caused jitter on the west side. becomes possible.

[Brief explanation of drawings]

FIG. 1 shows a configuration block diagram of an embodiment of the present invention, and FIG. 2 shows waveforms of various parts of the first illustrated embodiment. 1...Synchronization separation circuit 2...Integrator circuit 3...
・Comparator circuit 4...Pattern comparison circuit 5・
...Vertical synchronization pattern memory 6...Horizontal synchronization pulse count circuit.

Claims (1)

[Claims] 1. In a reproduction circuit that receives a transmitted television signal and reproduces the vertical synchronization signal of the television signal, the reproduction circuit includes a synchronization separation circuit and a reset circuit whose output has a period half the horizontal synchronization period. An integrating circuit that integrates while being reset by a pulse, a comparator circuit that compares the output of the integrating circuit with a predetermined setting level, and a comparison between the pattern of the output signal of the comparator circuit and a reference vertical synchronization pattern stored in memory. A pattern comparison circuit to be compared, a memory in which the reference vertical synchronization pattern is stored, and a vertical reset signal and a horizontal synchronization signal that are output from the pattern comparison circuit when the compared patterns match are input, and the vertical 1. A vertical synchronization reproducing circuit comprising: a horizontal synchronization pulse counter circuit to which a synchronization signal is output.