JPH0364284A - Non-standard signal detecting circuit - Google Patents

Abstract

PURPOSE:To reduce the frequency of an erroneous decision by bringing the jitter quantity detected in one horizontal period to in-field addition and obtaining a large jitter quantity once in one vertical period. CONSTITUTION:The subject circuit is provided with a horizontal period counter 1, a reference counting value holding part 2, a subtracter 3, an absolute value converting circuit 4, an in-field adder 5, and a comparator 6. In this state, by counting the number of system clocks in one horizontal period, detecting the horizontal jitter quantity in one line, and also, adding the jitter quantity of each line, the jitter quantity in one field is derived, and by a decision using its value, a non-standard signal detection is executed. In such a way, a stable decision which is strong against a noise, and in which an erroneous decision is scarcely generated can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a non-standard signal detection circuit used in a digital television receiver.

[Conventional technology]

Digital television converts video signals into digital signals and achieves higher image quality through digital signal processing.
In particular, digital televisions that achieve high image quality through three-dimensional YC separation that utilizes the correlation between adjacent frames perform high-quality processing on NTSC signal standards, that is, standard signals that satisfy equation (1) shown below. be able to.

r3cl: Color subcarrier frequency f□: Horizontal scanning frequency fv: Vertical scanning frequency However, when a consumer VTR is used as a signal source,
The frequency interleave relationship may collapse due to jitter in the running system, and the relationship between the color subcarrier frequency fset and the horizontal scanning frequency f9 may no longer satisfy equation (1).
In this case, performing three-dimensional digital signal processing will actually cause deterioration in image quality. Therefore, if the input signal is NTSC
It is necessary to change the digital video signal processing system depending on whether the signal is a standard signal that satisfies the standards or a non-standard signal that does not satisfy the frequency interleave relationship, such as in a VTR. In order to control this video signal processing system, a non-standard signal detection circuit is required to automatically determine whether an input signal is a standard signal or a non-standard signal.

The conventional configuration of this non-standard signal detection circuit is shown in FIG.
7 is a burst lock PLL that generates a burst lock clock ckb based on the burst signal of the input signal a;
8 is a line lock PLL that generates a line lock clock ckh based on the horizontal synchronization separation signal of the human input signal a;
9 is a vertical period frequency division pulse generation unit that generates pulses vb and vh obtained by dividing the input clocks ckb and ckh into vertical periods, and IO is a vertical period frequency division pulse generation section that generates pulses vb and line lock clock Ckh, which are obtained by dividing the frequency of the input clocks ckb and ckh into vertical periods. This is a phase comparator that compares the phases of pulses vh divided into vertical periods. The timing of pulses vb and vh at this time is shown in FIG.

When the input signal is a standard signal, N shown in equation (1) above is
Vertical period frequency division pulse v created from burst lock clock ckb for a stable signal that satisfies TSC standards.
The phases of the vertical period frequency divided pulse vh created from the line lock clock ckh and the line lock clock ckh are almost the same, and the phase difference g is an extremely small value.

On the other hand, when the input signal is a VTR, the relationship between the subcarrier frequency and the horizontal synchronization frequency does not satisfy equation (1) due to jitter in the tape running system, and does not meet the NTSC standard. As a result, the phase difference g becomes a large value. Therefore, the phase difference g between the vertical period frequency divided pulse vb created from the burst lock clock ckb and the vertical period frequency divided pulse vh created from the line lock clock ckh is detected, and when the phase difference g increases by a certain amount or more, It can be determined that the signal is a non-standard signal. In addition to VTRs, non-standard signal sources include game machines including Famicom.

In order to detect a non-standard signal, a determination is made on the magnitude of the phase difference g between the vertical period frequency division pulse vb created from the burst lock clock ckb and the vertical period frequency division pulse vh created from the line lock clock ckh. It is necessary to set a threshold for

In the case of a home VTR, due to jitter in the tape running system, the phase difference g between vertical frequency division pulses vb and Vh
The magnitude is about 500 to 600 nsecC. Therefore, it is necessary to set a value smaller than this jitter amount.
Generally, a determination threshold for detecting a non-standard signal is set at a location where the phase difference g is 100 to 200 nsec. For example, to generate a vertical period frequency divided pulse vb, 4fsc
(14,3MHz) burst clock 7 clock, line lock clock vertical period 0 frequency division pulse vh is burst lock clock vertical period frequency division pulse v
If it deviates from ±1 ck (±706 nsec) or more with respect to b, it is determined to be a non-standard signal.

If there is a deviation of ±lck or more in the vertical period, it is determined to be a non-standard signal, so the detection sensitivity is quite severe, and when a standard signal is input, noise etc. may cause an erroneous determination that it is a non-standard signal. .

[Problem to be solved by the invention]

Since conventional non-standard signal detection circuits are configured as described above, detection sensitivity must be set high in order to determine that the signal source such as a VTR is a non-standard signal. However, there were problems such as erroneous determination that the signal is a non-standard signal due to noise and other factors.

This invention was made to solve the above-mentioned problems, and aims to provide a non-standard signal detection circuit that is resistant to noise and can make stable judgments that are extremely unlikely to cause false judgments. purpose.

[Means to solve the problem]

The non-standard signal detection circuit according to the present invention includes a horizontal period counter that counts the number of system clocks in one horizontal period, detects the horizontal sick amount in one line, and adds the jitter amount of each line. The amount of jitter in the E-field is determined, and non-standard signal detection is performed by making a determination using that value.

[Effect]

The non-standard signal detection circuit in this invention detects the amount of horizontal jitter in one line and adds the amount of jitter in each line to find the amount of jitter in the l field. Therefore, it is possible to obtain a large value once per vertical period. and non-standard signal detection can be performed based on this value.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Generally, in the case of a VTR, the amount of jitter in one horizontal scanning line is 60 to 140 ns compared to the NTSC standard value.
It is about ec. On the other hand, when looking at the jitter of a VTR in terms of the vertical period, as described in the prior art section, the jitter amount of the line lock clock vertical period divided pulse with respect to the stable vertical period divided pulse of the vertical clock clock. is about 5
It is about 00 to 600 nsec. In this way, in the case of a VTR, the amount of jitter in a vertical period is not so large compared to the amount of jitter in one horizontal scanning period, partly because the jitter of each line is canceled out in both positive and negative directions. Therefore, in the present invention, attention is paid to jitter in one horizontal scanning period, the amount of jitter is detected, and the amount of jitter in each line is added within a field.

FIG. 1 shows the configuration of a non-standard signal detection circuit according to an embodiment of the present invention. In FIG. 1, I is a horizontal period counter;
2 is a reference count value holding section, 3 is a subtracter, 4 is an absolute value conversion circuit, 5 is an intra-field adder, and 6 is a comparator.

Next, the operation will be explained.

A horizontal period counter 1 counts the number of crotters in each horizontal scanning line. For example, a burst lock clock (or line lock clock) 4fsc (28.6 MHz) is used as the clock signal ck, and a count operation is performed in which each line is reset by a horizontal synchronization signal. In this way, one horizontal scanning period is detected. The reference count value holding section 2 is a part that holds count values corresponding to standard signals that meet the NTSC standard. When the burst lock clock 07 4 f s c (28,6 MHz) is used as the clock signal ck of the horizontal period counter 1, one horizontal scanning period is 910 ck, so the reference counter held by the reference count value holding section 2 The numerical value is 91O. The subtracter 3 subtracts the output value of the horizontal period counter 1 and the output value of the reference count value holding section 2.

The next absolute value converting circuit 4 converts the subtracted value into an absolute value, and detects the amount of jitter in one horizontal scan. The next intra-field adder 5 adds the amount of jitter in each horizontal scanning line output from the absolute value conversion circuit 4 to calculate the amount of jitter in one field. Using the jitter amount obtained once per vertical period in this way, the comparator 6 makes a determination based on a certain threshold value, and if the jitter amount output from the intra-field adder 5 becomes larger than the threshold value, It is determined that the signal is a non-standard signal, and a non-standard detection signal n is output.

Here, since the amount of jitter in one horizontal period is 60nsec to 140nsec with respect to the standard value of the NTSC standard, the burst lock clock 4fsc (28,6MH
z), the amount of jitter is O~2ck. Therefore, if the amount of jitter detected in one horizontal period is added within the field to obtain the amount of jitter once per vertical period, a considerably large amount of jitter can be obtained. As a result, the threshold value for non-standard signal determination can be set high, the noise margin becomes large, and the frequency of erroneous determination that a standard signal is input as a non-standard signal can be greatly reduced.

[Effects of the Invention] As described above, according to the present invention, the amount of jitter detected in one horizontal period is added within the field, and the amount of jitter is added in one vertical period.
Since a large amount of jitter is obtained, the threshold value for non-standard signal judgment can be set high, and the noise margin becomes large. This has the effect of greatly reducing the frequency of

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a non-standard signal detection circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a conventional non-standard signal detection circuit, and FIG. 3 is a diagram showing the configuration of a conventional non-standard signal detection circuit. FIG. 4 is a diagram showing waveforms of a frequency pulse and a line lock clock vertical period frequency division pulse. 2 is a horizontal period counter, 2 is a reference count value holding section, 3 is a subtracter, 4 is an absolute value conversion circuit, 5 is an intra-field adder, and 6 is a comparator. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Is the input signal installed in the digital television receiver a standard signal that meets the NTSC standard?
A non-standard signal detection circuit that determines whether the signal is a non-standard signal that does not meet the C standard includes a horizontal period counter that counts the number of clocks in one horizontal scanning period, and subtracts the output of the counter from a reference count value. a subtracter, and an absolute value converting circuit for converting the output of the subtracter into an absolute value, and means for detecting the amount of jitter with respect to an NTSC standard value of one horizontal scanning period; an intra-field adder that adds the amount of jitter for one field period; and an intra-field adder that performs threshold processing on the amount of jitter for one field period that is the output of the intra-field adder to determine if the amount of jitter is larger than the threshold. A non-standard signal detection circuit characterized by comprising a comparator that determines that the signal is a standard signal.