JPH03226072A - Synchronizing signal generator - Google Patents

Abstract

PURPOSE:To prevent generation of noise and to improve a pattern by counting an interval of a vertical synchronizing signal in the unit of 1H and applying field discrimination of the vertical synchronizing signal inputted externally based on the count so as to reset or preset a vertical counter. CONSTITUTION:A horizontal synchronization counter 14 frequency-divides a frequency input of nXfH of an original oscillator to 1/n and outputs a horizontal synchronization frequency fH. In this state, when a vertical synchronizing signal is inputted externally to a detector 16, the signal is converted into the vertical synchronizing signal synchronously with the frequency fH and outputted. Then the interval of the vertical synchronizing signals synchronously with the frequency fH is counted by a counter 17 operated by the frequency fH and the field discrimination is implemented by a field discrimination section 18. From the result of discrimination, a gate circuit 19 is controlled to reset a vertical synchronization counter 15. Thus, a counter giving adverse effect onto noise to at least effective video period is excluded from a synchronizing signal generator.

Description

[Detailed Description of the Invention]: Industrial Application Field] The present invention relates to a synchronization signal generation device used in television-related equipment, and particularly to a so-called external synchronization signal generation device that synchronizes with a synchronization signal generated by another synchronization signal generation device. The present invention relates to a synchronization signal generator that performs synchronization.

[Conventional technology]

Conventionally, this type of synchronization signal generation device compares the phases of an input external horizontal synchronization signal and a horizontal synchronization signal of the synchronization signal generation device using a phase comparator 51, as shown in FIG. The horizontal synchronization counter 5 is controlled by controlling the original oscillator 53 of the synchronization signal generator through the filter 52.
Horizontal synchronization is achieved by giving a transmission output to 4. A counter 55 for a vertical synchronizing signal is installed in the synchronizing signal generator at twice the horizontal scanning frequency (hereinafter referred to as 2fi) which is synchronized with the frequency (hereinafter referred to as f□) of one horizontal scanning period (hereinafter referred to as IH period). The detector 56 detects the vertical synchronization signal from the outside.
The counter 55 for vertical synchronization signal detects in 2fH units.
It is generally used to reset and synchronize with an external synchronization signal.

Problems to be Solved by the Invention C] However, in the conventional synchronizing signal generating device described above, since the counter 55 for the vertical period signal is operated at 2f, there is a The counting operation is performed when the scanning line is located approximately at the center of the effective screen scan amount. This is because if the television-related equipment that uses this synchronization signal generator handles minute video signals, (
For example, the noise generated at the time of branching (such as a video camera) feeds through to the video signal and causes noise interference near the center of the screen, significantly deteriorating the quality of the image obtained.

In order to prevent this, it is necessary to cause the counter 55 for the vertical synchronizing signal to operate at least once at f during the effective screen period, but such a configuration.

Let's reset it using an external vertical synchronization signal.

Then a problem arises. In other words, the currently widely used television systems such as the NTSC system, the PAL system, and the SECAM system use an interlace scan of 1, so the vertical synchronization signal is synchronized at an odd double of 1/2H, for example, the NTSC system. The method is 262.5H interval, PAL, SECA
In the M method, since the vertical synchronization signal is generated at 312.5H intervals, if this vertical synchronization signal is detected at IH intervals, the vertical synchronization will be performed in agreement with the horizontal synchronization, which has the disadvantage that interlaced scanning will not be possible.

[Means to solve the problem]

The synchronization signal generator of the present invention focuses on the fact that when an external vertical synchronization signal is detected at IH intervals, the intervals are different between the first field and the second field as described above.
A vertical synchronization counter that divides the frequency by one frame period in IH units, a means for taking in vertical synchronization signals inputted from the outside at intervals of one field period in IH units, and an interval of the vertical synchronization signals obtained by this means in IH units. The apparatus is characterized in that it has a counting means, performs a field determination of a vertical synchronizing signal input from the outside based on this counted value, and resets or presets the vertical counter based on this determination result and a signal from the capturing means. In other words, in order to solve the above-mentioned problem, if we consider the vertical synchronization signal detected at the IH interval, the 0.5H phase information will be lost, but if the interval of the vertical synchronization signal is the same as the first field and the second field. For example, in the case of the NTSC system, the external horizontal synchronization signal and the external vertical synchronization signal are input at the timing shown in Figure 3 (a) and (b), and the signal is input at the falling edge of the horizontal synchronization signal. A flip-flop 41.4 as shown in FIG. 4 detects an external vertical synchronization signal.
2 and a NAND gate 43, a reset signal like C in FIGS. 3(a) and 3(b) can be obtained. At this time, the input vertical synchronization signal from the outside is 262.5H between A and A' or between A' and A, but the detected reset signal of C is between B and B', that is, 262.5H. 26 in 1 field
2H, between B' and B, that is, 263 in the second field.
Hf7) interval. Also, the first field is 312H for the same reason as the l frame 625H system frame widely adopted in PAL and SECAM systems.

It is clear that a reset signal of the second field 313H interval is obtained.

〔Example〕

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The horizontal synchronization counter 14 receives a frequency input of nXfyo from the original oscillator.
/n and outputs the horizontal synchronization frequency f□.

Also, the vertical synchronization counter 15 keeps f8 up to frame synchronization.
For example, in a system of 1 frame 525H, the frequency is divided to 11525, and in a system of 1 frame 625H, the frequency is divided to 1/625. Then, based on these values of 14 and 15, the decoder unit 10 synthesizes various synchronization signals necessary for television-related equipment and outputs 8 signals. The horizontal synchronization signal input from the outside is phase-compared with the horizontal synchronization signal generated in the synchronization signal generator obtained from the decoder section 10 in the phase comparator 11, and this output is passed through the low-pass filter 12 to the original oscillator 13. Synchronization is achieved by obtaining a controlled frequency in addition to the In this state, when an external vertical synchronization signal is input to the detector 16, it is converted into a vertical synchronization signal synchronized with fTi and output. The counter 17, which operates at f□, counts the vertical synchronization signal interval synchronized with f8. , 263H, the field determining unit 18 determines that the field is the second field. Based on this determination result, the gate circuit 19 is controlled to
If the vertical synchronization counter 15 is reset (or preset) with the vertical synchronization signal obtained from the detector only during the field, the vertical synchronization counter 15 counting l frames can be
It is possible to reset.

The embodiment in FIG. 1 has a counter I7 for the vertical synchronization signal synchronized with f□ output from the detector, but the counter 17 can also be configured to double as the vertical synchronization counter 15. , a configuration diagram of an embodiment in this case is shown in FIG. The horizontal synchronization configuration from the outside and the point where a vertical synchronization signal synchronized with f from the external vertical synchronization signal is obtained by the detector 16 are the same as the embodiment in FIG. 1, and the same reference numerals as in FIG. 1 are used. is shown. In this practical example, the configuration is such that field determination can be made based on the count value of the vertical synchronization counter 25. For example, in the case of the NTSC system in which one frame consists of 525H, when the vertical synchronization counter 25 is configured to be preset to 2" by the input preset signal (see Fig. 3), 2 field reset position detection, i.e. “2
An IH period signal indicating a count value of 64'' is generated by the reset position detection section 28, and a gate circuit 29 is configured so that the vertical synchronization signal from the detector 16 does not act on the vertical synchronization counter 25 only during this period.

As a result, if the vertical synchronization signal corresponding to the first field is input from the detector 16 in a state where the vertical counter and the external vertical synchronization signal are not synchronized, the vertical synchronization counter 25 will receive a value other than "264". Sometimes the vertical synchronization counter 25 is preset to "2" and starts counting. Then, when a vertical synchronizing signal corresponding to the next second field is inputted from the outside, this signal is an inhibit signal based on the count value of "264" of the vertical counter, so that the vertical counter continues counting without being preset. On the other hand, when a signal corresponding to the second field is input from the outside in an asynchronous state, the vertical synchronization counter 25 also returns "26".
When the value is other than "4", the vertical synchronization counter 25 is preset to "2".

However, when the next external vertical synchronization signal corresponding to the first field is input, the count value becomes "265" because the signal from the detector 16 is longer by IH than the second field as described above. This occurs when , and a preset operation is performed.

After that, since the vertical synchronization counter 25 and the vertical synchronization signal from the outside are normally synchronized, the vertical synchronization signal corresponding to the second field from the detector 16 is "2" of the vertical synchronization counter 25.
It is inhibited by a count value of ``64'' and enters a synchronized state. That is, field determination is realized by a prohibition signal by a count value of ``264''.

〔Effect of the invention〕

As explained above, the present invention focuses on the fact that the vertical synchronization signals are different in the first field and the second field when the vertical synchronization signals are detected with the same IH cycle, and uses a vertical counter that operates from the horizontal synchronization frequency fyo. External synchronization of interlaced scanning can be realized from As a result, it is possible to eliminate a counter in the synchronization signal generating device that would have an adverse effect due to noise at least during the effective video period, and this is effective as a noise countermeasure for television-related equipment that handles minute video signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration diagram of an embodiment of the present invention;
FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention, and FIGS. 3(a) and 3(b) show the conversion from the first field to the second field and from the second field to the first field, respectively. The horizontal synchronizing signal a obtained from the external horizontal synchronizing signal or the synchronizing signal generator of the present invention synchronized with this and the external vertical synchronizing signal are detected in IH units by the detector. FIG. 4 is a diagram showing a vertical synchronization signal C. FIG. 4 is a circuit diagram showing an example of a detector, and FIG. 5 is a block diagram showing a conventional example. 10.50...decoder section, 11.51...
...Phase comparison L 12,52...Low pass filter 13.53...Original oscillator, 14.5
4...Horizontal synchronization counter, 15.25.55.
...Vertical synchronization counter, 16.56...
Detector, 17... Counter, 18...
Field determination section, 19.29... Gate circuit, 28... Reset position detection section, 41.42.
...D-flip-flop, 43...N
AND gate.

Claims (1)

[Claims] In a synchronization signal generator for television, a vertical synchronization counter divides the frequency by one frame period in units of one horizontal scanning period, and a means for capturing a vertical synchronization signal inputted from the outside at intervals of one field period in units of one horizontal scanning period. and a means for counting the interval of the vertical synchronizing signal obtained by this means in units of one horizontal scanning period, and using this counted value, performs field determination of the vertical synchronizing signal inputted from the outside, and compares this determination result with the above-mentioned vertical synchronizing signal. A synchronization signal generating device, characterized in that the vertical synchronization counter is reset or preset by a signal from a capture means.