JPH04139962A - Synchronizing signal generator - Google Patents

Abstract

PURPOSE:To generate various timing signals corresponding to plural kinds of the television systems by providing a counter skipping the count to the generator. CONSTITUTION:An H counter 5 counts a pulse number of clock signals CK fed from a frequency divider circuit 1 and outputs an H count data HD representing the count to an H decoder 6. Moreover, the H counter is reset by a reset pulse Hreset outputted from a synchronizing separator circuit 4 and outputs an H count pulse Hcp to a V counter 2 upon the receipt of the reset pulse Hreset. Furthermore, the V counter 2 skips the count at the NTSC mode to have a function to absorb the difference between scanning line number between the NTSC system and the PAL system. Thus, various timing signals corresponding to the plural kinds of the television systems are generated with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal generator that receives a synchronization signal compatible with multiple types of television systems and generates various timing signals synchronized with the synchronization signal. It is.

[Prior Art] A conventional synchronization signal generating device has an H counter that measures the horizontal synchronization period of an input television signal and a V counter that measures the vertical synchronization period, and the number of callan 1 output from the H counter is A horizontal synchronizing signal is generated by levering ~1 ~ data by an H decoder, a vertical synchronizing signal is generated by levering the count data output from the V counter by a V lever, and the H decoder, Various timing signals such as clamp pulses and flanking pulses were generated from the water 11 synchronization signal and vertical synchronization signal generated by the decoder.

However, when trying to make this synchronization signal generator compatible with multiple types of television systems such as the NTSC system and the PAL system, the V counter for the NTSC system and the V
Counters and Tecoators corresponding to each method were prepared, such as a V counter and a V Tecoater for the decoder PAL method, and these were made compatible by switching between them.

[Problems to be Solved by the Invention] However, in the conventional synchronizing signal generator as described above, it is necessary to prepare two types of V counters, one for the NTSC system and one for the PAL system, and a decoder. The number of gates constituting the decoder and the decoder increased, making the configuration more complex, and the cost was 1-high.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a synchronization signal generation device that can generate various timing signals compatible with a plurality of types of television systems with a simple configuration.

[Means for Solving the Problem] The synchronization signal generating device of the present invention is a device for processing an image signal that receives synchronization signals compatible with multiple types of television systems and generates various timing signals synchronized with the synchronization signals. The apparatus is equipped with a counter that counts the number of horizontal synchronizing pulses in a synchronizing signal corresponding to the television system, and also skips the count value according to the television system.

[Operation] According to the above configuration, various timing signals compatible with multiple types of television systems can be generated with a simple configuration.

[Example] Hereinafter, the present invention will be explained using examples of the present invention.

FIG. 1 is a diagram showing a schematic configuration of a synchronization signal generating device to which the present invention is applied, as an embodiment of the present invention.

The synchronizing signal generator shown in FIG. 1 is compatible with both the NTSC and PAL television systems.

In FIG. 1, 1 is a frequency dividing circuit that divides a reference signal and generates a clock signal Ck and a subcarrier signal fsc used inside the synchronization signal generator, 2 is a V counter, and 3
a V decoder that generates a vertical synchronization signal Vsync according to count data supplied from the V counter 2;
4 is a sync signal separation circuit that separates a horizontal sync signal and a vertical sync signal from a composite sync signal input from the outside; 5 is an H counter; and 6 generates a horizontal sync signal Hsync according to the count data supplied from the H counter 5. 7 is a decoder that generates various timing pulses such as clamp pulses and blanking pulses in accordance with the vertical synchronization signal Vsync signal supplied from the V decoder 3 and the horizontal synchronization signal Hsync output from the H decoder 6; The skip operation in the V counter 2 is NTS
This is an AND gate that allows permission only in C mode.

The operation of the configuration shown in FIG. 1 will be explained below.

In FIG. 1, a frequency dividing circuit 1 is supplied with a reference signal having a frequency four times that of the subcarrier signal fsc (i.e., 118 in NTSC mode) from a reference signal generator (not shown).
z, a signal with a frequency of 17.734475MHz in PAL mode) is input, and the 4-frequency divider 1 in the frequency divider circuit 1
a, is supplied to the 5 frequency divider 1b.

In addition, for the frequency dividing circuit I, either a synchronizing signal generator is operated to comply with the NTSC system (NTSC mode) or a P
A mode designation signal that specifies whether to operate in accordance with the AL system (PAL mode) is supplied, and if the mode designation signal specifies NTSC mode, the selector switch lc in the frequency divider circuit 1 is supplied. is connected to the N side in the figure, and when PAL mode is specified, the selector switch lc in the frequency divider circuit l is connected to the P side in the figure.
A 45 MHz clock signal Ck is output, and a 3.546895 MHz clock signal C is output during PAL mode.
The clock signal Ck is outputted from the V counter 2,
The signal is supplied to the decoder 3, H counter 5, and H decoder 6, respectively.

In addition, a subcarrier signal fsc (3.579545M in NTSC mode) is generated by dividing the input reference signal from the frequency divider circuit 1 by a 4-frequency divider 1a.
1+z, P A L mo 1 ~ sometimes L433[i+87
5 old 17. ) is output.

On the other hand, the synchronization signal generator is supplied with a composite synchronization signal that is externally reproduced from an image signal recorded on a recording medium, etc., and is separated from the reproduced image signal, and is input to the synchronization signal separation circuit 4. The synchronization signal separation circuit 4
outputs a reset pulse Hreset that resets the H counter 5 when it detects the previous edge of the horizontal synchronization signal in the input composite synchronization signal, and outputs a reset pulse Hreset that resets the V counter 2 when it detects the previous edge of the vertical synchronization signal.
Output reset.

Then, the H counter 5 counts the number of pulses of the clock signal CK supplied from the frequency dividing circuit 1 as described above, and sends the H count data H[l representing the count value to the H decoder 6.
and is reset by the reset pulse Hreset output from the synchronization signal separation circuit 4,
An H count pulse Hcp is output to the V counter 2 every time the reset pulse Hreset is input.

The V counter 2 counts the number of H count pulses Hcp supplied from the H counter 5 as described above, outputs V count data VD representing the count value to the V decoder, and outputs the V count data VD representing the count value to the V decoder. The field identification pulse FDP is output to the H counter 5 every time the reset pulse VreseL is input.
Counter 2 is reset every time it counts 313'.

By the way, the H counter 5 is supplied with a mote designation signal, and in PAL mode it is reset every time it counts "217", or in NTSC mode it is reset every time it counts "217".
217” is reset every time it is counted, and 2
18", or alternately each time the field identification pulse FDP is input from the V counter 2, and the H decoder 6 at the next stage receives these H count data HD. By decoding it, it becomes 15734.263Hz, P A in NTSC mode.
When in L mode, a horizontal synchronization signal of 15625.088Hz is output.

In addition, V counter 2 changes the count value to ``243'' when the count value reaches ``192'' when the NTSC is 1~1.
The V counter 2 has a function of absorbing the difference in the number of scanning lines between the NTSC system and the PAL system by skipping to ``194''. Output to ND gate 8. If a mote designation signal designating the NTSC mote is supplied to the AND gate 8, the AND gate 8 becomes open and the count detection pulse CDP or V
The signal is supplied to the counter 2, and the skip operation described above is performed.

As described above, the V count data VD output from the V counter 2 is supplied to the V decoder 3, and by decoding the V count data VD in the V decoder 3, a vertical synchronization signal is output, and the decoder 7 are the horizontal synchronizing signal H5ync supplied from the H decoder 6, and the V decoder 3
For example, various timing pulses such as a clamp pulse and a blanking pulse are generated in response to the vertical synchronizing signal Vsync supplied from the vertical synchronizing signal Vsync.

As described above, in this embodiment, by skipping the count value of the V counter according to the type of television system, the difference in the number of scanning lines for each television system can be reduced by 1 each for the V counter and V decoder. Therefore, it becomes possible to configure a circuit with a smaller number of gates than in the past, and it becomes possible to reduce costs.

Note that the synchronizing signal generator of this embodiment is compatible with both the NTSC system and the PAL system, but the present invention is not limited to this combination.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a synchronization signal generating device that can generate various timing signals compatible with multiple types of television systems with a compact configuration. You will be able to do it.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of a synchronization signal generating device to which the present invention is applied, as an embodiment of the present invention. l... Frequency divider circuit 2... V counter 3... ■Decoder 4... Synchronous signal separation circuit 5... H counter 6... H decoder 7... Tecoder

Claims (1)

[Scope of Claims] A device for processing an image signal that receives a synchronization signal compatible with multiple types of television systems and generates various timing signals synchronized with the synchronization signal, the apparatus comprising: A synchronization signal generating device comprising a counter that counts the number of horizontal synchronization pulses in a synchronization signal and skips the count value depending on the television system.