KR920009009B1 - Circuit for displaying picture of multiple channels - Google Patents

Abstract

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Description

Multi Channel Image Display Circuit

1 is a block diagram showing one embodiment of a multi-channel image display circuit according to the present invention.

FIG. 2 is a circuit diagram showing a part of the configuration of FIG.

3 is a timing chart for explaining a write operation according to the present invention.

4 is an explanatory diagram for explaining multi-channel image display on a display device.

5 is a block diagram showing an example of a conventional multi-channel image display circuit.

6 and 8 are timing charts for explaining the operation of the circuit of FIG.

7 is a diagram showing a map of an image memory.

* Explanation of symbols for the main parts of the drawings

11: antenna 12: TV tuner

13: image detection circuit 14: main screen signal processing circuit

15: screen switching circuit 17: time division switching circuit

18: A / D converter 19: Digital signal processing circuit

20: Image memory 21: A / D converter

22 microcomputer 23 PLL circuit

24: synchronous separation circuit 31: divider

32, 34: OR gate 35: AND gate

36: write address counter

The present invention relates to a multi-channel image display circuit capable of splitting and displaying a plurality of received images on a TV screen.

Recently, as a function of supplementing the channel search operation of a TV receiver, as shown in FIG. 4, image information obtained by receiving signals of multiple channels is displayed on a screen divided at the same time, and a signal channel and the screen information are displayed. There is provided a multi-channel image display circuit. 4 shows an example in which another multi-channel image is displayed as a sub screen on a part of the main screen. As another example, Japanese Patent Laid-Open No. 60-257681 discloses a means for displaying a multi-channel image by dividing the entire screen into equal parts.

5 is a configuration diagram showing the multi-channel image display circuit.

5, a desired channel signal is selected by the TV tuner 52, converted into an intermediate frequency (IF) signal, and enters the image detection circuit 53. As shown in FIG. The output of the video detection circuit 53 is input to the main picture signal processing circuit 54 which processes the chroma signal and the luminance signal separately, and is separated into two color difference signals R-Y and B-Y and the luminance signal -Y. These R-Y, B-Y and -Y signals are supplied to the CRT 56 via the screen switching circuit 55 and displayed as main screen information.

Reference numeral 57 is a time division switching circuit for changing the R-Y, B-Y, and -Y signals output from the main picture signal processing circuit 54 into time division multiple signals by the switching operation of the multiplexer. The output of this time division switching circuit 56 is digitally signaled by an analog / digital converter (hereinafter referred to as an A / D converter) 58 and input to the digital signal processing circuit 59. The digital signal processing circuit 59 generates an address signal and writes the digitalized image signal to the display image memory 60 capable of multi-channel divisional writing. The digital signal processing circuit 59 read-controls the image memory 60, and converts the written time-division multiple-format image signal through a digital / analog converter (hereinafter referred to as a D / A converter) 61. Supply to 55. The screen switching circuit 55 selectively switches and outputs the main screen signal and the multi-channel image signal according to the switching control signal from the digital signal processing circuit 59 to display an image as shown in FIG. do. The digital signal processing circuit 59 also supplies a predetermined switching control signal to the time division switching circuit 57.

The tuning microcomputer 62 performs reception control of the TV tuner 52 through a phase lock loop circuit (hereinafter referred to as a PLL circuit) 63. The microcomputer 62 also supplies a write permission signal to the digital signal processing circuit 59. The digital signal processing circuit 59 writes to the image memory 60 in the generation period of the write permission signal.

Reference numeral 64 is a synchronous separation circuit for separating the synchronous signal from the output of the video detection circuit 53, and the horizontal and vertical synchronous signals HD and VD output from the circuit 64 are sent to the digital signal processing circuit 59. Supply. The digital signal processing circuit 59 uses these synchronization signals HD and VD as a synchronization signal serving as a reference for the write address signal.

FIG. 6 shows a timing chart of an operation outline for displaying four channel multi-channel images as shown in FIG. In the figure, reference numeral 6A denotes a tuning operation, and channel 1, channel 2,... Channels are selected by sequentially switching the tuning signal from the PLL circuit 63. In this way, each channel is switched and received at predetermined intervals. Reference numeral 6B denotes a permission signal output from the microcomputer 62 and is generated each time reception of one channel is completed.

The write operation is performed in synchronization with the generation period of the write permission signal, as indicated by the symbol 6C, and the reception signals up to channels 1-4 can be written in the image memory 60.

7 shows an address map when writing a reception picture for four screens of channels 1-4. 7 (a) corresponds to channel 1. Similarly, 7 (b) corresponds to channel 2, 7 (c) corresponds to channel 3, and 7 (d) corresponds to channel 4, respectively. As can be seen from these figures, the number of addresses per horizontal scanning period is 56 corresponding to the received signal of each channel. First, in the case of writing the image information of the channel 1, the digital signal processing circuit 59 sets the address value of the vertical address counter to zero when the vertical synchronization signal VD of the channel 1 is processed. Each time the horizontal synchronizing signal HD of the channel 1 is processed by the digital signal processing circuit 59, the vertical address counter increments the count value by (+) 168 and repeatedly writes the horizontal period. When image information for one field of channel 1 is written, the vertical address counter adds the write address by (-) 24920 and returns to address 0. Then, the field is written again. When the microcomputer 62 stops the generation of the write permission signal, the digital signal processing circuit 59 completely finishes writing for one field, and then processes the next vertical sync signal VD to write address counter ( Add 24864 additions. As a result, the write address is set to 56, which is the write start address of the channel 2. When performing the write operation of the channel 2, the microcomputer 62 controls the PLL circuit 63 to receive the channel 2. When the channel 2 is received, the write permission signal is output from the microcomputer 62, so that the vertical address counter writes the received signal of the channel 2 into the image memory 60 from the write address at address 56. The writing of channel 3 and channel 4 is also the same. Therefore, the image memory 60 has a screen right end of channel 1 and a screen left end of channel 2, a screen right end of channel 2 and a screen left end of channel 3, a screen right end of channel 3 and a screen left end of channel 4, and a screen right end of channel 4; The address values coincide at the left end of the screen of channel 1 to form an address arrangement obtained by dividing the multi-channel image display area into four. With this address arrangement, it is possible to facilitate the counting of the read addresses triggered by the horizontal synchronizing signal in the main picture signal at the time of reading.

Here, the address counting operation per horizontal scanning period will be described with reference to FIG. In Fig. 8, 8A indicates the horizontal synchronizing signal HD, and 8B indicates the write operation period for the horizontal synchronizing signal HD. The digital signal processing circuit 59 counts the write address counter using the horizontal synchronizing signal HD as a trigger. In the period (low level) of the horizontal synchronizing signal HD, the generation of the address counting clock is stopped, and when this period ends and the interval between syringes is generated, the address counting clock is generated. In general, since the horizontal blanking period is 16% of the horizontal synchronization 63.5 µsec, the period of the horizontal synchronization signal HD is about 10.2 µsec, from which the effective picture period is about 53.3 µsec. The writing period Tw is determined in accordance with the overscan rate. In this case, assuming that the horizontal overscan rate is 10%, the writing period Tw of the received signal is

It becomes The write pause period Ts within the effective screen period is (53.3-48.0) / 2.

It becomes

That is, the digital signal processing circuit 59 writes a signal of about 2.67 μsec in each of the horizontal synchronization signal HD before and after the signal of one horizontal period in consideration of the overscan rate to the image memory 60.

Next, a case where a no signal channel is received will be described. In this case, noise is output from the synchronous separation circuit 64. This noise exhibits approximately horizontal period in-pulse noise depending on the nature of the synchronous separation time constant circuit.

The period of this noisy pulse varies depending on the performance of the synchronous separation circuit 64, but deviates by ± 2 μsec to ± 4 μsec from the normal period.

Therefore, when this noise pulse is indicated by the dotted line in 8A of FIG. 8, when Ts (= 2.67 µsec) or more and shorter than 4 µsec, the digital signal processing circuit 59 counts the number of addresses required for one horizontal period. Before reaching 56 counts, a malfunction occurs in which the address is added (+168) in response to inpulse noise. As a result, a phenomenon occurs in which the next video data of one horizontal period is not written to a predetermined address. For example, when the video data of the non-signal channel is written to the address to which the video signal of the audio signal channel is to be written, and the multi-channel display is performed, the difference of the picture on the display frame or the noise image of the non-signal channel is displayed at the display position of the audio signal channel. The malfunction that is displayed appears.

In order to prevent such a malfunction when the non-signal channel is received, the write stop period Ts is set to end the count of the write address, i.e., 56 counts, even if the synchronization of the horizontal synchronization signal HD becomes shorter than 4 mu sec. A setting longer than 2.67 μsec, for example, about 4.5 μsec to 5.0 μsec may be considered. However, if the writing stop period Ts is set longer, the writing period Tw is shortened and the information amount is insufficient because the amount of image information with an overscan rate of 16% or more is cut off.

As described above, in the conventional TV receiver having a multi-channel image display function, there is a problem that a write malfunction occurs due to the disturbance of the horizontal synchronizing signal HD caused by inpulse noise at the time of no signal channel reception. In addition, when the write stop period is extended and the write period Tw is shortened, the image is deleted beyond the overscan rate, so that there is a problem that the amount of information becomes insufficient.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-channel image display circuit which eliminates the above problems, prevents write malfunction, and does not reduce the amount of information of the oil signal channel.

That is, one form of the multi-channel image display circuit according to the present invention is a TV signal receiving means, an image memory for writing received image signals of a plurality of channels sequentially received by the means, and a horizontal synchronization signal from the received signals of the multiple channels. Means for determining whether the period of the horizontal synchronizing signal outputted from this sync separating means is within an allowable range for a predetermined period, an address counter for accessing the image memory, and a count for the counter. A clock generator for generating a driving clock, and a divider having the same division ratio, and according to the output of the determination means for each received channel, when the period of the horizontal synchronizing signal is within the allowable range, the clock generator Is supplied to the address counter and the output of the divider is addressed if it is out of the allowable range. And a digital signal processing means for supplying a write control to the image memory, and writing the received signal of the non-signal channel into the image memory every horizontal period without being disturbed by the disturbance of the period of the horizontal synchronization signal. It is characterized by one.

According to the present invention, when the period of the horizontal synchronizing signal output from the synchronizing separation means is within a predetermined allowable range, it is determined that no signal is received and the frequency of the write address generation clock is increased. As a result, writing of one horizontal period is finished within a time shorter than the normal period, and as in the related art, the next horizontal synchronizing signal arrives during the writing period, and the reception signal of each channel is not displayed out of each display area.

Hereinafter, according to the present invention, a multi-channel image display circuit will be described by the embodiment shown in the drawings.

FIG. 1 is a block diagram showing one embodiment of a multi-channel image display circuit according to the present invention, and FIG. 2 is a circuit diagram detailing part of the configuration of FIG.

In FIG. 1, 11 is a TV broadcast signal receiving antenna, 12 is a TV tuner, 13 is an image detection circuit, 14 is a main screen signal processing circuit, and 15 is a main screen signal from the main screen signal processing circuit 14. A screen switching circuit for switching between display and multi-channel image signal display, and 16 represents a display device for displaying the output from the screen switching circuit 15, for example, a cathode ray tube (hereinafter referred to as CRT). Numeral 22 denotes a microcomputer that executes the international language of the TV tuner 12, and controls the TV tuner 12 through the PLL circuit 23. As shown in FIG.

The main picture signal processing circuit 14 outputs two color difference signals R-Y and B-Y and a luminance signal -Y, and supplies them to the time division switching circuit 17, respectively. The time division switching circuit 17 is constituted by a multiplexer and time-divisions the R-Y, B-Y, and -Y signals, respectively, and supplies them to the A / D converter 18. The digital image signal is obtained from the A / D converter 18 in the form of a composite video signal and input to the digital signal processing circuit 19. The output of the image detection circuit 13 is input to the synchronous separation circuit 24. The vertical and horizontal synchronizing signals VD and HD obtained by synchronizing separation are input to the digital signal processing circuit 19 as reference signals such as a write address signal.

The microcomputer 22 determines the period of the horizontal synchronizing signal HD input from the synchronizing separation circuit 24. As a result, the microcomputer 22 supplies the decision signal S1 for determining the period of the horizontal synchronization signal HD to the terminal P1 of the digital signal processing circuit 19 together with the write permission signal. The digital processing circuit 19 generates a write address by these write permission signals and the determination signal S1.

The circuit shown in FIG. 2 shows the structure of the clock generation circuit for the write address counter in the digital signal processing circuit 19. As shown in FIG. In Fig. 2, the reference clock for counting the write address is supplied to the terminal P2. The frequency of this reference clock is 2 fo.

On the other hand, the determination signal S1 output from the microcomputer 22 is supplied to the terminal P1. In this case, the determination signal S1 becomes a high level when receiving a no-signal channel, and becomes a low level when receiving a no-signal channel. This determination signal S1 is input to one input terminal of the OR gate 32. The divided clock fo obtained by dividing the reference clock 2fo from the input terminal P2 into the 1/2 divider 31 is input to the other input terminal of the OR gate 32. The logical sum output from the OR gate 32 is input to one input terminal of the AND gate 35. The 2 fo reference clock from the input terminal P2 is input to one input terminal of the OR gate 34. The determination signal S1 is input to the other input terminal of the OR gate 34 through the inverter 33. The OR sum output from the OR gate 34 is input to the input terminal on the other side of the AND gate 35. The AND product output from this AND gate 35 becomes a count input of the write address counter 36.

Then, the digital signal processing circuit 19 reads out the data written into the image memory 20 based on the timing of the synchronization signal related to the main picture signal, and converts the data into an analog signal by the D / A converter 21. Supply to the screen switching circuit 15. As a result, the image signal as the screen information from the digital signal processing circuit 19 is displayed as one of the multi-channel images.

In the multi-channel image display circuit having such a configuration, the microcomputer 22 determines the period of the horizontal synchronization signal HD separated by the synchronization separation circuit 24. Accordingly, when the period of the horizontal synchronizing signal HD is within a disturbance range that can be tolerated from a normal value, the microcomputer 22 judges that the signal signal is received and outputs the low level discrimination signal S1. When the synchronization of the horizontal synchronizing signal HD is out of the allowable range, it is determined that there is no signal reception and outputs a high level determination signal S1.

In the circuit of FIG. 2, when the no signal channel is received, the determination signal S1 induced to the terminal P1 is at a high level, so that the OR sum output of the OR gate 32 is at a high level, and the 1/2 divider 31 The divided clock of the frequency fo from ()) is not output from the OR gate 32. In addition, since the determination signal S1 at this time is inverted by the inverter 33 to be at the low level, the reference clock of the frequency 2fo from the terminal P2 is obtained through the OR gate 34. At this time, since the output of the OR gate 32 is high level, the input of one of the AND gates 35 becomes high level. Therefore, the reference clock of frequency 2fo passing through the OR gate 34 is given to the write address counter 36 through the AND gate 35 and generates a write address.

In addition, since the determination signal S1 is at the low level upon reception of the channel signal channel, the divided clock of the frequency fo from the 1/2 divider 31 is obtained through the OR gate 32. On the other hand, the output of the inverter 33 is at the high level, and the output of the OR gate 34 is at the high level, so that the reference clock of frequency 2fo is not output from the OR gate 34. At this time, the divided clock of the frequency fo is obtained from the AND gate 35, and the write address counter 36 generates the write address at the divided clock of this frequency fo.

In this manner, the digital signal processing circuit 19 accesses the image memory 20 as a write address based on the reference clock of frequency 2fo at the time of receiving a no signal channel, and writes based on the divided clock of the frequency fo at the time of receiving a signal signal. The image memory 20 is accessed as an address.

In this manner, the clock 2 driving the write address counter 36 at the time of receiving a no-signal channel.

If fo is twice the counter driving clock fo at the time of receiving the signal channel, the timing chart of writing the image signal per horizontal period at the time of receiving the signal and receiving the channel is as shown in FIG.

In Fig. 3, 3A indicates the horizontal synchronizing signal HD, 3B indicates the writing period upon reception of the signal-signal channel, and 3C indicates the writing period upon reception of the no-signal channel.

At the time of receiving the signal, as in 8B of FIG. 8, the write stop period at the time of the effective screen period is set to 2.67 µsec x 2, and the reception signal can be written in the 48 µsec period therebetween. The write address in this write period is generated by the clock example of the frequency fo, and since the blur of the horizontal sync signal HD is less than in the case of no signal, it is absorbed within the overscan period, and the count of one horizontal period is reliably. Quit.

On the other hand, since the frequency of the drive clock of the write address counter 36 becomes 2fo at the time of no signal channel reception, as indicated by 3C, the write period is a period of 24 mu sec, which is the focal point at the time of receiving the signal signal channel. The time from the completion of the horizontal synchronizing signal HD to the start of writing is 2.67 secsec of reception of the channel signal channel, and therefore 1.335 secsec, which is half of that at the time of the reception of the no-signal channel. Accordingly, even when the disturbance of the horizontal synchronizing signal HD is +4 μsec at maximum, the allowable time Tm occurs from the end of the write address count to the next horizontal synchronizing signal HD. This Tm is

It becomes

That is, the allowable time Tm can be taken up to at least 24 sec, and the following horizontal synchronizing signal HD does not appear during the write address count as in the prior art. As a result, the address count error is eliminated, and there is no deviation of the image from the display area, and the image area of the no signal channel crosses into the display area of the signal signal channel.

In the present invention, the amount of information in the horizontal direction at the time of radio call channel reception is half of that at the reception of the signal-signal channel. However, since the image of the no-signal channel is noise, there is no practical problem even when the information amount is measured. When the clock signal frequency of the write address counter 36 is switched in half by the discrimination signal S1 from the microcomputer 22 at the time of receiving the signal signal, the signal is doubled at the time of no signal in the writing period. It is possible to write at an overscan rate equivalent to that of a normal TV signal.

Incidentally, the circuit of Fig. 2 in which the drive clock of the write address counter 36 is selected from the discrimination signal S1 can be conceived of various circuit systems other than the above embodiment. In addition, the counter driving clock at the time of receiving a signal channel does not necessarily need to be 1/2 at the time of reception of a signalless channel. As the counter drive clock at no signal is higher than at the signal, the extra time Tm can be increased.

As described above, according to the present invention, the multi-channel display screen is not wrongly displayed by the received signal of the non-signal channel, and there is an effect that the image of the signal channel is surely displayed in its display area.

Claims (4)

TV signal receiving means (101) for receiving a TV broadcast signal and video detecting the received signal: time division means (17) for time division of a plurality of video signals detected by this TV signal receiving means (011); An image memory 20 which writes a plurality of time division video signals obtained by the time division means 17 at predetermined addresses, respectively; Synchronization signal separation means 24 for separating a horizontal synchronization signal from the video signal detected by the TV signal receiving means 101; and driving and driving an address counter and this address counter for accessing the image memory 20; Image memory control means (19) which has a clock signal generating means for generating a clock signal, and supplies the drive clock signal to the address counter to perform write control of the image memory (20): from the image memory (20) In a multi-channel image display circuit having a display means 16 for simultaneously displaying video signals of multiple channels read out, the presence or absence of a broadcast signal for each channel using the horizontal synchronization signal separated by the synchronization signal separation means 24. And judging means 22 for judging? And outputting a different judging signal depending on the presence or absence of the no signal. The clock signal generating means of stage 19 selectively generates a first driving clock signal of a first frequency and a second driving clock signal of a second frequency higher than the first frequency, and from the determination means 22 Using the determination signal, the idle signal example supplies the first drive clock signal to the address counter, and when the signal does not signal, supplies the second drive clock signal to the address counter to write the image memory 20. A multi-channel image display circuit characterized by performing control. The multi-channel image display circuit according to claim 1, wherein said TV signal receiving means (101) comprises tuning means (22,23) including a microcomputer for sequentially tuning a plurality of channels at a predetermined cycle. 12. The signal reception apparatus according to claim 1, wherein the determination means (22) is included in the microcomputer, and when the period of the horizontal synchronization signal separated from the synchronization signal separation means (24) is within the allowable range from a predetermined period, the signal reception time is received. And a first determination signal for outputting the second determination signal for receiving a no-signal channel when out of the allowable range. 2. The clock signal generator P2 of claim 1, wherein the clock signal generating means comprises: a divider means 31 for dividing a frequency of an existing clock signal supplied from the reference clock signal source P2; A first OR gate 32 which takes a logical sum of the divided clock signal divided by the dividing means 31 and the selling signal from the finalizing means 22; and the reference clock signal from the reference clock signal source P2. And a second OR gate 34 which takes a logical sum of the inverted signal of the determination signal from the determination means 22 and an AND gate that takes a logic of the outputs of the first and second OR gates 32 and 34. And a multi-channel image display circuit.

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