JPH0681315B2 - Non-standard signal detection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal processing circuit of a television receiver, and particularly to a so-called non-standard which is different from an NTSC signal such as a special reproduction signal of a VDP (video disc player). Detect the signal,
The present invention relates to a non-standard signal detection circuit suitable for performing optimum signal processing.

[Conventional technology]

For NTSC signals, which is the current broadcasting system, various systems have been discussed for the signal processing technology of a digital television receiver aiming at high image quality by signal processing on the receiver side. As an example, "New research and development trends in Japan and abroad" by Achiha and 1 other person, Journal of the Television Society of Japan, Vol.36, No.10 (1982), PP9
31-944. Here, in order to improve the image quality, a spatio-temporal processing technology in which the time axis operation is added to the horizontal and vertical axes of the image is introduced. Furthermore, in addition to image quality improving means such as frame comb Y / C separation by this spatiotemporal processing, inter-field interpolation, and scanning line double speed conversion, the movement of the image is detected, and when the movement is a still image, The above-mentioned spatio-temporal processing is performed, and motion-adaptive signal processing is performed to adaptively switch to spatial processing such as line comb Y / C separation and intra-field interpolation that does not perform time-axis processing on a moving image. By this processing, it is possible to achieve higher image quality for so-called standard signals that conform to the NTSC signal standard such as normal broadcasting.

[Problems to be solved by the invention]

The above-mentioned prior art utilizes the fact that the burst signal phase is always in a predetermined phase relationship between frames or fields in space-time signal processing. Therefore, there is a problem that the so-called non-standard signal, in which the relationship of the burst signal phase is lost, may not provide the effect of the spatiotemporal processing and may cause image quality deterioration.

That is, in the case of an NTSC signal, the color subcarrier frequency f _SC ,
Between the horizontal scanning frequency f _H , the vertical scanning frequency f _V , and the frame frequency f _F , By utilizing the fact that the phase of the color subcarrier is opposite between frames, the frame comb Y / C separation circuit and the image movement detection circuit are processed by the interframe arithmetic processing of the input video signal. I am configuring.

However, in the case of a non-standard signal, the relationship of the above formula (1) does not hold.

For example, in home VDP, special playback (still image playback,
The special reproduction signal reproduced by double speed reproduction, slow reproduction, etc. has a discontinuous burst signal phase and can be said to be a kind of non-standard signal. At this discontinuity of the burst signal phase, an APC that generates the system clock in the conventional example that is phase-synchronized with the burst signal
(Automatic Phase Control) As a result of the circuit being out of synchronization, the system clock frequency is also disturbed until the phase is synchronized again. Therefore, for example, if the generated clock is selected to be four times the color subcarrier frequency f _SC , the above equation (1) can be written as As shown in the equation (2), the generated clock frequency is disturbed at the point where the burst signal phase becomes discontinuous as described above,
The formula (2) is not satisfied. Using the system clock of such an APC circuit, one frame as in the past = 910.525
When three-dimensional spatiotemporal processing such as frame comb Y / C separation, motion detection, and scanning line interpolation is performed by sequentially storing data in a frame memory composed of data, it is clear from equation (2) Correspondence of video data between fields becomes inaccurate, so that the above signal processing malfunctions.

As described above, there is a problem that the image quality is deteriorated by performing the image quality enhancement process of the conventional standard signal without considering the property of the input video signal.

An object of the present invention is to accurately detect, when a television signal having a discontinuous burst signal phase, such as a special reproduction signal of VDP, which is a kind of non-standard signal, is input, and to provide a circuit based on the input signal. It is an object of the present invention to provide a non-standard signal detection circuit that eliminates malfunctions and enables optimum image quality improvement signal processing.

[Means for solving problems]

The above purpose is the output from the phase comparison circuit in the APC (Automatic Phase Control) circuit (hereinafter referred to as the APC detection voltage).
And a second holding means for holding a predetermined reference value obtained from the detection result and a second holding means for holding a predetermined reference value, and comparing the outputs of these means. It is achieved by configuring a non-standard signal detection circuit with a comparison means for integrating and an integration means for integrating the output of this comparison means, and detecting the change state of the APC detection voltage within the vertical blanking period by this. It

[Action]

The output from the phase comparison circuit in the APC circuit is greatly disturbed at the point of discontinuity when a signal such as a VDP special reproduction signal having a discontinuous burst signal phase is input. The comparison means is for a vertical blanking period including the discontinuity point.
A value that holds the APC detection voltage is compared with a value that holds the APC detection voltage during the video period in which the APC circuit is in a steady state, or a preset fixed reference value is compared to determine a non-standard signal. Further, even if it is a non-standard signal, the disturbance of the APC detection voltage does not always occur in every vertical scanning cycle, and therefore the above-mentioned determination result is further given to the integrator circuit, and a constant non-standard signal unless the input signal changes. The detection result of is obtained. In this way, accurate non-standard signal detection is possible,
Image quality can be improved by appropriate signal processing.

〔Example〕

 An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, 101 is a burst gate pulse input terminal, 102 is a burst signal input terminal, 103 is a phase comparison circuit,
104 is a low pass filter (LPF), 105 is a voltage controlled crystal oscillator circuit (VCXO), 106 and 107 are gate circuits, 108 and 109 are peak value holding (peak / hold) circuits (P / H circuits), 110 Is a comparison circuit, 111 is an integration circuit, 112 is a control signal generation circuit, 11
3 is a horizontal sync pulse input terminal, 114 is a vertical sync pulse input terminal, and 115 is a non-standard signal output terminal. Further, a waveform diagram for explaining the operation of FIG. 1 is shown in FIG.

A PL including the phase comparison circuit 103, LPF 104, and VCXO 105 shown in FIG.
The L loop is the APC circuit of a conventional television receiver. In FIG. 2, the oscillation output signal (b) of the VCXO 105 is output by the phase comparison circuit 103 to the burst signal input terminal 102.
The phase of the burst signal (c) input from the device is compared with that of each burst period (a), and the phase detection signal (d) is output. That is, in the phase comparison circuit 103, when the oscillation output signal (b) of the VCXO 105 touches the + side, the burst signal (c) is gated to perform detection. Next, this phase detection signal (d) is converted by the LPF 104 into a phase error signal (e) in which only the DC component is extracted, and becomes a control signal for the VCXO 105.

In the state on the left side of FIG. 2, the burst signal (c) and VCXO10
The 5 oscillation output signals (b) are locked while maintaining a 90 ° phase difference from each other. However, when a VDP special reproduction signal or the like is input, the phase of the burst signal (c) becomes discontinuous during the vertical blanking period as shown in the right part of FIG. 2 (VDP special reproduction: In the vertical blanking period,
This is because the track jump of the reading spot is performed. ) Here, the dotted line portion of the burst signal (c) is a waveform having burst signal phase continuity in the standard state. In the phase discontinuous state, the phase detection signal (d) changes from the waveform on the left side to the disturbed waveform on the right side. This is because the APC circuit is in an asynchronous state due to phase discontinuity. After that, the oscillation frequency of the VCXO 105 changes due to the phase error signal (e), and after 10 to 20 horizontal scanning periods, the burst signal (c) again.
Since the operation returns to the state on the left side of FIG. 2 in synchronization with the APC circuit, the APC circuit becomes stable during the video period. Therefore, a non-standard signal can be detected by comparing the phase error signal (e) in the vertical blanking period and the video period.

This detection portion is changed from the gate circuit 106 of FIG. 1 to the integration circuit 111.
It consists of up to. The gate circuit 106 opens the gate for a predetermined period of the video period by the control pulse from the control signal generation circuit 112, and passes the phase error signal (e). P / H circuit 108
Holds the peak value of the phase error signal (e) from the gate circuit 106. On the other hand, the gate circuit 107 has a vertical blanking period,
Open the gate and use the P / H circuit 109 in the same way to output the phase error signal (e).
Holds the peak value of.

The values held by the P / H circuits 108 and 109 are input to the comparison circuit 110 as the peak value signals (f). Here, if the burst signal is continuous in phase, the peak value signals (f) from the P / H circuits 108 and 109 are input as shown in the left part of FIG. 2, but due to discontinuity, the APC circuit 2 is in an asynchronous state, the peak value signal (f) from the P / H circuit 109 is input as shown in the right part of FIG.

Therefore, in the comparison circuit 110, during the comparison pulse period from the control signal generation circuit 112, it is determined whether the peak value signals (f) of the two coincide or not, and the comparison result pulse (g) is output. Here, by selecting the comparison pulse period as a predetermined period near the end of one field, values in the same field can be compared with each other.

The above detection operation is performed for each field.
Since the burst signal phase becomes discontinuous once every two fields in VDP still reproduction, etc., even if the input video signal is a non-standard signal, the comparison result output in each vertical cycle of the comparison circuit 110 described above. Cannot be directly used as the determination result of the non-standard signal. Therefore, the integrating circuit 111 is connected to the subsequent stage of the comparing circuit 110 to detect the nonstandard signal as described above with high accuracy. In this way, the non-standard signal detection signal is sent to another signal processing circuit, and the signal processing corresponding to the non-standard signal is switched to prevent deterioration of image quality.

In the block diagram above, the AP during the vertical blanking period and the video period
The maximum value of the C detection voltage is compared by the comparison circuit 110, and at this time, the APC detection voltage during the video period during which the APC circuit is operating stably is used as the comparison reference. It is also possible to use a fixed value. In this case, instead of the gate circuit 106 and the P / H circuit 108 that operate to hold the APC detection voltage in the video period, a reference value setting circuit by resistance division or the like is used in the analog method.
In the digital method, a reference value setting circuit such as a binary switch circuit is used.

Next, the details of each part in FIG. 1 will be described.

FIG. 3 shows gate circuits 106 and 107 and P / H circuits 108 and 10.
9 is a circuit diagram showing details of 9. FIG.

In the figure, the emitter follower circuit composed of the transistor Q1 operates as an input buffer, and the phase error signal from the LPF 104 is input. Field effect transistor (hereinafter FE
T) Q2 operates as a switch and passes a signal when the control pulse of the control signal generation circuit 112 is applied to the gate electrodes of the FETs Q2 and Q3. The above is the configuration of the gate circuits 106 and 107.

Also, diodes D1 to D2, capacitors C1 to C2, FETs Q3 to Q
The circuit consisting of 6 is the P / H circuits 108 and 109. First, the diode D1 passes only the negative signal of the signal from the gate circuit 106 (107), and the peak value of the negative signal is the capacitor.
The held negative peak value is given to the comparison circuit 110 via the high input impedance source follower circuit which is held in C1 and is constituted by the FET Q5. Here, the held peak value is a reset signal from the control signal generation circuit 112, which makes the FET Q3 conductive and discharges the charge stored in the capacitor C1 and returns to the initial state. Similarly, the peak value of the positive polarity portion of the signal is held in the capacitor C2 by the diode D2, and the charging charge is discharged by the switching operation of the FET Q4. As described above, the P / H circuit 108 (109)
Both positive and negative peaks of the signal are retained.

Next, FIG. 4 shows details of the comparison circuit 110.

The negative and positive peak values of the video period obtained by the P / H circuit 108 and the negative and positive peak values of the vertical blanking period obtained by the P / H circuit 109. Is a comparator 401 and 4
A comparator output is obtained when the absolute value of the peak value input to each 02 is larger than the absolute value of the output of the P / H circuit 108. The outputs of the comparators 401 and 402 are divided by the resistors R401 to R404 and input to the OR circuit 403. The output of the OR circuit 403 is output through the AND circuit 404 only during the comparison pulse input period of the control signal generation circuit 112. In this way, when the amplitude of the phase error signal in the vertical blanking period is larger than that in the video period, that is, when the burst signal phase is discontinuous, the AND circuit 404 outputs a phase discontinuity detection pulse. .

Since the output of the comparator circuit 110 is the information indicating the discontinuity of the burst signal phase, a stable non-standard signal detection signal is obtained by the integrating circuit shown in FIG.

In FIG. 5, 501 and 502 are D type latch circuits, 503 is an AND circuit, 504 is a counter circuit with a count number N, 505 is a counter circuit with a count number M, 506 is an OR circuit,
507 is an RS flip-flop circuit.

The detection pulse of the burst signal phase discontinuity from the comparison circuit 110 is VCX by the D latch circuits 501 and 502 and the AND circuit 503.
The waveform is shaped into a pulse having a width of one clock of the oscillation clock of O105 and becomes the count clock of the N counter circuit 504. on the other hand,
The counting clock of the M counter circuit 505 is the P / H circuits 108 and 1
The reset signal (V _S pulse) that resets 09 every vertical scanning cycle is input, and the number of fields is counted M times. That is, when the number of times the phase discontinuity occurs occurs at a rate of N / M fields or more, the carry of the N counter circuit 504 is output and the RS flip-flop circuit 507 is set to the non-standard signal detection pulse. To the output terminal 115. Then, the carry of the N counter circuit 504 goes through the OR circuit 506, resets the respective counter circuits 504 and 505, and starts counting again. On the contrary, the N counter circuit 504
If the carry output of the M counter circuit 505 is obtained before the time is full, the RS flip-flop circuit 507 is reset and judged as the standard signal. Therefore, the threshold for non-standard signal detection is set when the phase discontinuity occurs with a probability of N / M or more, and the threshold can be set freely by appropriately changing the values of N and M, respectively.

As described above, the concrete examples of FIGS. 3 to 5 are the cases where the APC circuit of FIG. 1 is formed by a generally well-known analog circuit. Next, when the APC circuit is assembled by a digital circuit. , And the circuit of each part when the non-standard signal detection part is composed of all digital circuits will be described below.

FIG. 6 shows the gate circuit 106 (107) and the P / H circuit 108 (109) when the APC circuit is a digital circuit and the output of the LPF 104 is a digital value.

In the figure, 601, 605 and 606 are OR circuits, 602 to 604 are D latch circuits, and 607 and 608 are comparator circuits. LPF
The digital data from 104 is held in the D latch circuit 602 and given to the P / H circuit 108 (109). At this time, VCXO1
The latch clock sent from 05 is selected by the OR circuit 601 only during the gate pulse period from the control signal generation circuit 112. Therefore, the gate circuit 106 (107) is configured by the OR circuit 601 and the D latch circuit 602. The D latch circuit 603 holds the positive peak value of the phase error signal from the gate circuit 106 (107). This held data is stored in the gate circuit 106 (1
07) The data sent from the
The comparator circuit 607 receives the data of a value larger than the data held in the D latch circuit 603, and the OR circuit 60.
5 operates so that the latch clock is output, rewrites the latch contents of the D latch circuit 603, and holds the peak value. After that, when the reset signal is input, the held data is cleared, and the peak value in the next vertical scanning period is held again. Similarly, the D latch circuit 604, the OR circuit 606, and the comparator circuit 608 hold the negative peak value of the input signal. At this time, the comparator circuit 608 is the comparator circuit 6
Contrary to 07, when the input data is smaller than the held data, the control pulse is output.

The above is another specific example of the gate circuit 106 (107) and the P / H circuit 108 (109).

Next, FIG. 7 shows another specific example of the comparison circuit 110. 7th
The circuit shown is a continuation of the P / H circuit 108 (109) shown in FIG. The peak values of the positive polarity and the negative polarity of the video period and the vertical blanking period sent from the P / H circuits 108 and 109 are compared by the comparator circuits 701 and 702, and the burst signal phase discontinuity detection signal is OR circuit. If the signal is normal, the standard signal detection signal is output to the OR circuit 704. The OR circuits 703 and 704 take the sum of the positive and negative peak values to generate a detection pulse in the non-standard state or the standard state. The AND circuits 705 and 706 are gate circuits for generating the detection signal after the output results of the P / H circuits 108 and 109 are fixed and the comparison result is sufficiently stabilized. As described above, the AND circuit 705 outputs the non-standard state detection pulse, and the AND circuit 706 outputs the standard state detection pulse.

FIG. 8 shows another specific example of the integrating circuit 111. This integrator circuit 111 makes the detection pulse sent from the comparison circuit 110 as shown in FIG. 7 into a stable non-standard signal detection signal so that the signal processing of the digital television receiver can always be performed under the optimum conditions. I have to.

In FIG. 8, 801 is an N counter circuit and 802 is UP / down.
A counter circuit, 803 is an OR circuit, and 804 is an RS flip-flop circuit.

Of the non-standard / standard-state detection pulses obtained in FIG. 7, the standard-state detection pulse is input to the N counter circuit 801,
Weighting is performed so that a pulse is output once for N counts. By this processing, there was a deviation in the occurrence probability of the non-standard / standard state. This makes it easy to identify non-standard video signals. In addition, the weighted standard state detection pulse and non-standard state detection pulse are UP / down counter circuit 8
It is integrated by 02. The UP / down counter circuit 802 has an initial value i.
Is set, the count value is increased when the standard state detection pulse is input, and the count value is decreased when the non-standard state detection pulse is input. When the count value is i + j, the carry output is output, and when the count value is i−j, the borrow output is output, and each output passes through the OR circuit 803 to initialize the UP / down counter circuit 802 again. At this time, the set value i is read into the counter circuit 802. The carry output and borrow output of the up / down counter circuit 802 are connected to the reset input and the set input of the RS flip-flop circuit, respectively.
When the borrow output is output from the n counter circuit 802, the output of the RS flip-flop circuit 804 is at a high level, and a non-standard signal detection pulse is applied to the output terminal 115. The above is the description of the integrating circuit in FIG.

Next, a specific example of the control signal generating circuit 112 will be described with reference to FIG. In the figure, 901 to 904 and 908 are mono-multivibrators, 905 is an N shift register, 906 is an inverter, 90
7 is an AND circuit.

The mono multivibrator 901 has a vertical sync signal input terminal 114.
The trailing edge of the vertical synchronizing signal input from the device is used as a trigger to output the first pulse for a period determined by the time constants of resistance and capacitance. The trailing edge of this first pulse is set to coincide with the trailing edge of the vertical blanking interval (VBLK). Further, the mono-multivibrator 902 outputs the second pulse by using the trailing edge of the first pulse as a trigger. The inverted output of this second pulse is set to match the VBLK pulse. In this way, the VBLK pulse is created. In the same manner, the mono-multi vibrators 903 and 904 create a gate pulse that gates a predetermined period of the video period.

On the other hand, N shift register 905, everter 906, AND circuit 9
The differential circuit constituted by 07 obtains a differential pulse at the leading edge of the VBLK pulse, and this differential pulse serves as a reset signal for the P / H circuits 108 and 109. Also, Mono Multi Vibrator 908
Uses the trailing edge of the second pulse as a trigger to output a gate pulse to be supplied to the comparison circuit 110 until the VBLK pulse rises. The above is the first specific example of the control signal generation circuit 112.

FIG. 10 shows another specific example of the control signal generation circuit 112. In the figure, 1001 is an n-bit counter circuit, 1002 to 1006.
Is a level setting switch, 1007 to 1011 are comparators, and 1012 to 1014 are RS flip-flop circuits.

The counter circuit 1001 performs a counting operation using the vertical synchronizing signal as a reset pulse and the horizontal synchronizing signal as a clock. Comparators 1007 and 1008 are counter circuits 10
The count value from 01 is compared with the value set by the switches 1002 and 1003, and when they match, a pulse of one horizontal period is output and the RS flip-flop 1012 is operated to generate a gate pulse for a predetermined period of the video period. To do. Similarly, the switches 1004 and 1005, the comparators 1009 and 1010, and the RS flip-flop circuit 1014 generate VBLK pulses.
The RS flip-flop 1013 is a comparator 1007.
And 1010 are used to output the gate pulse for the comparison circuit 110 during the period from the trailing edge of the gate pulse to the leading edge of the VBLK pulse in the video period. Further, the comparator 1011 and the switch 1006 output a reset pulse to be given to the P / H circuits 108 and 109 during the horizontal period immediately before the VBLK pulse.

As described above, according to the present embodiment, by using the non-standard signal detection circuit of FIG. 1, it is possible to stably and easily detect a non-standard signal such that the burst signal phase becomes discontinuous. You can

In this embodiment, the LPF 104 is used in the non-standard signal detector and the APC part.
However, it is of course possible to provide them independently to increase the loop gain of the APC part and the detection sensitivity of non-standard signals.

FIG. 11 is a block diagram showing a nonstandard signal detection circuit as another embodiment of the present invention. In the figure, 1101 is the first
An LPF different from the LPF104 shown in the figure, 1102 is an absolute value circuit, 1103
Is a switching circuit, 1104 and 1105 are average value holding circuits, and others are the same as in FIG. Next, the operation of FIG. 11 will be described with reference to the waveform chart of FIG. In the waveform diagram of FIG. 2, the burst period is shown as a unit.
In the waveform diagram of FIG. 12, one vertical scanning period (1V) is shown as a unit.

The output of the phase comparison circuit 103 in the APC circuit shown in FIG. 1 is waved by the LPF 1101. The output waveform of LPF1101
It is shown in Fig. 12 (a). The signal in Fig. 12 (a) is the absolute value circuit 11
The absolute value is taken by 02 and becomes a signal like the waveform (a), and the switching circuit 1103 operates by the signal switching pulse (c) from the control signal generation circuit 112, and the vertical blanking period (VBLK). ) Is selected by the average value circuit 1104, and the average value circuit 1105 is selected during other periods.
Average value circuits 1104 and 1105 are switching circuits 1103, respectively.
Calculate the average value of the input signal level for the period selected in
The value is held for one vertical scanning period, the average value is again obtained in the next period, and the held contents are updated. The output (D) of the average value circuit 1104 and the output (E) of the average value circuit 1105 thus obtained are compared in size by the comparison circuit 110 to obtain a comparison result signal (F). The switching pulse (c) output from the control signal generation circuit 112 during the comparison period
Controlled by the switching pulse (c)
During the high level period, the comparison circuit 110 performs the comparison. The comparison result signal (f) thus obtained is an accurate nonstandard signal detection signal obtained by the integration circuit 111 similar to that shown in FIG.

FIG. 13 is a block diagram showing an example of a signal processing circuit portion of a digital television receiver using the nonstandard signal detection circuit according to the present invention.

In the figure, 1302 is an analog comb filter, and 1303,1
309, 1315, 1325, 1338 are switch circuits, 1304, 1319, 1320 are
A / D converter, 1305 is a motion detection circuit, 1306 and 1322 are frame comb filters, 1307 and 1323 are line comb filters, 1308, 1312, 1321 and 1324 are mixers, 1310 is a field interpolation filter, 1311, 1327 and 1330 are line interpolation filters,
1313,1328,1331 is double speed conversion circuit, 1314,1329,1332 is D / A
Converter, 1316 is bandpass filter, 1317 is ACC (Autom
atic Color Control) circuit, 1318 is a color subtone circuit, 1321 is a multiplexer, 1326 is a demultiplexer, 1336 is an OR circuit, and 1337 is a non-standard signal detection circuit according to the present invention. The operation of FIG. 13 will be described below.

When the television signal input from the input terminal 1301 is a non-standard signal, it passes through the analog comb filter 1302 and is separated into the luminance signal and the chrominance signal and input to the switches 1303 and 1315, respectively. It is directly input from the switch 1301 to the switches 1303 and 1315.

Hereinafter, the case of inputting a standard signal will be described. Input terminal 1301
The television signal directly input from the switch through the switch 1303 is digitized by the A / D converter 1304 and then input to the frame comb filter 1306 and the line comb filter 1307. Here, the frame comb filter 1306 performs luminance signal separation by calculation processing between frames, the line comb filter 1307 performs luminance signal separation by calculation processing between lines, and the mixer 1308 detects the motion detection circuit 1305. The outputs of the comb filters are mixed according to the amount of movement. The luminance signal thus obtained is passed through the switch 1309 and then the field interpolation filter 1310 and the line interpolation filter.
1311 and the double speed conversion circuit 1313. The output of the interpolation filter is mixed by the mixer 1312 according to the amount of motion as in the case of the comb filter to obtain an interpolation signal. The double speed conversion circuit 1313 at the next stage compresses the time axis in half and sequentially scans the interpolation signal and the actual television signal (hereinafter, actual signal). The brightness signal thus obtained is converted back into an analog signal by the D / A converter 1314, and a double speed sequential scan brightness signal is obtained at the output terminal 1333.

On the other hand, the color signal to be superimposed on the television signal input to the bandpass filter 1316 via the switch 1315 separates and extracts the multiplexed band, and after the color signal amplitude is corrected by the ACC circuit 1317, It is input to the color demodulation circuit 1318. The color demodulation circuit 1318 converts the color signals into (RY) and (B-
Y) The color difference signals are demodulated and the respective color difference signals are A / D
Feed converters 1319 and 1320. The A / D-converted color difference signals (RY) and (BY) are sequentially time-division-multiplexed by the multiplexer 1321 for each image sampling point. After that, this color signal is given to the frame comb filter 1322 and the line comb filter 1323, color signal extraction by interframe processing and color signal extraction by interline processing are performed, and the mixer 13
At 21, the outputs of the comb filters are mixed according to the amount of movement described above, and the color signal is extracted. The extracted color signal is input to the demultiplexer 1326 via the switch 1325, and the time-division multiplexed color difference signal is converted into the original color difference signal (R-
Y) and (BY). After that, interpolation signals are created by the line interpolation filters 1327 and 1330, and the respective color difference signals (RY) and (BY) are subjected to the double speed sequential scan conversion in the same manner as the luminance signal by the double speed conversion circuits 1328 and 1331, and D / A
Converted to analog signal with converter 1329 and 1332 and output terminal
Given to 1334 and 1335.

The above is the operation when the standard signal is input. Next, the operation when the non-standard signal is input will be described.

Non-standard signal detection circuit 1337 for detecting the discontinuity of the burst signal phase according to the present invention, or other non-standard detection circuit (a circuit for detecting a non-standard signal other than the non-standard signal detected by the non-standard signal 1337, for example, If a non-standard signal is detected by the VTR detection circuit, etc., the non-standard signal detection circuit
Output of 1337 or output of other non-standard detection circuit 1342
Is input to the OR circuit 1336. This allows the OR circuit 1336
Outputs detection signals for all non-standard signals. Each switch circuit is controlled by this detection signal, that is, the switch circuits 1303, 1309, 1325 are respectively switched to the lower side, and the switch circuits 1315, 1338 are respectively switched to the right side. As a result, the system clock 1341 changes from the clock 1339 from the APC circuit to the clock 1340 from the AFC circuit.
, And drive each circuit. The clock 1340 from the AFC circuit is synchronized with the horizontal synchronizing signal of the input signal. Therefore, even if there is no predetermined relationship between the color subcarrier and the luminance signal (the relationship of the above formula (1)), the interfield Since the positional relationship of the sampling pixels in is maintained, field interpolation is possible. As described above, the interpolating portion can perform the same operation as the standard time by using the system clock 1341 as the clock 1340 from the AFC circuit. On the other hand, in the case of comb filter processing, if the non-standard signal is processed with the clock 1340 from the AFC circuit, dot interference may occur in which the chrominance signal component leaks into the luminance signal. To the analog comb filter 1302 for processing. As described above, even if a non-standard signal is input, it can be detected and the circuit can be controlled so that optimum signal processing is performed.

As described above, even when a nonstandard signal such as a burst signal phase discontinuity such as a VDP special reproduction signal is input by using the present invention, it is possible to always provide a high quality image by optimal signal processing. it can.

〔The invention's effect〕

According to the present invention, it is possible to easily and accurately detect a non-standard signal that does not have the continuity of the color subcarrier phase. Therefore, such a non-standard signal is input to a digital television receiver. Even if it is carried out, there is an effect that the optimum signal processing can be performed and a higher quality image can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a non-standard signal detection circuit as one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is a gate circuit of FIG. FIG. 4 is a circuit diagram showing one specific example of the peak hold circuit, FIG. 4 is a circuit diagram showing one specific example of the comparison circuit of FIG. 1, and FIG. 5 is a circuit diagram showing one specific example of the integrating circuit of FIG. FIG. 6 is a circuit diagram showing another specific example of the gate circuit and the peak hold circuit of FIG.
FIG. 7 is a circuit diagram showing another specific example of the comparison circuit of FIG.
FIG. 8 is a circuit diagram showing another specific example of the integrating circuit of FIG.
9 is a circuit diagram showing a specific example of the control signal generating circuit of FIG. 1, FIG. 10 is a circuit diagram showing another specific example of the control signal generating circuit of FIG. 1, and FIG. 11 is a circuit diagram of the present invention. FIG. 12 is a block diagram showing another embodiment, FIG. 12 is a waveform diagram for explaining the operation of each part of FIG. 11, and FIG. 13 is a signal processing of a digital television receiver using the nonstandard signal detection circuit according to the present invention. It is a block diagram showing an example of a circuit part. 103 ... Phase comparator circuit, 104 ... LPF, 105 ... VCXO, 106, 107 ...
Gate circuits, 108, 109 ... Peak hold circuits, 110 ... Comparison circuits, 111 ... Integrator circuits, 112 ... Control signal generation circuits.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Sakamoto, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Electric Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Ichio Nakagawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa House number Incorporated company, Hitachi, Ltd. Home Appliances Research Laboratory (72) Inventor, Masahiko Achiha 1-280, Higashi Koigakubo, Kokubunji, Tokyo (56) References, Hitachi, Ltd. Central Research Laboratory (56) Reference JP-A-61-234189 (JP, A) Kai 63-276994 (JP, A)

Claims (3)

[Claims] 1. A phase comparison means for comparing the phases of the burst signal and the reproduced clock for each burst signal period in an input television signal, a filter for smoothing an output from the phase comparison means, and the filter. A variable frequency oscillating means for changing the oscillating frequency in accordance with the output from the device and outputting the oscillating output as the reproduced clock, and a clock reproducing means for reproducing a clock synchronized with the color subcarrier in the television signal. In the television receiver, the output from the phase comparison means smoothed by a filter is detected for a first predetermined period in one vertical scanning period of the television signal, and a predetermined result obtained from the detection result is detected. First holding means for holding a value, second holding means for holding a predetermined reference value, and the first and second holding means. Each of the held values is compared with each other to discriminate their magnitude, and a comparing means for outputting the discrimination result and an integrating means for integrating the output from the comparing means are included. A non-standard signal detection circuit, wherein an integrated output is output as a detection signal indicating whether or not the television signal is a non-standard signal. 2. The non-standard signal detection circuit according to claim 1, wherein the second holding means outputs the output from the phase comparing means smoothed by a filter in the television signal. A non-standard signal detection circuit, which detects during a second predetermined period other than the first predetermined period in one vertical scanning period and holds a predetermined value obtained from the detection result as the reference value. . 3. The non-standard signal detection circuit according to claim 1, wherein the second holding means holds a preset fixed value as the reference value. Signal detection circuit.