JPS60198973A - Vertical synchronizing signal detecting circuit - Google Patents

Abstract

PURPOSE:To make the titled circuit suitable for semiconductor circuit integration without generating malfunction due to noise by using a noise eliminating circuit, a trailing edge detecting circuit, a counter and a vertical synchronizing signal generating circuit and applying digital processing to a composite synchronizing signal so as to detect a vertical synchronizing signal. CONSTITUTION:When the composite synchronizing signal is inputted to the noise eliminating circuit 102 via an input terminal 101, a part of the noise is eliminated by the circuit 102 and the result is given to the trailing edge detecting circuit 104. The circuit 104 detects a trailing edge pulse of the composite synchronizing signal and its output is outputted to a control circuit 106. On the other hand, the composite synchronizing signal eliminated with noise is fed to the circuit 106 from the circuit 102. The circuit 106 resets the counter 115, measures the position of the trailing edge pulse by output signals 108-114 of the counter 115 so as to detect a horizontal synchronizing signal, an equivalent pulse and the vertical synchronizing signal, the counter 115 and the composite synchronizing signal are synchronized and the vertical synchronizing signal is generated (117).

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a vertical synchronization signal detection circuit used for video synchronization signal processing, and can be applied to the fields of reeds, televisions, VTRs, and video discs.

(Conventional configuration and its problems) A conventional vertical synchronization signal separation circuit consists of a differentiator, a filter,
It is composed of analog circuits such as multi-pipelines, and when converting these into a semiconductor integrated circuit, it is necessary to use a large chip area and create capacitive elements and resistive elements, or to use external capacitors and resistors. .

Also, since it is an analog circuit, noise countermeasures are troublesome.
It may malfunction.

(Objective of the Invention) The present invention eliminates the problems that existed in such conventional vertical synchronization signal separation circuits, provides a vertical synchronization signal detection circuit that is easy to integrate into a semiconductor integrated circuit, and is less likely to malfunction due to noise. It is something to do.

(Structure of the Invention) To summarize, the present invention includes a noise removal circuit to which a composite synchronization signal of a television synchronization signal is supplied, a falling edge detection circuit connected to the noise removal circuit, and a falling edge detection circuit connected to the noise removal circuit. A vertical synchronization signal detection circuit comprising a control circuit connected to a downstream edge detection circuit, a counter connected to the control circuit, and a vertical synchronization signal generation circuit also connected to the control circuit. , a simple configuration and good noise resistance can be realized.

(Description of Embodiment) FIG. 1 shows the overall system configuration of an embodiment of the present invention. ] 01 is an input terminal, 102 is a noise removal circuit, 103 is a composite synchronization signal line from which noise has been removed, 1
04 is a falling edge detection circuit, and 105 is a falling edge detection circuit.
Zorus supply line, 106 is a control circuit, 107 is a counter reset signal line, 108 is a Q, 25H signal line,
109 is the 075H signal line, 110 is the 0.45H signal line,
111 is a 0.55H signal line, 112 is a 0.95H signal line, 113 is an IH signal line, 114 is a 105H signal line, 11
5 is color/1, 16 is vertical synchronization signal generation signal line, 1
17j-jl are vertical synchronizing signal generation circuits, and 118 is a vertical synchronizing signal output terminal.

Next, its operation will be explained. Composite synchronization signal is input terminal 10
1 to the noise removal circuit 102. The noise removal circuit 102 removes part of the noise contained in the composite synchronization signal, and outputs the composite synchronization signal from which part of the noise has been removed to the falling edge detection circuit 104 via the signal line 103. Falling edge detection circuit 04 detects the falling edge pulse of the composite synchronizing signal and outputs it to the control circuit 106 via the falling edge pulse supply a105. Here, the falling edge pulse refers to a pulse corresponding to the falling edge of the composite synchronization signal, as shown in FIG. 3, which will be described later.

A counter reset signal is output from the control circuit 106 to the counter 115 via a counter reset signal line 107. On the other hand, from the counter 115 to the control circuit 106, 0.25H (
However, H is the period of the horizontal synchronizing signal) signal is the signal line]09
0.75) , the 1'H signal is sent via the signal line 113, and the 1'H signal is sent via the signal m114.
．． o5H signals are output respectively. Noise removal circuit 1
A composite synchronization signal from which noise has been removed is input from the signal line 103 to the control circuit 106 from the signal line 103. Control circuit 1.06 to vertical synchronization signal generation circuit 11
A vertical and vertical synchronizing signal generation signal is output to the signal line 116 to the signal line 116. The control circuit 106 is the counter 11
5 is reset, and the output signal 108 of the counter 115 is reset.
~114, measure the position of the falling edge/guru, detect the horizontal synchronization signal, equivalent edge, and vertical synchronization signal, synchronize the counter 115 with the composite synchronization signal, and detect the vertical synchronization signal. making it possible for it to occur.

The counter 115 is reset by the control circuit 106 to 0.25H, 0.75H, 0.45Hlo.
, 55H, 0095H, IH, LO5H signals)
Output to roll circuit 106.

The vertical synchronization signal generation circuit 117 has a built-in counter,
A vertical synchronization signal generation signal is inputted via a signal line 116, and a vertical synchronization signal with a constant period is outputted to an output terminal 118.

FIG. 2 shows a specific circuit configuration including the two functions of the noise removal circuit 102 and the falling edge detection circuit 104 shown in FIG. In the figure, 101 is an input terminal into which a composite synchronization signal is input, 103 is a composite synchronization signal line from which part of the noise has been removed, and 105 is a falling Sieno pulse supply line, all of which are the same as those shown in Figure 1. Yes, 2
o] is a clock/signal input terminal, which is supplied with a sufficiently higher frequency than the composite synchronizing signal, for example, a clock signal (not shown) on the order of several MHy, and is 202 to 201°2.
09.210 is D7, Book, Pu, 205-208.
211 is a NOR circuit.

FIG. 3 shows a timing chart of the circuit in FIG. 2, in which (a) shows the composite synchronization signal, (b) shows the output signal of the NOR circuit 205 in FIG. 2, and (c) shows the NOR circuit 205.
6 output signal, (d) is the NOR circuit 207+7) output signal (composite synchronization signal from which part of the noise at the terminal 103 has been removed), (e) is the output signal of the NOR circuit 211 (the falling terminal of 105) , )・Signal on the gurus supply line)
It shows.

The operation will be explained below with reference to FIGS. 2 and 3. Here, as shown in FIG. 3(a), the input terminal 101 receives the normal composite synchronization signal specified in (a) and one port).
The combination of a noise component with a period shorter than three times the period of the black, curus specified in (c) and a noise component with a period longer than three times the synchronization of the black, ri, and gurus specified in (c). Consider the case when a signal is supplied.

Under the above conditions, the output of the NOR circuit 205 is
Figure (b) K becomes K as shown. The output of the NOR circuit 206 is as shown in FIG. 3(c) VC. terminal 10
3, a signal as shown in FIG. 3(d) is output. In the signal of FIG. 3(d), the noise component shown in (b) which is shorter than the cycle of 7/FF2O3 is removed. A signal shown in FIG. 3(e) is output to the terminal IO5. At the terminal 165, the signal shown in (d) at the terminal 103 is connected to the rising edge of the signal shown in (d) at the terminal 103, from which noise components that are shorter than three times the cycle of the (→) signal shown in (a) are removed. The lower 9th pulse signal is output.As shown above, the noise removal circuit 102 and the falling edge detection circuit remove the noise component whose period is three times shorter than the period of the clock pulse of the composite synchronization signal. Then, the falling signal is detected and the falling signal is output.

FIG. 4 shows a specific circuit configuration of the control circuit 106 in FIG. 1. 401°403.40 in the diagram
8,417 is RS Frinopflotso, 404-406,
409,416.418 D frig 70 horns, 402
,410,412,414゜4-19 ,420 is AN
D circuit, 4'07, 411゜415.421 is an OR circuit, 413, 422 is an inverter circuit The AND circuit 402 receives the 4.010Q output of the RS flip 11 flop and the falling shear and no pulses from the signal line 105.
．． A falling signal between 45H and 0.55H is output, and this is converted to R'S Frisoge70) 7' 4 '0
Supplied to the set terminal (S) of No.3. D Furitsunofuro 1f
404 to 406 are RS flip-flops for holding the output level of the flip-flop 403 for a period of three times the output of the AND circuit 410 and setting the R87 logic flag a7f403Vc').

Therefore, 7" flop 403 of RS flip is 045H and 0
It is set by a falling edge pulse during 55H, and this state is maintained for three pulse periods of the output ie pulse of the AND circuit 410.

Next, the RS Furi, Gflo, G408 is set with a 0.95H signal via the signal m112, and the 1,05H signal supplied from the signal line 114 and the D
It is reset by either Furi, Zofro, or Pu418 output/Gurus. The D-flinogfronoso 418 is a circuit for synchronizing the output of the AND circuit 410 to prevent malfunction. D Free Ruff 0 Fu 0. No. 409 is a circuit for synchronizing the outputs of the RS Frizzoflo and f408 to prevent malfunctions, and outputs a signal synchronized with the clock signal to the AND circuit 410. The output of the D free flag 409 and the falling edge pulse are input to the AND circuit 410 . Therefore, the AND circuit 410 combines the 0.95H signal and the 10H signal.
Outputs a falling signal between the 5H signal and the 5H signal. 0
．． The falling edge pulse between the 95H signal and the 1.05H signal corresponds to the horizontal synchronization component, and the output of the AND circuit 410 is only the falling edge pulse corresponding to the horizontal synchronization signal. .

To summarize the above, RS Furi and Zofro 70403 are:
A falling transition/e pulse corresponding to the equivalence/relance between the 0.45H signal and the 0.55H signal is detected. This circuit was designed with a permissible range of variation in the period of the equivalent/Grus component of the input composite synchronization signal being 0.45H to 0.55H. AND circuit 4] 0 is 0.95H and 1.0
Falling edge corresponding to the horizontal synchronization component during 5H 4
Detect responses.

The OR circuit 41 is supplied with a 025H signal via a signal line 108 and a 0.75H signal via a signal line 109, respectively. Three signals are input to the AND circuit 412: the output of the OR circuit 411, the inverted composite synchronization signal from the impairing circuit 422, and the output of the RS Frizzo Frozzo 403. Only when the composite synchronization signal is low level, the 025H signal or 0
．． Outputs /4' pulse of 75H signal. Therefore, signal line 1
16, the 025H signal or 075 signal is detected only when the equivalent signal is detected and the high level of the composite synchronization signal is detected.
An H signal is output.

The AND circuit 414 includes D-Furi, Pflo, f 409
The inverted output of 0) and the noise-removed composite synchronous signal falling edge F/, are input, and the falling edge between O)I and 0.95H is output to the OR circuit 415. O
A 1.05H signal is also input to the R circuit 415, and outputs the falling edge, no morno, and 1.05H signals excluding the falling Sieno pulse corresponding to the horizontal synchronization component. D free,
The clock lodges 416 and 418 are circuits to synchronize and prevent malfunctions, and output the input signals in synchronization with the clocks, registers, and clocks.

RS flip flop 417 is D flip flop 7
'418, set by the falling sea edge corresponding to the horizontal synchronization component, D frizzo float f41
It is reset by a falling edge pulse other than the falling edge pulse corresponding to the horizontal synchronization component via 6 and a 1.05H signal. In other words, RS frig-flo f417 is
It is set when the falling edge corresponding to the horizontal synchronization component is detected, and the falling edge corresponding to the noise component is detected.
It is reset by the 05H signal, which corresponds to the loss of signal and horizontal synchronization component. The output of the RS Flinoflotz f417 indicates whether the circuit is synchronized to the input composite sync signal.

The AND circuit 419 has ζ of the RS flip-flop 417.
Output and counter 115 ]H signal output and AND circuit 41
Three signals with an output of 0 are input, and the circuit outputs a falling slope signal corresponding to the horizontal synchronization component when the circuit is synchronized with the input composite synchronization signal.

AND circuit 420 has RS function, Gutsulodge 4]7's ζ
Falling edges and pulses are input via output and signal lines 105, and outputs all falling edges and pulses when the circuit is not synchronized with the input composite synchronization signal. The OR circuit 421 receives the outputs of the AND circuits 419 and 420, and outputs a counter reset signal to the signal line 07. Therefore, when the circuit is synchronized with the input composite synchronization signal, the signal m107 outputs a falling edge corresponding to the horizontal synchronization component, and on the other hand, when the circuit is synchronized with the input composite synchronization signal, If not, all falling Etsuno/F pulses are output.

FIG. 5 shows a specific circuit configuration of the counter 115 in FIG. 1. In the figure, 501ViO, 25H
, 0,45H, 0,55H, 0,75H.

502 is a 0, 05H period kakunta that counts each signal from IH to 105H, 503 is D-Furi, Gutsulodge, and 504 is RS-Furi, F0Flo.

505 is an AND circuit.

The reason why two counters 501 and 502 are used here is to determine the next horizontal synchronization component after the missing horizontal synchronization component when the horizontal synchronization component is missing due to noise in the composite synchronization signal. This is because the counter needs to be reset at the IH cycle. On the other hand, when generating a horizontal synchronization component, the period of the input horizontal synchronization component is normally IH, but since the period fluctuates, it is necessary to make it slower than the maximum one. Otherwise, the horizontal synchronization component will be generated before the input horizontal synchronization component is detected. In this circuit, the allowable range of variation in the period of the horizontal synchronization component is 0.
The design was carried out as 95H to 105H.

The counter 501 is reset by a counter reset signal via the counter signal input signal 107. If the circuit is synchronized to the input composite sync signal, 095H and 1
The falling edges and pulses between 05H and the IH double signal are reset, and if they are not synchronized, they are reset at all falling edges and pulses. The power rank 502 starts counting the IH multiplication signal of the counter 501, and the signal is 0.95.
Counting is stopped/zoomed at the falling edge pulse and the 1.05H signal between the H and 1.05H signals.

FIG. 6 shows a specific circuit configuration of the vertical synchronization signal generation circuit 117, and 601 is an RS
02 is a 3H counter, and 603 is an inverter circuit.

RS 71J knob flow, 7'601d, is set by the vertical synchronization signal generation signal outputted from the control circuit 106 via the signal line 116.

When RS Furi, Pflo, and f601 are reset, 3H
When the reset of the counter 602 is removed and the counter starts counting and counts for 3H period, the 3H output of the 3H counter 602 (Jl/S, RS Furi, fFlo, Zorro 01 are set, 3H power 9 The printer 602 strikes,
76. Therefore, the vertical synchronizing signal generating circuit shown in FIG. 6 outputs a signal having a width of 3H to the vertical synchronizing signal output terminal 118 when the vertical synchronizing signal generating signal is output from the control circuit. This circuit was designed with the pulse width of the vertical synchronization signal being 3H.

The above is an explanation of this embodiment, but when this circuit is not synchronized with the input composite synchronization signal, the counter is reset L at every falling esono signal, and between 0.95H and 1.05H. The falling edge and no pulse corresponding to a certain horizontal synchronization component are detected, and the counter is reset by the detected /response to synchronize with the input composite synchronization signal. When this circuit and the input composite synchronization signal are synchronized, circuit asynchronization is detected by the 1 and 05H signals corresponding to the falling edge, jump, and horizontal synchronization components that are not present between 095H and 105H. hand,
Reset the counter at the next downhill, Sopulse. Therefore, after detecting non-synchronization, when a falling Sieno response is detected between the 0.95H and 105H signals, the circuit becomes synchronous again. This circuit malfunctions when two or more noises occur in succession, and it operates normally even if one noise occurs between horizontal synchronization components or one horizontal synchronization component is missing.

In addition, the vertical synchronization signal is generated by detecting the equivalent signal and adjusting the level of the input composite synchronization signal to the Q, 25H signal or 0.
The design is such that a vertical synchronization signal is not generated when a 0 equivalent iE pulse is not detected, which is determined based on the position of the 75H signal. The vertical synchronization component is detected based on the level of the input composite synchronization signal. If there is a vertical synchronization component, the level of the composite synchronization signal is inverted, so the 0.25H signal or 075H signal
Determine the level of the input composite synchronization signal based on the position of the signal. The reason why the level is determined at two points, the 025H signal and the 075H signal, is that the position of the vertical synchronization component is shifted by 0.5H period from the position of the horizontal synchronization component in the odd and even fields.

(Effects of the Invention) As explained above, according to the present invention, a vertical synchronization signal can be detected from a composite synchronization signal by denotal processing, does not malfunction due to noise, and is configured with a denotal circuit. This eliminates the need for capacitors and resistors, making it suitable for semiconductor integration.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a concrete circuit diagram of a noise removal circuit and a falling transition detection circuit, and FIG. The time charts of the circuit, FIG. 4, FIG. 5, and FIG. 6 are specific circuit diagrams of the control circuit, counter, and vertical synchronization signal generation circuit, respectively. Downhill. Detection circuit, 106... Control circuit, 1]5 Counter, 117... Vertical synchronization signal generation circuit. 4 Figure 1U

Claims (1)

[Claims] A noise removal circuit that is supplied with a composite synchronization signal of the video I#j synchronization signal and that removes part of the noise included in the falling edge of the composite synchronization signal; A falling edge detection circuit for separating falling edges, the noise removal circuit and the falling edge. a control circuit that detects the equivalent signal and the vertical synchronization signal component by obtaining the output signal of the signal detection circuit; A vertical synchronization signal detection circuit comprising: a kakunta that supplies a component detection signal to the control circuit; and a vertical synchronization signal generation circuit that is controlled by the control circuit and generates a signal of a constant period. .